U6083B

Features • • • • • Pulse-width Modulation up to 2 kHz Clock Frequency Protection Against Short-circuit, Load Dump Overvoltage and Reverse VS Duty Cycle 18% to 100% Continuously Internally Reduced Pulse Slope of Lamp’s Voltage Interference and Damage Protection According to VDE 0839 and ISO/TR 7637/1 • Charge-pump Noise Suppression • Ground-wire Breakage Protection 1. Description The U6083B is a PWM IC in bipolar technology for the control of an N-channel power MOSFET used as a high-side switch. The IC is ideal for use in brightness control systems (dimming) of lamps, for example, in dashboard applications. PWM Power Control IC with Interference Suppression U6083B Rev. 4770B–AUTO–09/05 Figure 1-1. Block Diagram with External Circuit VS 1 5 C5 Rsh 6 VBatt Current monitoring + short circuit detection C1 4 RC oscillator PWM Logic Control input Charge pump 7 C3 47 nF 8 47 kΩ 3 Duty cycle reduction GND 2 Output C2 Duty cycle range 18 to 100% Voltage monitoring Slew rate control 150 Ω R3 Ground 2 U6083B 4770B–AUTO–09/05 U6083B 2. Pin Configuration Figure 2-1. Pinning DIP8 1 2 3 4 OUTPUT 2 VS SENSE DELAY VS GND VI OSC 8 7 6 5 Table 2-1. Pin 1 2 3 4 5 6 7 8 Pin Description Symbol VS GND VI OSC DELAY SENSE 2 VS OUTPUT Function Supply voltage VS IC ground Control input (duty cycle) Oscillator Short-circuit protection delay Current sensing Voltage doubler Output 3 4770B–AUTO–09/05 3. Functional Description 3.1 3.1.1 3.1.1.1 Pin 1, Supply Voltage, VS or VBatt Overvoltage Detection Stage 1 I f overvoltages of V Batt > 2 0V (typically) occur, the external transistor is switched off, and switched on again at VBatt < 18.5V (hysteresis). 3.1.1.2 Stage 2 If VBatt > 28.5V (typically), the voltage limitation of the IC is reduced from VS = 26V to 20V. The gate of the external transistor remains at the potential of the IC ground, thus producing voltage sharing between FET and lamps in the event of overvoltage pulses (e.g., load dump). The shortcircuit protection is not in operation. At VBatt approximately < 23V, the overvoltage detection stage 2 is switched off. Thus, during overvoltage detection stage 2, the lamp voltage Vlamp is calculated as follows: VLamp = VBatt – VS – VGS VS = supply voltage of the IC at overvoltage detection stage 2 VGS = gate - source voltage of the FET 3.1.2 Undervoltage Detection In the event of voltages of approximately VBatt < 5.0V, the external FET is switched off and the latch for short-circuit detection is reset. A hysteresis ensures that the FET is switched on again at approximately VBatt ≥ 5.4V. 3.2 3.2.1 Pin 2, GND Ground-wire Breakage To protect the FET in the case of ground-wire breakage, a 1 MΩ resistor between gate and source is recommended to provide proper switch-off conditions. 3.3 Pin 3, Control Input The pulse width is controlled by means of an external potentiometer (47 kΩ). The characteristic (angle of rotation/duty cycle) is linear. The duty cycle can be varied from 18 to 100%. It is possible to further restrict the duty cycle with the resistors R1 and R2 (see Figure 7-1 on page 11). In order to reduce the power dissipation of the FET and to increase the lifetime of the lamps, the IC automatically reduces the maximum duty cycle at pin 8 if the supply voltage exceeds V2 = 13V. Pin 3 is protected against short-circuit to VBatt and ground (VBatt ≤ 16.5V). 4 U6083B 4770B–AUTO–09/05 U6083B 3.4 Pin 4, Oscillator The oscillator determines the frequency of the output voltage. This is defined by an external capacitor, C2. It is charged with a constant current, I, until the upper switching threshold is reached. A second current source is then activated which taps a double current, 2 × I, from the charging current. The capacitor, C2, is thus discharged at the current, I, until the lower switching threshold is reached. The second source is then switched off again and the procedure starts once more. 3.4.1 Example for Oscillator Frequency Calculation Switching thresholds VT100 VT100 VT