U6813B

Features • • • • • • • Digital Self-supervising Watchdog with Hysteresis One 150-mA Output Driver for Relay One High-side Driver for N-channel Power FET Positive and Negative Enable Output Positive and Negative Reset Output Over/Under-voltage Detection Relay and Power FET Outputs Protected Against Standard Transients and 55-V Load Dump 1. Description The function of microcontrollers in safety-critical applications (e.g., anti-lock systems) needs to be monitored permanently. Usually, this task is accomplished by an independent watchdog timer. The monolithic IC U6813B, designed in bipolar technology and qualified according to the needs of the automotive industry, includes such a watchdog timer and provides additional features for added value. With the help of integrated driver stages, it is easy to control safety-related functions of a relay and of an N-channel power MOSFET in high-side applications. In case of a microcontroller malfunction or supply-voltage anomalies, the U6813B provides positive and negative reset and enable output signals. This flexibility guarantees a broad range of applications. The U6813B is based on of Atmel’s fail-safe ICs U6808B and U6809B. Fail-safe IC with High-side and Relay Driver U6813B Rev. 4543B–AUTO–10/05 Figure 1-1. Block Diagram VCC Bandgap reference 2.44 V Power-on reset Reset delay fosc 3 P-RES 3.3 V 16 Reset debounce fosc 3.3-V under- and overvoltage detect. 4 N-RES 1 VCC 14 RELO Current limitation VCC 5-V under- and overvoltage detect. 6 N-EN RELI 13 19k FETI 12 19k Watchdog WDI 11 19k Internal oscillator fosc RCoscillator supervisor V CC 5 P-EN 9 RC oscillator FET output 7 FETO VS 15 SGND 2 GND 10 WDC 8 CAPI 2 U6813B 4543B–AUTO–10/05 U6813B 2. Pin Configuration Figure 2-1. Pinning SO16 RELO GND P-RES N-RES P-EN N-EN VS CAPI 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 3.3V SGND VCC RELI FETI WDI WDC FETO Table 2-1. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Description Symbol RELO GND P-RES N-RES P-EN N-EN VS CAPI FETO WDC WDI FETI RELI VCC SGND 3.3V Description Open-collector output driver Supply Digital output Digital output Digital output Digital output Battery supply Analog input Power FET output Analog input Digital input Digital input Digital input Supply Supply Analog input Function Fail-safe relay driver General ground Positive reset signal Negative reset signal Positive enable signal Negative enable signal Voltage for charge pump Input bootstrap capacitor High voltage for N-channel FET External RC for watchdog timer Watchdog trigger signal Activation of power FET Activation of relay driver 5-V supply Sense ground, reference for VCC and 3.3 V 3.3-V supply Pulse sequence FET on: H Driver on: H Reset: H Reset: L Enable: H Enable: L Type Driver on: L 3 4543B–AUTO–10/05 3. Fail-safe Functions A fail-safe IC has to maintain its monitoring function even if there is a fault condition at one of the pins (e.g., short circuit), ensuring that a microcontroller system does not reach a “critical status”. A critical status means, for example, if the system is not able to switch off the relay or disable the power MOSFET, or if the system is not able to provide a signal to the microcontroller via ENABLE- and RESET-outputs in the case of a fault condition. The U6813B is designed to handle those fault conditions according to Table 3-1 for a maximum of system safety. Table 3-1. VCC ok ok ok ok ok x wrong Notes: Truth Table 3.3V ok ok ok ok ok wrong x WDI ok ok ok ok wrong x x RELI H L (1) FETI x x H L (1) RELO on off x x off off off FETO x x on off off off off N-RES H H H H H L L P-RES L L L L L H H P-EN(2) H H H H L L L N-EN(3) L L L L H H H x x x x x x x x 1. default state at open input 2. P-EN disable: low 3. N-EN disable: high 4. Watchdog Description Figure 4-1. Watchdog Block Diagram WDC Binary counter Dual MUX WDI Slope detector Up/down counter RS-FF WD-OK RESET OSCERR The microcontroller is monitored by a digital window watchdog which accepts an incoming trigger signal of a constant frequency for correct operation. The frequency of the trigger signal can be varied in a broad range as the watchdog’s time window is determined by external R/C components. The following description refers to the watchdog timing diagram with tolerances (see Figure 4-2 on page 5). 4 U6813B 4543B–AUTO–10/05 U6813B 4.1 WDI Input (Pin 11) The microcontroller has to provide a trigger signal with the frequency fWDI which is fed to the WDI input. A positive edge of fWDI detected by a slope detector resets the binary counter and clocks the up/down counter.The latter one counts only from 0 to 3 or reverse. Each correct trigger increments the up/down counter by 1, each wrong trigger decrements it by 1. As soon as the counter reaches status 3, the RS flip-flop is set; see Figure 4-3 (Watchdog state diagram). A missing incoming trigger signal is detected after 250 clocks of the internal watchdog frequency fRC (see WD_OK output) and resets the up/down counter directly. 4.2 WDC Input (Pin 10) It is to be equiped by external R/C components. By means of an external R/C circuitry, the IC generates a time base (frequency fWDC) independent from the microcontroller. The watchdog’s time window refers to a frequency of fWDC = 100 × fWDI. 4.3 OSCERR Input A smart watchdog has to ensure that internal problems with its own time base are detected and do not lead to an undesired status of the complete system. If the RC oscillator stops oscillating, a signal is fed to the OSCERR input after a time-out delay. It resets the up/down counter and disables the WD-OK output. Without this reset function, the watchdog would freeze its current status when fRC stops. 4.4 RESET Input During power-on and under/overvoltage detection, a reset signal is fed to this pin. It resets the watchdog timer and sets the initial state. 4.5 WD-OK Output After the up/down counter has reached to status 3 (see Figure 4-3, Watchdog State Diagram), the RS flip-flop is set and the WD-OK output becomes logic “1”. As WD-OK is directly connected to the enable pins, the open-collector output P-EN provides also logic “1” while a logic “0” is available at N-EN output. If on the other hand the up/down counter is decremented to “0”, the RS flip-flop is reset, the WD-OK output and the P-EN output are logic “0” and N-EN output is logic “1”. The WD-OK output also controls a dual MUX stage which shifts the time window by one clock after a successful trigger, thus forming a hysteresis to provide stable conditions for the evaluation of the trigger signal “good or false”. The WD-OK signal is also reset in case the watchdog counter is not reset after 250 clocks (missing trigger signal). Figure 4-2. Time/s Watchdog Timing Diagram with Tolerances 79/ fWDC 80/ fWDC 169/ fWDC 170/ fWDC 250/ fWDC 251/ fWDC Watchdog Window update rate is good Update rate is too fast Update rate is either too fast or good Update rate is either too slow or good Update rate is too slow Update rate is either too slow or pulse has dropped out Pulse has dropped out 5 4543B–AUTO–10/05 Figure 4-3. Watchdog State Diagram good Initial status bad bad O/F bad good 1/F good bad 2/F good 1/NF bad bad 3/NF 2/NF good good 4.6 Explanation In each block, the first character represents the state of the counter. The second notation indicates the fault status of the counter. A fault status is indicated by an “F” and a no-fault status is indicated by an “NF”. When the watchdog is powered up initially, the counter starts at the 0/F block (initial state). “Good” indicates that a pulse has been received whose width resides within the timing window. “Bad” indicates that a pulse has been received whose width is either too short or too long. 4.7 Watchdog Window Calculation Example with recommended values Cosc = 6.8 nF (should be preferably 10%, NPO) Rosc = 36 kΩ (can be 5%, Rosc < 200 kΩ due to leakage current and humidity) RC oscillator tWDC (s) = 10-3 [Cosc (nF) [(0.00078 Rosc (kΩ)) + 0.0005]] fWDC (Hz) = 1/(tWDC) Watchdog WDI fWDI (Hz) = 0.01 fWDC tWDC = 200 µs → fWDC = 5 kHz fWDI = 50 Hz → tWDI = 20 ms WDI pulse width for fault detection after 3 pulses: Upper watchdog window Minimum: 169/ fWDC = 33.8 ms→ fWDC/169 = 29.55 Hz Maximum: 170/ fWDC = 34 ms → fWDC/170 = 29.4 Hz Lower watchdog window Minimum: 79/ fWDC = 15.8 ms → fWDC/79 = 63.3 Hz Maximum: 80/ fWDC = 16 ms → fWDC/80 = 62.5 Hz 6 U6813B 4543B–AUTO–10/05 U6813B WDI dropouts for immediate fault detection: Minimum: 250/ fWDC = 50.0 ms Maximum: 251/ fWDC = 50.2 ms Remarks to reset relay The duration of the over- or undervoltage pulses determines the enable- and reset outputs. A pulse duration shorter than the debounce time has no effect on the outputs. A pulse longer than the debounce time results in the first reset delay. If a pulse appears during this delay, a second delay time is triggered. Therefore, the total reset delay time can be longer than specified in the data sheet. 5. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage range Power dissipation VS = 5V; Tamb = –40°C VS = 5V; Tamb = 125°C Junction temperature Ambient temperature range Storage temperature range Symbol VS Ptot Ptot Tj Tamb Tstg Value –0.2 to +26 250 150 150 –40 to +125 –55 to +155 Unit V mW mW °C °C °C 6. Thermal Resistance Parameters Junction ambient Symbol RthJA Value 110 Unit K/W 7 4543B–AUTO–10/05 7. Electrical Characteristics VCC = 5V, Tamb = –40 to +125°C; reference pin is GND or SGND (over- and under-voltage detection); fintern = 200 kHz +50%/–45%, fWDC = 5 kHz ±10%; fWDI = 50 Hz, bootstrap capacitor CBoot = 47 nF at pin CAPI No. 1 1.1 Parameters Supply Operation-voltage range Operation-voltage range of RESET outputs Current consumption Digital Input WDI Detection low Detection high Internal pull-down resistor Input current low Input current high Digital Input RELI Detection low Detection high Internal pull-down resistor Input current low Input current high Digital Input FETI Detection low Detection high Internal pull-down resistor Input current low Input current high Input voltage = 0V Input voltage = 5V 12 12 12 12 12 VFETI VFETI RINT12 IFETI IFETI –0.2 0.7 × VCC 10 –5 100 0.3 × VCC VCC + 0.2V 40 5 550 V V kΩ µA µA A A A A A Input voltage = 0V Input voltage = 5V 13 13 13 13 13 VRELI VRELI RINT13 IRELI IRELI –0.2 0.7 × VCC 10 –5 100 0.3 × VCC VCC + 0.2V 40 5 550 V V kΩ µA µA D D A A A Input voltage = 0V Input voltage = 5V 11 11 11 11 11 VWDI VWDI RINT11 IWDI IWDI –0.2 0.7 × VCC 10 –5 100 0.3 × VCC VCC + 0.2V 40 5 550 V V kΩ µA µA D D A A A V = 5.25V, Relay on Tamb = –40° C Tamb = +125° C 14 VCC VCC 4.5 5.5 V D Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 1.2 14 1.1 18.0 V A 1.3 2 2.1 2.2 2.3 2.4 2.5 3 3.1 3.2 3.3 3.4 3.5 4 4.1 4.2 4.3 4.4 4.5 Note: 14 ICC ICC 15 10 mA mA A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 1. If VS > 26 V the current has to be limited at 5 mA by an external resistor. 8 U6813B 4543B–AUTO–10/05 U6813B 7. Electrical Characteristics (Continued) VCC = 5V, Tamb = –40 to +125°C; reference pin is GND or SGND (over- and under-voltage detection); fintern = 200 kHz +50%/–45%, fWDC = 5 kHz ±10%; fWDI = 50 Hz, bootstrap capacitor CBoot = 47 nF at pin CAPI No. 5 5.1 5.2 5.3 5.4 6 6.1 6.2 6.3 6.4 6.5 7 7.1 7.2 7.3 7.4 7.5 8 8.1 8.2 8.3 8.4 8.5 Parameters Saturation voltage low Leakage current Reset debounce time (switch to low) Reset delay (switch back to high) Saturation voltage high Leakage current Internal pull-down resistor Reset debounce time (switch to low) Reset delay (switch back to high) Saturation voltage high Leakage current Internal pull-down resistor Enable debounce time (switch to low) Enable delay (switch back to high) Saturation voltage high Leakage current Internal pull-up resistor Enable debounce time (switch to high) Enable delay (switch back to low) Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Digital Output N-RES (Open Collector) Ireset ≤ 2.5 mA at 5V, high state Over- or undervoltage Over- or undervoltage 4 4 4 4 VSAT4 ILEAK4 tDEB4 tDEL4 120 320 50 0.5 0.5 500 V µA µs ms A A A A Digital Output P-RES (Internal Pull-down Resistor) Ireset ≤ 0.3 mA at 0V, low state at 5V Over- or undervoltage Over- or undervoltage 3 3 3 3 3 VSAT3 ILEAK3 RINT3 tDEB3 tDEL3 25 120 320 50 VCC– 0.5V VCC 0.5 100 500 V µA kΩ µs ms A A A A A Digital Output N-EN (with Open Collector and Internal Pull-down Resistor) I ≤ 1 mA at 0V, low state at 5V Over- or undervoltage Over- or undervoltage 6 6 6 6 6 VSAT6 ILEAK6 RINT6 tDEB6 tDEL6 25 120 320 85 VCC – 0.5V VCC 0.5 100 500 V µA kΩ µs ms A A A A A Digital Output P-EN (Internal Pull-up Resistor) I ≤ 3 mA at 5V, high state at 0V Over- or undervoltage Over- or undervoltage 5 5 5 5 5 VSAT5 ILEAK5 RINT5 tDEB5 tDEL5 12.5 120 320 85 0.5 0.5 50 500 V µA kΩ µs ms A A A A A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. If VS > 26 V the current has to be limited at 5 mA by an external resistor. 9 4543B–AUTO–10/05 7. Electrical Characteristics (Continued) VCC = 5V, Tamb = –40 to +125°C; reference pin is GND or SGND (over- and under-voltage detection); fintern = 200 kHz +50%/–45%, fWDC = 5 kHz ±10%; fWDI = 50 Hz, bootstrap capacitor CBoot = 47 nF at pin CAPI No. 9 9.1 9.2 9.3 9.4 9.5 10 10.1 10.2 10.3 10.4 10.5 10.6 11 11.1 11.2 11.3 12 12.1 12.2 12.3 12.4 12.5 13 13.1 13.2 13.3 13.4 13.5 13.6 Note: Parameters Relay Driver (RELO) Saturation voltage Current limitation Internal clamping voltage Turn-off energy Leakage current VBatt = 16V VBatt = 26V at 25°C I ≤ 150 mA 1 1 1 1 1 ILEAK1 ILEAK1 VS + 10V 9 20 26 VSAT1 ILIM VCL 0.1 150 26 30 20 200 VS + 15V 20 24 30 200 10 0.5 300 30 V mA V mJ µA µA A A A C A Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Power-FET Output FETO (Maximum Load Capacitor at FET Gate 470 pF, Charge-pump Frequency 110 to 300 kHz) Output voltage Operation range Overvoltage shutdown Internal clamping voltage On/off frequency Maximum current Battery Supply Internal clamping voltage Clamping current capability(1) Leakage current Reset and VCC Control Lower reset level Upper reset level Hysteresis Reset debounce time Reset delay Reset and 3.3V Control Lower reset level Upper reset level Hysteresis Reset debounce time Reset delay Current Reference SGND Reference SGND 16 16 16 16 16 16 V3.3V V3.3V VHYST16 tDEB16 tDEL16 I3.3V 2.97 3.47 15 120 20 320 50 3.13 3.63 70 500 80 0.5 V V mV µs ms mA A A A A A C Reference SGND Reference SGND 14 14 14 14 14 VCC VCC VHYST14 tDEB tDEL 4.5 5.25 25 120 20 320 50 4.75 5.5 100 500 80 V V mV µs ms A A A A A at FETI = low 7 7 7 VCL IVS ILEAVS 26 5 100 30 V mA µA A A A FETO VS = 9V to 15V 9 7 7 9 9 9 VOUT9 VS VS VCL f IFETO V V V V Hz µA A A A A A A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 1. If VS > 26 V the current has to be limited at 5 mA by an external resistor. 10 U6813B 4543B–AUTO–10/05 U6813B 7. Electrical Characteristics (Continued) VCC = 5V, Tamb = –40 to +125°C; reference pin is GND or SGND (over- and under-voltage detection); fintern = 200 kHz +50%/–45%, fWDC = 5 kHz ±10%; fWDI = 50 Hz, bootstrap capacitor CBoot = 47 nF at pin CAPI No. 14 14.1 15 15.1 15.2 Parameters RC Oscillator WDC Oscillator frequency Watchdog Timing Power-on-reset prolongation time Detection time for RC-oscillator fault Time interval for over/under-voltage detection Reaction time of reset output at over/under voltage Nominal frequency for WDI Nominal frequency for WDC Minimum pulse duration for a guaranteed WDI input-pulse detection Frequency range for a correct WDI signal Number of incorrect WDI trigger counts for locking the outputs Number of correct WDI trigger counts for releasing the outputs Detection time for a stucked WDI signal Minimum pulse duration for a guaranteed WDI input-pulse detection Frequency range for a correct WDI signal Hysteresis range at the WDI ok margins Detection time for a stucked WDI signal (WDI dropout) VWDI = constant 250 80 1 VWDI = constant fWDC = 5 kHz fRC = 100 fWDI fWDI = 1/100 fWDC VCR = constant tPOR tRCerror tD,OUV 34.3 81.9 103.1 246 ms ms A A ROSC = 36 kΩ COSC = 6.8 nF 10 fWDC 4.5 5 5.5 kHz A Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 15.3 0.16 0.64 ms A 15.4 tR,OUV fWDI fWDC 0.187 0.72 ms A 15.5 15.6 10 1 65 6.5 Hz kHz D D 15.7 fWDC = 5 kHz tP,WDI 364 µs A 15.8 fWDC = 5 kHz fWDI nlock 32.35 56.25 Hz D 15.9 3 A 15.10 nrelease tWDIerror 49 3 A 15.11 16 51 ms A Watchdog Timing Relative to fWDC 2 cycles A 16.1 16.2 16.3 170 cycles cycle D A 16.4 251 cycles A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. If VS > 26 V the current has to be limited at 5 mA by an external resistor. 11 4543B–AUTO–10/05 8. Protection Versus Transient Voltages According to ISO TR 7637-1 Level 4 (Except Pulse 5) Pulse 1 2 3a 3b 5 Note: Voltage –110V +110V –160V +150V 55V Source Resistance(1) 10Ω 10Ω 50Ω 50Ω 2Ω Rise Time 100V/s 100V/s 30V/ns 20V/ns 10V/ms Duration 2 ms 0.05 ms 0.1 µs 0.1 µs 250 ms Amount 15.000 15.000 1h 1h 20 1. In the case of the relay driver, the coil resistance of Rmin = 150Ω has to be added to the source resistance. 9. Timing Diagrams Figure 9-1. Watchdog in Too-fast Condition Normal operationWDI too fast 5V WDI 0V VBatt RELO 0V VBatt FETO 0V 5V P-EN 0V 5V N-EN 0V Don't care 14195 Normal operation 12 U6813B 4543B–AUTO–10/05 U6813B Figure 9-2. Watchdog in Too-slow Condition Normal operation 5V WDI 0V VBatt RELO 0V VBatt FETO 0V 5V P-EN 0V 5V N-EN 0V Don't care 14196 WDI too slow Normal operation Figure 9-3. Overvoltage Condition Overvoltage condition > 120 µs 5V >5.5 V < 120 µs >5.5 V V CC 0V V Batt RELO 0V V Batt FETO 0V 5V P-EN 0V 5V N-EN 0V 5V N-RES 0V 5V P-RES 0V Reset debounce time 1st Reset delay 2nd Reset delay 3 good WDI pulses Don't care 13 4543B–AUTO–10/05 Figure 9-4. Undervoltage Condition Undervoltage condition > 120 µs 5V