U6815BM-NFLG3Y

Features • Six High-side and Six Low-side Drivers • Outputs Freely Configurable as Switch, Half Bridge, or H-bridge • Capable to Switch All Kinds of Loads Such as DC Motors, Bulbs, Resistors, Capacitors and Inductors 0.6A Continuous Current Per Switch Low-side: RDSon < 1.5Ω Versus Total Temperature Range High-side: RDSon < 2.0Ω Versus Total Temperature Range Very Low Quiescent Current IS < 20 µA in Standby Mode Outputs Short-circuit Protected Overtemperature Prewarning and Protection Under- and Overvoltage Protection Various Diagnosis Functions Such as Shorted Output, Open Load, Overtemperature and Power Supply Fail • Serial Data Interface • Daisy Chaining Possible • SO28 Power Package • • • • • • • • Dual Hex DMOS Output Driver with Serial Input Control U6815BM 1. Description The U6815BM is a fully protected driver interface designed in 0.8-µm BCDMOS technology. It is used to control up to 12 different loads by a microcontroller in automotive and industrial applications. Each of the 6 high-side and 6 low-side drivers is capable of driving currents up to 600 mA. The drivers are freely configurable and can be controlled separately from a standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors, capacitors, and inductors can be combined. The IC design especially supports the applications of H-bridges to drive DC motors. Protection is guaranteed for short-circuit conditions, overtemperature, under- and overvoltage. Various diagnostic functions and a very low quiescent current in standby mode enable a wide range of applications. The U6815BM has automotive qualification for conducted interferences, EMC protection, and 2-kV ESD protection. 4545D–BCD–04/09 Figure 1-1. Block Diagram HS1 15 HS2 13 HS3 12 HS4 3 HS5 2 HS6 28 Fault detector Fault detector Fault detector Fault detector Fault detector Fault detector 5 VS 10 DI 26 VS 25 S C T O L D H S 6 L S 6 H S 5 L S 5 H S 4 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R 6 OV protection 7 VS Osc GND GND CLK S I VS CS 24 Input Register Ouput Register 17 Control logic L S 6 H S 5 L S 5 H S 4 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 T P UV protection 8 GND 9 GND INH P S F I N H S C D H S 6 Thermal protection Power ON Reset VCC 20 GND 21 GND 22 GND 23 GND 19 DO 18 Fault detector Fault detector Fault detector Fault detector Fault detector Fault detector VCC 16 LS1 14 LS2 11 LS3 4 LS4 1 LS5 27 LS6 VCC 2 U6815BM 4545D–BCD–04/09 U6815BM 2. Pin Configuration Figure 2-1. Pinning SO28 HS6 28 LS6 27 DI 26 CLK 25 CS 24 GND GND GND GND VCC 23 22 21 20 19 DO 18 INH 17 LS1 16 HS1 15 U6815BM Lead frame 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LS5 HS5 HS4 LS4 VS GND GND GND GND VS LS3 HS3 HS2 LS2 Table 2-1. Pin 1 2 3 4 5 6, 7, 8, 9 10 11 12 13 14 15 16 17 18 19 20, 21, 22, 23 24 25 26 27 28 Pin Description Symbol LS5 HS5 HS4 LS4 VS GND VS LS3 HS3 HS2 LS2 HS1 LS1 INH DO VCC GND CS CLK DI LS6 HS6 Function Low-side driver output 5, power-MOS open drain with internal reverse diode, overvoltage protection by active zenering, short-circuit protection, diagnosis for short and open load High-side driver output 5, power-MOS open drain with internal reverse diode, overvoltage protection by active zenering, short-circuit protection, diagnosis for short and open load High-side driver output 4 (see pin 2) Low-side driver output 4 (see pin 1) Power supply output stages HS4, HS5, HS6, internal supply; external connection to pin 10 necessary Ground, reference potential, internal connection to pin 20 to 23, cooling tab Power supply output stages HS1, HS2 and HS3 Low-side driver output 3 (see pin 1) High-side driver output 3 (see pin 2) High-side driver output 2 (see pin 2) Low-side driver output 2 (see pin 1) High-side driver output 1 (see pin 2) Low-side driver output 1 (see pin 1) Inhibit input, 5-V logic input with internal pull down, low = standby, high = normal operating Serial data output, 5-V CMOS logic level tristate output for output (status) register data, sends 16-bit status information to the microcontroller (LSB is transferred first). Output will remain tristated unless device is selected by CS = low, therefore, several ICs can operate on one data output line only. Logic supply voltage (5V) Ground (see pins 6 to 9) Chip select input, 5-V CMOS logic level input with internal pull-up, low = serial communication is enabled, high = disabled Serial clock input, 5-V CMOS logic level input with internal pull-down, controls serial data input interface and internal shift register (fmax = 2 MHz) Serial data input, 5-V CMOS logic level input with internal pull-down, receives serial data from the control device, DI expects a 16-bit control word with LSB being transferred first Low-side driver output 6 (see pin 1) High-side driver output 6 (see pin 2) 3 4545D–BCD–04/09 3. Functional Description 3.1 Serial Interface Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and is accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) must be transferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, Pin DO is in tristate condition. This output is enabled on the falling edge of CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is transferred first. Figure 3-1. CS Data Transfer DI SRR 0 LS1 1 HS1 2 LS2 3 HS2 4 LS3 5 HS3 6 LS4 7 HS4 8 LS5 9 HS5 10 LS6 11 HS6 12 OLD 13 SCT 14 SI 15 CLK DO TP SLS1 SHS1 SLS2 SHS2 SLS3 SHS3 SLS4 SHS4 SLS5 SHS5 SLS6 SHS6 SCD INH PSF Table 3-1. Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Input Data Protocol Input Register SRR LS1 HS1 LS2 HS2 LS3 HS3 LS4 HS4 LS5 HS5 LS6 HS6 OLD SCT SI Function Status register reset (high = reset; the bits PSF, SCD and overtemperature shutdown in the output data register are set to low) Controls output LS1 (high = switch output LS1 on) Controls output HS1 (high = switch output HS1 on) See LS1 See HS1 See LS1 See HS1 See LS1 See HS1 See LS1 See HS1 See LS1 See HS1 Open-load detection (low = on) Programmable time delay for short circuit and overvoltage shutdown (short-circuit shutdown delay high/low = 100 ms/12.5 ms, overvoltage shutdown delay high/low = 15 ms/3.5 ms Software inhibit; low = standby, high = normal operation (data transfer is not affected by standby function because the digital part is still powered) 4 U6815BM 4545D–BCD–04/09 U6815BM After power-on reset, the input register has the following status: Bit 15 (SI) H Bit 14 (SCT) H Bit 13 (OLD) H Bit 12 (HS6) L Bit 11 (LS6) L Bit 10 (HS5) L Bit 9 (LS5) L Bit 8 (HS4) L Bit 7 (LS4) L Bit 6 (HS3) L Bit 5 (LS3) L Bit 4 (HS2) L Bit 3 (LS2) L Bit 2 (HS1) L Bit 1 (LS1) L Bit 0 (SRR) L Table 3-2. Bit 0 1 Output Data Protocol Output (Status) Register TP Status LS1 Function Temperature prewarning: high = warning (overtemperature shut down)(1) Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off) Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off) Description see LS1 Description see HS1 Description see LS1 Description see HS1 Description see LS1 Description see HS1 Description see LS1 Description see HS1 Description see LS1 Description see HS1 Short circuit detected: set high, when at least one output is switched off by a short-circuit condition Inhibit: this bit is controlled by software (bit SI in input register) and hardware inhibit (pin 17). High = standby, low = normal operation Power supply fail: over- or undervoltage at pin VS detected 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Note: Status HS1 Status LS2 Status HS2 Status LS3 Status HS3 Status LS4 Status HS4 Status LS5 Status HS5 Status LS6 Status HS6 SCD INH PSF 1. Bit 0 to 15 = high: overtemperature shutdown 5 4545D–BCD–04/09 4. Power Supply Fail In the event of over or undervoltage at pin VS, an internal timer is started. When the overvoltage delay time (tdOV) programmed by the SCT Bit or the undervoltage delay time (tdUV) is reached, the power-supply fail bit (PSF) in the output register is set and all outputs are disabled. When normal voltage is present again, the outputs are immediately enabled. The PSF bit remains high until it is reset by the SRR bit in the input register. 5. Open-load Detection If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and a pull-down current for each low-side switch is turned on (open-load detection current IHS1-6, ILS1-6). If VVS – VHS1-6 or VLS1-6 is lower than the open-load detection threshold (open-load condition), the corresponding bit of the output in the output register is set to high. Switching on an output stage with OLD bit set to low disables the open-load function for this output. 6. Overtemperature Protection If the junction temperature exceeds the thermal prewarning threshold, TjPW set, the temperature prewarning bit (TP) in the output register is set. When temperature falls below the thermal prewarning threshold TjPW reset, the bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word: with CS = high to low, the state of TP appears at Pin DO. After the microcontroller has read this information, CS is set high and the data transfer is interrupted without affecting the state of input and output registers. If the junction temperature exceeds the thermal shutdown threshold Tj switch off, the outputs are disabled and all bits in the output register are set high. The outputs can be enabled again when the temperature falls below the thermal shutdown threshold, Tj switch on, and when a high has been written to the SRR bit in the input register. Thermal prewarning and shutdown threshold have hysteresis. 7. Short-circuit Protection The output currents are limited by a current regulator. Current limitation takes place when the over-current limitation and shutdown threshold (IHS1-6, ILS1-6) are reached. Simultaneously, an internal timer is started. The shorted output is disabled during a permanent short when the delay time (t dSd ) programmed by the Short-Circuit Timer (SCT) bit is reached. Additionally, the Short-Circuit Detection (SCD) bit is set. If the temperature prewarning bit TP in the output register is set during a short, the shorted output is disabled immediately and SCD bit is set. By writing a high to the SRR bit in the input register, the SCD bit is reset and the disabled outputs are enabled. 7.1 Inhibit There are two ways to disable the U6815BM: 1. Set bit SI in the input register to zero 2. Switch Pin 17 (INH) to 0V In both cases, all output stages are turned off but the serial interface stays active. The output stages can be activated again by bit SI = 1 or by pin 17 (INH) switched back to 5V. 6 U6815BM 4545D–BCD–04/09 U6815BM 8. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All values refer to GND pins. Parameters Supply voltage Supply voltage, t < 0.5s; IS > –2A Supply voltage difference Supply current Supply current, t < 200 ms Logic supply voltage Input voltage Logic input voltage Logic output voltage Input current Output current Output current Output voltage Reverse conducting current (tpulse = 150 µs) Junction temperature range Storage temperature range Pins 5, 10 5, 10 |VS_Pin5 – VS_Pin10| 5, 10 5, 10 19 17 24 to 26 18 17, 24 to 26 18 1 to 4, 11 to 16 27, 28 2, 3, 12, 13, 15, 28 1, 4, 11, 14, 16, 27 2, 3, 12, 13, 15, 28 towards 5, 10 Symbol VVS VVS ΔVVS IVS IVS VVCC VINH VDI, VCLK, VCS VDO IINH, IDI, ICLK, ICS IDO ILS1 to ILS6 IHS1 to IHS6 HS1 to HS6 LS1 to LS6 IHS1 to IHS6 Tj Tstg Value –0.3 to +40 –1 150 1.4 2.6 –0.3 to +7 –0.3 to +17 –0.3 to VVCC + 0.3 –0.3 to VVCC + 0.3 –10 to +10 –10 to +10 Internally limited (see output specification) –0.3 to +40 17 –40 to +150 –55 to +150 Unit V V mV A A V V V V mA mA mA mA V A °C °C 9. Thermal Resistance All values refer to GND pins Parameters Junction - pin, measured to GND, Pins 6 to 9 and 20 to 23 Junction ambient Symbol RthJP RthJA Value 25 65 Unit K/W K/W 10. Operating Range All values refer to GND pins Parameters Supply voltage Logic supply voltage Logic input voltage Serial interface clock frequency Junction temperature Notes: 1. Threshold for undervoltage detection 2. Output disabled for VVS > VOV (threshold for overvoltage detection) Pins 5, 10 19 Symbol VVS VVCC Min. VUV (1) Typ. 5 Max. 40 (2) Unit V V V MHz °C 4.5 –0.3 5.5 VVCC 2 17, 24 to VINH, VDI, VCLK, VCS 26 25 fCLK Tj –40 +150 7 4545D–BCD–04/09 11. Noise and Surge Immunity Parameters Conducted interferences Interference suppression ESD (human body model) ESD (machine model) Note: 1. Test pulse 5: VSmax = 40V Test Conditions ISO 7637-1 VDE 0879 Part 2 MIL-STD-883D Method 3015.7 EOS/ESD - S 5.2 Value level 4 (1) level 5 2 kV 150V 12. Electrical Characteristics 7.5V < VVS < 40V; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. Parameters Current Consumption Quiescent current (VS) Quiescent current (VCC) Supply current (VS) normal operating Supply current (VCC) Internal Oscillator Frequency Frequency (time-base for delay timers) Over- and Undervoltage Detection, Power-on Reset Power-on reset threshold Power-on reset delay time Undervoltage detection threshold Undervoltage detection hysteresis Undervoltage detection delay Overvoltage detection threshold Overvoltage detection hysteresis Overvoltage detection delay Overvoltage detection delay Thermal Prewarning and Shutdown Thermal prewarning, set Thermal prewarning, reset Thermal prewarning hysteresis Thermal shutdown, off Thermal shutdown, on Thermal shutdown hysteresis Notes: 1. Only valid for version U6815BM-N. 2. Delay time between rising edge of CS after data transmission and switch-on output stages to 90% of final level. TjPWset TjPWreset ΔTjPW Tj switch off Tj switch on ΔTj switch off 150 130 125 105 145 125 20 170 150 20 190 170 165 145 °C °C K °C °C K Pins 5, 10 Pins 5, 10 Input register, Bit 14 (SCT) = high Input register, Bit 14 (SCT) = low Pin 19 After switching on VVCC Pins 5, 10 Pins 5, 10 VVCC tdPor VUV ΔVUV tdUV VOV ΔVOV tdOV tdOV 7 1.75 7 18 1 21 5.25 3.4 30 5.5 0.4 21 22.5 3.9 95 4.4 160 7.0 V µs V V ms V V ms ms fOSC 19 45 kHz VVS < 16V, INH or bit SI = low Pins 5, 10 4.5V < VVCC < 5.5V, INH or bit SI = low, pin 19 VVS < 16V, pins 5, 10 all output stages off All output stages on, no load 4.5V < VVCC < 5.5V, normal operating, pin 19 IVS IVCC IVS IVS IVCC 0.8 40 20 1.2 10 150 µA µA mA mA µA Test Conditions/Pins Symbol Min. Typ. Max. Unit 8 U6815BM 4545D–BCD–04/09 U6815BM 12. Electrical Characteristics (Continued) 7.5V < VVS < 40V; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. Parameters Ratio thermal shutdown, off/thermal prewarning, set Ratio thermal shutdown, on/thermal prewarning, reset Output Specification (LS1 to LS6, HS1 to HS6), 7.5V < VVS < VOV On resistance, low On resistance, high Output clamping voltage IOut = 600 mA, Pins 1, 4, 11, 14, 16 and 27 IOut = –600 mA, Pins 2, 3, 12, 13, 15 and 28 ILS1–6 = 50 mA, Pins 1, 4, 11, 14, 16, 27 VLS1–6 = 40V, all output stages off, Pins 1, 4, 11, 14, 16 and 27 VHS1–6 = 0V, all output stages off, Pins 2, 3, 12, 13, 15 and 28 Pins 1-4, 11-16, 27 and 28 Pins 1-4, 11-16, 27 and 28 Pins 1, 4, 11, 14, 16 and 27 Pins 2, 3, 12, 13,15 and 28 Input register, bit 14 (SCT) = high Input register, bit 14 (SCT) = low Input register, bit 13 (OLD) = low, output off, pins 1, 4, 11, 14, 16, 27 Input register, bit 13 (OLD) = low, output off, pins 2, 3, 12, 13, 15, 28 RDS On L RDS On H VLS1–6 ILS1–6 IHS1–6 Woutx dVLS1–6/dt dVHS1–6/dt ILS1–6 IHS1–6 tdSd tdSd ILS1–6 IHS1–6 ILS1–6/ IHS1–6 Input register, bit 13 (OLD) = low, output off, pins 1, 4, 11, 14, 16, 27 Input register, bit 13 (OLD) = low, output off, pins 2, 3, 12, 13, 15, 28 RLoad = 1 kΩ RLoad = 1 kΩ VLS1–6 VVS– VHS1–6 tdon tdoff 0.3 × VVCC 0.7× VVCC 100 10 700 80 50 650 –1250 70 8.75 60 –150 1.2 0.6 0.6 4 4 0.5 1 V V ms ms 200 950 –950 100 –10 15 400 1250 –650 140 17.5 200 –30 40 1.5 2.0 60 10 Ω Ω V µA µA mJ mV/µ s mA mA ms ms µA µA Test Conditions/Pins Symbol Tj switch off/ TjPW set Tj switch on/ TjPW reset Min. 1.05 1.05 Typ. 1.17 1.2 Max. Unit Output leakage current Inductive shutdown energy(1) Output voltage edge steepness Overcurrent limitation and shutdown threshold Overcurrent shutdown delay time Open-load detection current Open-load detection current ratio Open-load detection threshold Output switch on delay (2) Inhibit Input Input voltage low level threshold Input voltage high level threshold Hysteresis of input voltage Pull-down current Notes: Pin 17 Pin 17 Pin 17 VINH = VVCC, pin 17 VIL VIH ΔVI IPD V V mV µA 1. Only valid for version U6815BM-N. 2. Delay time between rising edge of CS after data transmission and switch-on output stages to 90% of final level. 9 4545D–BCD–04/09 12. Electrical Characteristics (Continued) 7.5V < VVS < 40V; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. Parameters Test Conditions/Pins Symbol Min. 0.3 × VVCC 0.7 × VVCC 50 2 –50 500 50 –2 0.5 VVCC – 1V –10 10 Typ. Max. Unit Serial Interface - Logic Inputs (DI, CLK, CS) Input voltage low level threshold Input voltage high level threshold Hysteresis of input voltage Pull-down current, Pins DI and CLK Pull-up current Pin CS Serial Interface - Logic Output (DO) Output voltage low level Output voltage high level Leakage current (tristate) Notes: IOL = 3 mA, pin 18 IOL = –2 mA, pin 18 VCS = VVCC, 0V < VDO < VVCC, pin 18 VDOL VDOH IDO V V mA Pins 24 to 26 Pins 24 to 26 Pins 24 to 26 VDI, VCLK = VVCC, pins 25, 26 VCS= 0V, pin 24 VIL VIH ΔVI IPDSI IPUSI V V mV µA µA 1. Only valid for version U6815BM-N. 2. Delay time between rising edge of CS after data transmission and switch-on output stages to 90% of final level. 13. Serial Interface – Timing Parameters DO enable after CS falling edge DO disable after CS rising edge DO fall time DO rise time DO valid time CS setup time CS setup time VDO < 0.2 × VVCC Input register, Bit 14 (SCT) = high Input register, Bit 14 (SCT) = low Test Conditions CDO = 100 pF CDO = 100 pF CDO = 100 pF CDO = 100 pF CDO = 100 pF Timing Chart No.(1) 1 2 – – 10 4 8 9 9 5 6 – 7 3 11 12 Symbol tENDO tDISDO tDOf tDOr tDOVal tCSSethl tCSSetlh tCSh tCSh tCLKh tCLKl tCLKp tCLKSethl tCLKSetlh tDIset tDIHold 225 225 140 17.5 225 225 500 225 225 40 40 Min. Typ. Max. 200 200 100 100 200 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CS high time CLK high time CLK low time CLK period time CLK setup time CLK setup time DI setup time DI hold time Note: 1. see Figure 13-1 on page 11 10 U6815BM 4545D–BCD–04/09 U6815BM Figure 13-1. Serial Interface Timing Diagram with Chart Numbers 1 2 CLK DO 9 CS 4 CLK 7 5 3 6 8 DI 11 CLK 10 12 DO Inputs DI, CLK, CS: High level = 0.7 × VCC, Low level = 0.3 × VCC Output DO: High level = 0.8 × VCC, Low level = 0.2 × VCC For chart numbers, see Table “Serial Interface – Timing” on page 10. 11 4545D–BCD–04/09 Figure 13-2. Application Circuit M U5021M Watchdog Enable HS1 15 HS2 13 HS3 12 HS4 3 HS5 2 HS6 28 VS BYT41D VS 10 26 DI 25 CLK S C T O L D H S 6 L S 6 H S 5 L S 5 H S 4 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R VS 6 GND 7 VS GND 8 GND 9 Thermal protection Power ON Reset VCC GND 20 GND 21 GND 22 GND Fault detector Fault detector Fault detector Fault detector Fault detector Fault detector Reset Trigger Fault detector Fault detector Fault detector Fault detector Fault detector Fault detector 5 VBatt + VS 13V Osc S I OV protection Microcontroller 24 CS 17 INH 18 DO Input Register Ouput Register Control logic L S 6 H S 5 L S 5 H S 4 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 T P UV protection P S F I N H S C D H S 6 23 GND 19 VCC VCC VCC VCC VCC 16 LS1 14 LS2 11 LS3 4 LS4 1 LS5 27 LS6 + 5V M VS VS M 14. Application Notes It is strongly recommended to connect the blocking capacitors at VCC and VS as close as possible to the power supply and GND pins. Recommended value for capacitors at VS: Electrolythic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. Value for electrolytic capacitor depends on external loads, conducted interferences, and reverse conducting current IHSx (see table Absolute Maximum Ratings). Recommended value for capacitors at VCC: Electrolythic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF. To reduce thermal resistance, it is recommended to place cooling areas on the PCB as close as possible to the GND pins. 12 U6815BM 4545D–BCD–04/09 U6815BM 15. Ordering Information Extended Type Number U6815BM-NFLY U6815BM-NFLG3Y Package SO28 SO28 Remarks Tubed, Pb-free Taped and reeled, Pb-free 16. Package Information Package SO28 Dimensions in mm 18.05 17.80 9.15 8.65 7.5 7.3 2.35 0.4 1.27 28 16.51 15 0.25 0.10 0.25 10.50 10.20 technical drawings according to DIN specifications 1 14 17. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4545D-BCD-04/09 History • Put datasheet in a new template • Absolute Maximum Ratings table changed • • • • Put datasheet in a new template Pb-free logo on page 1 added New heading rows on Table “Absolute Maximum Ratings” on page 7 added Table “Ordering Information” on page 13 changed 4545C-BCD-09/05 13 4545D–BCD–04/09 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support auto_control@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. 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