U7006B-MLBG3

Features • • • • • • • Single 3-V Supply Voltage High Power-added Efficient Power Amplifier (Pout typically 26.5 dBm) Ramp-controlled Output Power Low-noise Preamplifier (NF typically 1.8 dB) Biasing for External PIN Diode T/R Switch Current-saving Standby Mode Few External Components Electrostatic sensitive device. Observe precautions for handling. DECT SiGe Front End IC with High PAE U7006B Description The U7006B is a monolithic SiGe transmit/receive front end IC with power amplifier, 50-W i nternal matching, low-noise amplifier and T/R switch driver. It is especially designed for operation in TDMA systems like DECT. Due to the ramp-control feature and a very low quiescent current, an external switch transistor for VS is not required. Figure 1. Block Diagram VS_PA V1_PA PA PA_IN RAMP LNA LNA_IN TX/RX Standby control T/R Switch driver SWITCH_OUT V2_PA_OUT LNA_OUT RX_ON PU R_SWITCH 4714A–DECT–07/03 1 Pin Configuration Figure 2. Pinning PSSO16 R_SWITCH SWITCH_OUT 1 16 PU 2 15 RX_ON GND1 3 14 LNA_OUT LNA_IN V1_PA 4 13 GND2 U7006B 5 12 VS_LNA V2_PA_OUT 6 11 PA_IN V2_PA_OUT 7 10 RAMP V2_PA_OUT 8 9 VS_PA Pin Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol R_SWITCH SWITCH_OUT GND1 LNA_IN V1_PA V2_PA-OUT VS_PA RAMP PA_IN VS_LNA GND2 LNA_OUT RX_ON PU Function Resistor to GND sets the PIN diode current Switched current output for PIN diode Ground Low-noise amplifier input Inductor to power supply for power amplifier Inductor to power supply and matching network for power amplifier output Supply voltage for power amplifier Power-ramping control input Power amplifier input Supply-voltage input for low-noise amplifier Ground Low-noise amplifier output RX active high Power-up active high 2 U7006B 4714A–DECT–07/03 U7006B Absolute Maximum Ratings All voltages refer to GND (Pins 3 and slug), ESD protection according to ESD-S5.2-1994, Class M1. Parameters Supply voltage; pins 6, 10, 13 and 16 (no RF) Junction temperature Storage temperature Input power PA, Pin 11 Input power LNA, Pin 4 Symbol VS Tj Tstg PinPA PinLNA Value 5 150 -40 to +125 +10 -5 Unit V °C °C dBm dBm Thermal Resistance Parameters Junction ambient Symbol RthJA Value 30 Unit K/W Operating Range All voltages refer to GND (Pins 3, 13 and slug). The following table represents the sum of all supply currents depending on the TX/RX mode. Power supply points are VS_LNA, VS_PA, V1_PA, V2_PA_OUT. Parameters Supply voltage pins 5, 6, 7, 8 and 9 Supply voltage pin 12 Supply current TX RX Standby current PU = 0 Ambient temperature Symbol VS VS IS IS IS Tamb -25 Min. 2.7 2.7 Typ. 3 3.6 350 8 10 +25 +70 Max. 4.6 4.6 Unit V V mA mA µA °C Electrical Characteristics Test conditions (unless otherwise specified): VS = 3 V, Tamb = 25°C, CW mode Parameters Power Amplifier Supply voltage Supply current Supply current Standby current Frequency range Power gain Gain-control range Ramping voltage Ramping current Power-added efficiency Notes: (1) Test Conditions Pins 5, 6, 7, 8 and 9 TX RX (PA off) Standby TX TX, pin 11 to pins 6, 7, 8 TX TX, power gain (max), pin 10 TX, power gain (max), pin 10 TX Symbol VS IS_TX IS_RX IS_standby f Gp DGp VRAMP max IRAMP PAE Min. 2.7 Typ. 3 350 Max. 4.6 10 10 Unit V mA µA µA GHz dB dB V 1.88 28 48 2.1 0.5 40 1.94 2.0 mA % 1. Power amplifier shall be unconditionally stable, maximum duty cycle 50%, maximum load mismatch and duration: TBD 2. With external matching network (see Figure 13 ) 3. Low-noise amplifier shall be unconditionally stable 3 4714A–DECT–07/03 Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS = 3 V, Tamb = 25°C, CW mode Parameters Saturated output power Input matching (2) Output matching (2) Test Conditions TX, referred to pins 6, 7, 8 VS = 3.6 V TX, pin 11 TX, pins 6, 7, 8 TX, pins 6, 7, 8 Pin 11 TX, pin 10 Pin = 2 dBm, VRAMP = 2 V VSWRout < 10:1 (all phases) Standby, pin 2 RX Symbol Psat VSWRin VSWRout 2 fo 3 fo PinPA Min. Typ. 26.5 < 2:1 < 2:1 -30 10 -60 Max. Unit dBm Harmonics at P 1dB Maximum input power Stability (non harmonic emission) dBc dBm dBc T/R Switch Driver (Currently Programmed by External Resistor from R_SWITCH to GND) IS_O_standby IS_O_RX IS_O_100 IS_O_1k2 IS_O_33k VS IS IS IS f Gp NF P1dB IIP3 VSWRin VSWRin ViH ViL IiH IiL 2.4 0 40 0 1.88 17 19 1.8 -7 -15 < 2:1 < 2:1 VS 0.5 V V µA µA 2.0 2.7 1 3 10 3.6 8 300 1 10 1.94 4.6 2 2 µA µA mA mA mA V mA µA µA GHz dB dB dBm dBm Switch-out current output TX at 100 W TX at 1.2 kW TX at 33 kW Low-noise Amplifier Supply voltage Supply current (3) All, pin 12 RX TX (control logic active), pin 12 Standby, pin 12 RX RX, pin 4 to pin 14 RX RX, refer to pin 14 RX RX RX = 1, pins 5 and 16 =0 =1 =0 Supply current (LNA and control logic) Standby current Frequency range Power gain Noise figure Gain compression 3rd-order input interception point Input matching Output matching Logic Input Levels (RX_ON, PU) High input level Low input level High input current Low input current Notes: 1. Power amplifier shall be unconditionally stable, maximum duty cycle 50%, maximum load mismatch and duration: TBD 2. With external matching network (see Figure 13 ) 3. Low-noise amplifier shall be unconditionally stable 4 U7006B 4714A–DECT–07/03 U7006B Control Logic Table 1. Control Logic for LNA and T/R Switch Driver Operation Mode Standby TX RX PU 0 1 1 RX_ON 0 0 1 Figure 3. Output Power versus Ramp Voltage 30 20 Pout (dBM) 10 0 -10 -20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VRAMP (V) Input/Output Circuits Figure 4. Input Circuit PA_IN/VS_PA 9 VS_PA 11 PA_IN 13 GND 5 4714A–DECT–07/03 Figure 5. Input Circuit RAMP/VS_PA 9 VS_PA 10 RAMP Slug GND Figure 6. Input Circuit V1_PA 5 V1_PA Slug GND Figure 7. Input/Output Circuit V2_PA 6, 7, 8 V2_PA_OUT Slug GND 6 U7006B 4714A–DECT–07/03 U7006B Figure 8. Input Circuit LNA_IN/VS_LNA 12 VS_LNA 4 LNA_IN 3 GND Figure 9. Output Circuit LNA_OUT 12 VS_LNA 14 LNA_OUT Slug GND 7 4714A–DECT–07/03 Figure 10. Input Circuit SWITCH_OUT/R_SWITCH 9 VS_PA 2 SWITCH_OUT 1 R_SWITCH Slug GND Figure 11. Input Circuit RX_ON 12 VS_LNA 15 RX_ON Figure 12. Input Circuit PU 12 VS_LNA 16 PU 8 U7006B 4714A–DECT–07/03 U7006B Typical Application Circuit Figure 13. Typical Schematic LNA_OUT PU RX_ON PCB PA_IN RAMP 16 15 14 13 12 11 10 9 U7006B TX/RX standby control TX LNA PA 1 2 3 4 5 6 Harmonic termination PCB 7 8 PCB diel. BPF VS PCB Microstripline l/4 Antenna 9 4714A–DECT–07/03 Figure 14. U7006B Application Board Schematic Figure 15. U7006B Application Board Layout LNA_OUT PA_IN RAMP 0R 0R 56 pF 22 nH 56 pF PU GND 56pF RX_ON DECT Frontend 100 pF 100pF 0R 2.7 pF 4.7 mF 0R 2.2 nH 1.1 pF 0.9 pF 0R 0R LED 56 pF 0R V1PA 18 nH 56 pF 1nF 1nF 1mF 56pF 0R 1 mF V2PA 0R PA VccPA 2k7 0R 390R 0R LNA_IN PA_OUT TMK9821 10 U7006B 4714A–DECT–07/03 SWITCH_OUT 4.7 mF LNA 1 nF VS_LNA U7006B Ordering Information Extended Type Number Package Remarks U7006B-MLB U7006B-MLBG3 PSSO16 PSSO16 Tube Taped and reeled Package Information 11 4714A–DECT–07/03 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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