AS10515F16MIL

Recei eceiv Quad Line Receiver Quad Austin Semiconductor, Inc. AS10515F16MIL Quad Line Receiver AVAILABLE AS MILITARY SPECIFICATIONS • Military Equivalent Screening - 883 1.2.2 PIN ASSIGNMENT (Top View) 16-Pin FlatPack (F) GENERAL DESCRIPTION The AS10515F16MIL is a quad differential amplifier designed for use in sensing differential signals over long lines. The base bias supply (VBB) is made available at pin 9 to make the device useful as a Schmitt trigger, or in other applications where a stable reference voltage is necessary. Active current sources provide the AS10515F16MIL with excellent common mode noise rejection. If any amplifier in a package is not used, one input of that amplifier must be connected to VBB (pin 9) to prevent upsetting the current source bias network. • PD = 150mW Max/Pkg (No Load) • tpd = 2.0ns typ • tr, tf = 2.0ns type (20% - 80%) DIN\ C OUT D OUT VCC2 VCC1 A OUT B OUT AIN\ 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 D IN CIN CIN\ VBB V EE BIN\ BIN A IN BURN-IN CONDITIONS: VTT = -2.0V MAX/ -2.2V MIN VEE = -5.7V MAX/ -5.2V MIN VBB = All pins designated for VBB must be tied together, no external voltage applied. NOTES 1. VBB to be used to supply bias to the AS10515F16MIL only and bypassed (when used) with 0.01 µF to 0.1 µF capacitor. 2. When the input pin with the bubble goes positive, the output goes negative. PIN ASSIGNMENTS FUNCTION VCC1 AOUT BOUT AIN\ AIN BIN BIN\ VEE VBB CIN\ CIN DIN DIN\ COUT DOUT VCC2 FLATS 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 BURN-IN (CONDITION C) GND 51 Ω to VTT 51 Ω to VTT VBB GND GND VBB VEE VBB VBB GND GND VBB 51 Ω to VTT 51 Ω to VTT GND LOGIC DIAGRAM 4 5 6 7 10 11 12 13 VBB 2 3 14 15 9 For more products and information please visit our web site at www.austinsemiconductor.com Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS10515F16MIL Rev. 2.1 07/06 1 Recei eceiv Quad Line Receiver Quad Austin Semiconductor, Inc. Channel A VCC = 2.0V ± 0.005V AS10515F16MIL Channel B Coax B Coax A 25 µF ± 20% 0.1 µF ± 20% R1 *Pulse Generator Input Coax D.U.T. CL *Pulse Generator must be capable of rise and fall times of 2.0ns ± 0.2ns. 0.1 µF ±20% NOTES: 1. tr = tf = 2.0ns ±0.2ns measured at (20% - 80%) VEE = -3.2V ±0.005V 2. PW > 20ns 3. PRF = 1.0 MHz 4. R1 = 50 Ω resistor in series with 50 Ω coax constituting the 100 Ω load. 5. Unused outputs should be loaded 100 Ω to ground. 6. 2:1 divider may be used. R1 = 50 Ω resistor in series with a 50 Ω coax cable constituting the 100 Ω load. tr tf PS1 VIN 80% 50% 20% > 20ns 80% 50% 20% PS2 tTLH 80% 50% 20% 80% 50% 20% tTHL VOUT VOUT\ tPLH tPHL 80% 50% 20% tPHL tPLH 80% 50% 20% tTHL AS10515F16MIL Rev. 2.1 07/06 tTLH Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. Figure 1. Switching Test Circuit and Waveforms 2 AS10515F16MIL Rev. 2.1 07/06 QUIESCENT LIMIT TABLE* Test Temperature VIH1 -0.78 -0.63 -0.88 -1.92 -1.255 -1.510 +1.01 +0.28 -3.2 -5.2 -1.82 -1.000 -1.400 +1.24 +0.36 -3.2 -5.2 -5.2 -5.2 -1.85 -1.105 -1.475 +1.11 +0.31 -3.2 -5.2 -5.2 VIL1 VIH2 VIL2 PS1 PS2 VEEL VEE VCB TA = 25°C TA = 125°C TA = -55°C Test Voltage Values (Volts) * ELECTRICAL CHARACTERISTICS Each MECL 10K series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 100 Ω resistor to -2.0 volts. SYMBOL PARAMETER TEST VOLTAGE APPLIED TO PINS BELOW: Pinouts referenced are for F package, check Pin Assignments VCC = 0V, Output Load = 100 Ω to -2.0V Functional Parameters: VIH1 VIL1 8 8 5, 6, 11, 12 4, 7, 10, 13 4, 7, 10, 13 5, 6, 11, 12 8 8 8 8 4-7 10 - 13 8 8 VIH2 VIL2 VEE 5, 6, 11, 12 4, 7, 10, 13 4, 7, 10, 13 5, 6, 11, 12 -0.78 -0.825 -0.63 -1.62 -0.78 -0.845 -0.63 -1.60 -1.23 -29 95 -1.0 -1.5 µA 165 165 µA -29 mA -1.24 -1.12 -1.44 -1.32 V -1.82 -1.525 -1.92 -1.635 V -1.10 -0.88 V -1.82 -1.545 -1.92 -1.655 V -1.08 -0.88 V UNITS LIMITS +25°C +125°C -55°C Subgroup 1 Subgroup 2 Subgroup 3 MIN MAX MIN MAX MIN MAX VCC 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 P.U.T. 2, 3 ,14, 15 2, 3 ,14, 15 2, 3 ,14, 15 2, 3 ,14, 15 9 8 4-7 10 - 13 4-7 10 - 13 4-7 10 - 13 VOH -0.93 VOL -1.85 VOH1 -0.95 Austin Semiconductor, Inc. 3 VOL1 -1.85 **VBB -1.35 IEE -26 *** 4-7 11 - 13 4-7 11 - 13 4-7 11 - 13 4-7 11 - 13 5, 6 11, 12 5, 6 11, 12 IIH High Output Voltage Low Output Voltage High Output Voltage Low Output Voltage Reference Voltage Power Supply Current Input Current High ICBO Input Leakage Current -1.0 Recei eceiv Quad Line Receiver Quad Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS10515F16MIL ** Connected to pin 9. *** Measure voltage on pin 9 while it is connected to other pins. AS10515F16MIL Rev. 2.1 07/06 QUIESCENT LIMIT TABLE* Test Temperature VIH1 -0.78 -0.63 -0.88 -1.92 -1.255 -1.510 +1.01 +0.28 -3.2 -5.2 -5.2 -1.82 -1.000 -1.400 +1.24 +0.36 -3.2 -5.2 -5.2 -1.85 -1.105 -1.475 +1.11 +0.31 -3.2 -5.2 -5.2 VIL1 VIH2 VIL2 PS1 PS2 VEEL VEE VCB TA = 25°C TA = 125°C TA = -55°C Test Voltage Values (Volts) * ELECTRICAL CHARACTERISTICS Each MECL 10K series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 100 Ω resistor to -2.0 volts. SYMBOL PARAMETER TEST VOLTAGE APPLIED TO PINS BELOW: Pinouts referenced are for F package, check Pin Assignments VCC = 2.0V, Output Load = 100 Ω to GND Functional Parameters: VIN 4, 7, 11, 13 2, 3, 14, 15 4, 7, 11, 13 2, 3, 14, 15 4, 7, 11, 13 2, 3, 14, 15 4, 7, 11, 13 2, 3, 14, 15 VOUT 1.1 1.1 1.0 1.0 2.90 1.0 4.0 1.0 3.5 ns 2.9 1.0 4.0 1.0 3.5 ns 3.3 1.0 4.4 1.0 3.9 ns 3.3 1.0 4.4 1.0 3.9 ns UNITS LIMITS +125°C -55°C +25°C Subgroup 9 Subgroup 10 Subgroup 11 MIN MAX MIN MAX MIN MAX VCC 1, 16 1, 16 1, 16 1, 16 VEEL 8 8 8 8 P.U.T. 2, 3 ,14, 15 2, 3 ,14, 15 2, 3 ,14, 15 2, 3 ,14, 15 tTLH Rise Time Austin Semiconductor, Inc. 4 tTHL tPHL Recei eceiv Quad Line Receiver Quad Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. tPLH Fall Time Propagation Delay High to Low Propagation Delay Low to High AS10515F16MIL