AS4DDR32M16

Austin Semiconductor, Inc. 8 Meg x 16 x 4 Banks Double Data Rate SDRAM COTS, Plastic Encapsulated Microcircuit FEATURES • VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V • Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture (has two – one per byte) • Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle • Differential clock inputs (CK and CK#) • Commands entered on each positive CK edge • DQS edge-aligned with data for READs; center-aligned with data for WRITEs • DLL to align DQ and DQS transitions with CK • Four internal banks for concurrent operation • Data mask (DM) for masking write data (has two–one per byte) • Programmable burst lengths: 2, 4, or 8 • Auto Refresh and Self Refresh Modes • Longer lead TSOP for improved reliability (OCPL) • 2.5V I/O (SSTL_2 compatible) • Concurrent auto precharge option is supported • tRAS lockout supported (tRAP = tRCD) COTS COTS PEM CO SDRAM AS4DDR32M16 (Top View) PIN ASSIGNMENT FIGURE 1: 66-Pin TSOP OPTIONS • Configuration 32 Meg x 16 (8 Meg x 16 x 4 banks) • Packaging Plastic 66-pin TSOPII (400 mil width, 0.65mm pin pitch) • Timing – Cycle Time 6ns @ CL = 2.5 (DDR333) (FBGA only) (Future offering) 7.5ns @ CL = 2.5 (DDR266B) 8ns @ CL = 2.5 (DDR250) • Temperature Rating Industrial Temperature (-40°C to +85°C) Enhanced Temperature (-40°C to +105°C) Military Temperature (-55°C to +125°C) MARKING 32M16 Configuation Refresh Count Row Addressing Bank Addressing Column Addressing 8 Meg x 16 x 4 banks 8K 8K (A0 - A12) 4 (BA0, BA1) 1K (A0 - A9) DG TABLE 1: Key Timing Parameters -6 -75 -8 SPEED GRADE -6 -75 -8 CLOCKRATE CL = 2 133 MHz 100 MHz 100 MHz CL=2.5 167 MHz 133 MHz 125 MHz DATA-OUT WINDOW 2.1 ns 2.5 ns 2.7 ns ACCESS WINDOW ±0.7 ns ±0.75 ns ±0.8 ns DQS-DQ SKEW +0.40 ns +0.5 ns -0.6 ns NOTES: IT ET XT * CL = CAS (Read) Latency For more products and information please visit our web site at www.austinsemiconductor.com AS4DDR32M16 Rev. 1.5 06/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 Austin Semiconductor, Inc. GENERAL DESCRIPTION The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. The 512Mb DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 512Mb DDR SDRAM effectively consists of a single 2n-bit wide, oneclock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-halfclock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. This offering has two data strobes, one for the lower byte and one for the upper byte. The 512Mb DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a powersaving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All full drive option outputs are SSTL_2, Class II compatible. COTS COTS PEM CO SDRAM AS4DDR32M16 NOTE: 1. The functionality and the timing specifications discussed in this data sheet are for the DLL-enabled mode of operation. 2. Throughout the data sheet, the various figures and text refer to DQ’s as “DQ.” The DQ term is to be interpreted as any and all DQ collectively, unless specifically stated otherwise. Additionally, the DQ’s are divided into two bytes, the lower byte and upper byte. For the lower byte (DQ0 through DQ7) DM refers to LDM and DQS refers to LDQS. For the upper byte (DQ8 through DQ15) DM refers to UDM and DQS refers to UDQS. 3. Complete functionality is described throughout the document and any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. 4. Any specific requirement takes precedence over a general statement. FIGURE 2: 512Mb DDR SRAM Part Number EXAMPLE: AS4DDR32M16DG-75/IT AS4DDR 32M16 Package Speed / Temperature TEMPERATURE Industrial Temperature Enhanced Temperature Military Temperature SPEED -6 -75 -8 tCK = 6ns, CL = 2.5 tCK = 7.5ns, CL = 2.5 tCK = 8ns, CL = 2.5 PACKAGING 400 mil TSOP DG IT ET XT AS4DDR32M16 Rev. 1.5 06/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 Austin Semiconductor, Inc. COTS COTS PEM CO SDRAM AS4DDR32M16 FIGURE 3: FUNCTIONAL BLOCK DIAGRAM 32 Meg x 16 AS4DDR32M16 Rev. 1.5 06/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 Austin Semiconductor, Inc. FUNCTIONAL DESCRIPTION The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. The 512Mb DDR SDRAM is internally configured as a quad-bank DRAM. The 512Mb DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 512Mb DDR SDRAM consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions, and device operation. COTS COTS PEM CO SDRAM AS4DDR32M16 supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200µs delay prior to applying an executable command. Once the 200µs delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a LOAD MODE REGISTER command should be issued for the extended mode register (BA1 LOW and BA0 HIGH) to enable the DLL, followed by another LOAD MODE REGISTER command to the mode register (BA0/ BA1 both LOW) to reset the DLL and to program the operating parameters. Two-hundred clock cycles are required between the DLL reset and any READ command. A PRECHARGE ALL command should then be applied, placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed (tRFC must be satisfied.) Additionally, a LOAD MODE REGISTER command for the mode register with the reset DLL bit deactivated (i.e., to program operating parameters without resetting the DLL) is required. Following these requirements, the DDR SDRAM is ready for normal operation. REGISTER DEFINITION Mode Register The mode register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency and an operating mode, as shown in Figure 4 on page 5. The mode register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Mode register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4A6 specify the CAS latency, and A7-A12 specify the operating mode. INITIALIZATION DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to VDD and VDDQ simultaneously, and then to VREF (and to the system VTT). VTT must be applied after VDDQ to avoid device latch-up, which may cause permanent damage to the device. VREF can be applied any time after VDDQ but is expected to be nominally coincident with VTT. Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied. After CKE passes through VIH, it will transition to a SSTL 2 signal and remain as such until power is cycled. Maintaining an LVCMOS LOW level on CKE during power-up is required to ensure that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read access). After all power AS4DDR32M16 Rev. 1.5 06/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 Austin Semiconductor, Inc. BURST LENGTH Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 4. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command.Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts. BURST TYPE Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 2, Burst Definition. COTS COTS PEM CO SDRAM AS4DDR32M16 FIGURE 4: Mode Register Definition TABLE 2: BURST DEFINITION STARTING BURST COLUMN LENGTH ADDRESS 2 A0 0 1 A1 A0 00 01 10 11 A2 A1 A0 000 001 010 011 100 101 110 111 ORDER OF ACCESS WITHIN A BURST TYPE = TYPE = SEQUENTIAL INTERLEAVED 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 4 NOTES: 1. Whenever a boundary of the block is reached within a given sequence in Table 2, the following access wraps within the block. 2. For a burst length of two, A1 - Ai select the two-data-element block; A0 selects the first access within the block. 3. For a burst length of four, A2 - Ai select the four-data-element block; A0-A1 select the first access within the block. 4. For a burst length of eight, A3 - Ai select the eight-data-element block; A0-A2 select the first access within the block. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 AS4DDR32M16 Rev. 1.5 06/06 5 Austin Semiconductor, Inc. READ LATENCY The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2, or 2.5 clocks, as shown in Figure 5. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 3, CAS Latency (CL), on page 6 indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. COTS COTS PEM CO SDRAM AS4DDR32M16 FIGURE 5: CAS LATENCY OPERATING MODE The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A12 each set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. Although not required by the Austin Semiconductor device, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode. All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used, as unknown operation or incompatibility with future versions may result. TABLE 3: CAS LATENCY (CL) SPEED -6 -75 -8 ALLOWABLE OPERATING CLOCK FREQUENCY CL = 2 75 < f < 133 75 < f < 100 75 < f < 100 CL = 2.5 75 < f < 167 75 < f < 133 75 < f < 125 AS4DDR32M16 Rev. 1.5 06/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 Austin Semiconductor, Inc. EXTENDED MODE REGISTER The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, and output drive strength. These functions are controlled via the bits shown in Figure 6. The extended mode register is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL. The extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. COTS COTS PEM CO SDRAM AS4DDR32M16 MODE FIGURE 6: EXTENDED REGISTER DEFINITION OUTPUT DRIVE STRENGTH The normal drive strength for all outputs are specified to be SSTL2, Class II. This device supports a programmable option for reduced drive. This option is intended for the support of the lighter load and/or point-to-point environments. The selection of the reduced drive strength will alter the DQ pins and DQS pins from SSTL2, Class II drive strength to a reduced drive strength, which is approximately 54 percent of the SSTL2, Class II drive strength. NOTES: 1. E14 and E13 (BA1 and BA0) must be “0, 1” to select the Extended Mode Register vs. the base Mode Register. 2. The reduced drive strength option is supported. 3. The QFC# option is not supported. DLL ENABLE/DISABLE When the part is running without the DLL enabled, device functionality may be altered. The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. AS4DDR32M16 Rev. 1.5 06/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 Austin Semiconductor, Inc. COMMANDS Table 4 and Table 5 provide a quick reference of available commands. This is followed by a verbal description of each command. Two additional Truth Tables, Table 7 and Table8 appear following the Operation section, provide current state/ next state information. COTS COTS PEM CO SDRAM AS4DDR32M16 TABLE 4: TRUTH TABLE - COMMANDS (Note 1 applies to all commands) FUNCTION DESELECT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER CS# H L L L L L L L L RAS# X H L H H H L L L CAS# X H H L L H H L L WE# X H H H L L L H L ADDR NOTES X 9 X 9 Bank/Row 3 Bank/Col 4 Bank/Col 4 X 8 Code 5 X 6, 7 Op-Code 2 NOTES: 1. CKE is HIGH for all commands shown except SELF REFRESH. 2. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A12 provide the opcode to be written to the selected mode register. 3. BA0-BA1 provide bank address and A0-A12 provide row address. 4. BA0-BA1 provide bank address; A0-A9 provide column address. A10 HIGH enables the auto precharge feature (non persistent), and A10 LOW disables the auto precharge feature. 5. A10 LOW: BA0-BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0-BA1 are “Don’t Care.” 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; for within the Self Refresh mode all inputs and I/Os are “Don’t Care” except for CKE. 8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for read bursts with auto precharge enabled and for write bursts. 9. DESELECT and NOP are functionally interchangeable. TABLE 5: TRUTH TABLE - DM OPERATION (Note 1 applies to all commands) FUNCTION Write Enable Write Inhibit DM L H DQ Valid X NOTE: 1. Used to mask write data; provided coincident with the corresponding data. AS4DDR32M16 Rev. 1.5 06/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 Austin Semiconductor, Inc. DESELECT The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in progress are not affected. COTS COTS PEM CO SDRAM AS4DDR32M16 NO OPERATION (NOP) The NO OPERATION (NOP) command is used to instruct the selected DDR SDRAM to perform a NOP (CS# is LOW with RAS#, CAS#, and WE# are HIGH). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. row will remain open for subsequent accesses. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the precharge command is issued. Except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging. LOAD MODE REGISTER The mode registers are loaded via inputs A0–A12. See mode register descriptions in the Register Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A12 selects the row. This row remains active (or open) for accesses until a precharge command is issued to that bank. A precharge command must be issued before opening a different row in the same bank. AUTO PRECHARGE Auto precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/ row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual Read or Write command. This device supports concurrent auto precharge if the command to the other bank does not interrupt the data transfer to the current bank. Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. This “earliest valid stage” is determined as if an explicit PRECHARGE command was issued at the earliest possible time, without violating tRAS (MIN), as described for each burst type in the Operation section of this data sheet. The user must not issue another command to the same bank until the precharge time (tRP) is completed. READ The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A9 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A9 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the AS4DDR32M16 Rev. 1.5 06/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 Austin Semiconductor, Inc. BURST TERMINATE The BURST TERMINATE command is used to truncate read bursts (with auto precharge disabled). The most recently registered READ command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of this data sheet. The open page which the READ burst was terminated from remains open. COTS COTS PEM CO SDRAM AS4DDR32M16 AUTO REFRESH AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous to CAS#-BEFORE RAS# (CBR) refresh in FPM/EDO DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. All banks must be idle before an AUTO REFRESH command is issued. The addressing is generated by the internal refresh controller. This makes the address bits a “Don’t Care” during an AUTO REFRESH command. The 512Mb DDR SDRAM requires AUTO REFRESH cycles at an average interval of 7.8125µs (maximum). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM, meaning that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 9 x 7.8125µs (70.3µs). Note the JEDEC specifications only allows 8 x 7.8125µs, thus the Austin Semiconductor specification exceeds the JEDEC requirement by one clock. This maximum absolute interval is to allow future support for DLL updates internal to the DDR SDRAM to be restricted to AUTO REFRESH cycles, without allowing excessive drift in tAC between updates. Although not a JEDEC requirement, to provide for future functionality features, CKE must be active (High) during the AUTO REFRESH period. The AUTO REFRESH period begins when the AUTO REFRESH command is registered and ends tRFC later. REFRESH. The procedure for exiting self refresh requires a sequence of commands. First, CK and CK# must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP commands issued for tXSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for tXSNR time, then a DLL Reset and NOPs for 200 additional clock cycles before applying any other command. BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the DDR SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated, as shown in Figure 7. After a row is opened with an ACTIVE command, a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 20ns with a 133 MHz clock (7.5ns period) results in 2.7 clocks rounded to 3. This is reflected in Figure 8, which covers any case where 2 1V/ns (> 2V/ns if measured differentially). 31. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mv/ns reduction in slew rate. For -6 speed grades, slew rate must be > 0.5V/ns. If slew rate exceeds 4V/ns, functionality is uncertain. 32. VDD must not vary more than 4 percent if CKE is not active while any bank is active. 33. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by the same amount. 34. tHP (MIN) is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK# inputs, collectively during bank active. (continued) Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 45 Austin Semiconductor, Inc. COTS COTS PEM CO SDRAM AS4DDR32M16 FIGURE 32: DERATING DATA VALID WINDOW (tQH - tDQSQ) NOTES (continued): 35. READs and WRITEs with auto precharge are not allowed to be issued until tRAS (MIN) can be satisfied prior to the internal precharge command being issued. 36. Any positive glitch must be less than 1/3 of the clock cycle and not more than +400mV or 2.9V, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mV or 2.2V, whichever is more positive. 37. Normal Output Drive Curves: a. The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 33 b. The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 33. c. The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 34. d. The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 34. e. The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0V, and at the same voltage and temperature. f ) The full variation in the ratio of the nominal pullup to pull-down current should be unity ±10 percent, for device drain-to-source voltages from 0.1V to 1.0V. (continued) FIGURE 33: FULL DRIVE PULLDOWN CHARACTERISTICS FIGURE 34: FULL DRIVE PULL-UP CHARACTERISTICS AS4DDR32M16 Rev. 1.5 06/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 46 Austin Semiconductor, Inc. NOTES (continued): 38. Reduced Output Drive Curves: a. The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 35. b. The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 35. c. The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 36. d. The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 36. e. The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4 for device drainto-source voltages from 0.1V to 1.0V, and at the same voltage and temperature. f. The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10 percent, for device drain-to-source voltages from 0.1V to 1.0V. 39. The voltage levels used are derived from a minimum VDD level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. 40. VIH overshoot: VIH (MAX) = VDDQ + 1.5V for a pulse width < 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a pulse width < 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 41. VDD and VDDQ must track each other. 42. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + tRPRE (MAX) condition. 43. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). 44. During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even VDD/VDDQ are 0V, providind a minimum of 42Ω o f series resistance is used between the VTT supply and the input pin. 45. The current Austin Semiconductor part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. 46. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or LOW. 47. Random addressing changing 50 percent of data changing at every transfer. 48. Random addressing changing 100 percent of data changing at every transfer. 49. CKE must be active (HIGH) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising lock edge, until rRFC has been satisfied. COTS COTS PEM CO SDRAM AS4DDR32M16 FIGURE 35: REDUCED DRIVE PULLDOWN CHARACTERISTICS FIGURE 36: REDUCED DRIVE PULLUP CHARACTERISTICS 50. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to remail stable. Although IDD2F, IDD2N and IDD2Q are similar, IDD2F is “worst case”. 51. Whenever the operating frequency is altered, not including jitter, the DLL is required to the reset followed by 200 clock cycles befoe any READ command. 52. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20MHz. Any noise above 20MHz at the DRAM grenerated from any source other than that of the DRAM itself may not exceed the DC voltage range of 2.6V ±100mV. 53. The -6/-6T speed grades will operate with tRAS (MIN) = 40ns and tRAS (MAX) = 120,000ns at any slower frequency. AS4DDR32M16 Rev. 1.5 06/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 47 Austin Semiconductor, Inc. COTS COTS PEM CO SDRAM AS4DDR32M16 TABLE 18: NORMAL OUTPUT DRIVE CHARACTERISTICS PULL-DOWN CURRENT (m A PULL-UP CURRENT (m A VOLTAGE NOMINAL NOMINAL NOMINAL NOMINAL (V) MINIMUM MAXIMUM MINIMUM MAXIMUM H IGH LO W HIG H LO W 0.1 6.0 6.8 4.6 9.6 -6.1 -7.6 -4.6 -10.0 0.2 12.2 13.5 9.2 18.2 -12.2 -14.5 -9.2 -20.0 0.3 18.1 20.1 13.8 26.0 -18.1 -21.2 -13.8 -29.8 0.4 24.1 26.6 18.4 33.9 -24.0 -27.7 -18.4 -38.8 0.5 29.8 33.0 23.0 41.8 -29.8 -34.1 -23.0 -46.8 0.6 34.6 39.1 27.7 49.4 -34.3 -40.5 -27.7 -54.4 0.7 39.4 44.2 32.2 56.8 -38.1 -46.9 -32.2 -61.8 0.8 43.7 49.8 36.8 63.2 -41.1 -53.1 -36.0 -69.5 0.9 47.5 55.2 39.6 69.9 -43.8 -59.4 -38.2 -77.3 1.0 51.3 60.3 42.6 76.3 -46.0 -65.5 -38.7 -85.2 1.1 54.1 65.2 44.8 82.5 -47.8 -71.6 -39.0 -93.0 1.2 56.2 69.9 46.2 88.3 -49.2 -77.6 -39.2 -100.6 1.3 57.9 74.2 47.1 93.8 -50.0 -83.6 -39.4 -108.1 1.4 59.3 78.4 47.4 99.1 -50.5 -89.7 -39.6 -115.5 1.5 60.1 82.3 47.7 103.8 -50.7 -95.5 -39.9 -123.0 1.6 60.5 85.9 48.0 108.4 -51.0 -101.3 -40.1 -130.4 1.7 61.0 89.1 48.4 112.1 -51.1 -107.1 -40.2 -136.7 1.8 61.5 92.2 48.9 115.9 -51.3 -112.4 -40.3 -144.2 1.9 62.0 95.3 49.1 119.6 -51.5 -118.7 -40.4 -150.5 49.4 2.0 62.5 97.2 123.3 -51.6 -124.0 -40.5 -156.9 2.1 62.8 99.1 49.6 126.5 -51.8 -129.3 -40.6 -163.2 2.2 63.3 100.9 49.8 129.5 -52.0 -134.6 -40.7 -169.6 2.3 63.8 101.9 49.9 132.4 -52.2 -139.9 -40.8 -176.0 2.4 64.1 102.8 50.0 135.0 -52.3 -145.2 -40.9 -181.3 2.5 64.6 103.8 50.2 137.3 -52.5 -150.5 -41.0 -187.6 2.6 64.8 104.6 50.4 139.2 -52.7 -155.3 -41.1 -192.9 2.7 65.0 105.4 50.5 140.8 -52.8 -160.1 -41.2 -198.2 NOTE: The above characteristics are specified under best, worse, and nominal process variation/conditions. AS4DDR32M16 Rev. 1.5 06/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 48 Austin Semiconductor, Inc. COTS COTS PEM CO SDRAM AS4DDR32M16 TABLE 19: REDUCED OUTPUT DRIVE CHARACTERISTICS PULL-DOWN CURRENT (m A PULL-UP CURRENT (m A VOLTAGE NOMINAL NOMINAL NOMINAL NOMINAL (V) MINIMUM MAXIMUM MINIMUM MAXIMUM H IGH LO W HIG H LO W 0.1 3.4 3.8 2.6 5.0 -3.5 -4.3 -2.6 -5.0 0.2 6.9 7.6 5.2 9.9 -6.9 -7.8 -5.2 -9.9 0.3 10.3 11.4 7.8 14.6 -10.3 -12.0 -7.8 -14.6 0.4 13.6 15.1 10.4 19.2 -13.6 -15.7 -10.4 -19.2 0.5 16.9 18.7 13.0 23.6 -16.9 -19.3 -13.0 -23.6 0.6 19.9 22.1 15.7 28.0 -19.4 -22.9 -15.7 -28.0 0.7 22.3 25.0 18.2 32.2 -21.5 -26.5 -18.2 -32.2 0.8 24.7 28.2 20.8 38.8 -23.3 -30.1 -20.4 -35.8 0.9 26.9 31.3 22.4 39.5 -24.8 -33.6 -21.6 -39.2 1.0 29.0 34.1 24.1 43.2 -26.0 -37.1 -21.9 -43.2 1.1 30.6 36.9 25.4 46.7 -27.1 -40.3 -22.1 -46.7 1.2 31.8 39.5 26.2 50.0 -27.8 -43.1 -22.2 -50.0 1.3 32.8 42.0 26.6 53.1 -28.3 -45.8 -22.3 -53.1 1.4 33.5 44.4 26.8 56.1 -28.6 -48.4 -22.4 -56.1 1.5 34.0 46.6 27.0 58.7 -28.7 -50.7 -22.6 -58.7 1.6 34.3 48.6 27.2 61.4 -28.9 -52.9 -22.7 -61.4 1.7 34.5 50.5 27.4 63.5 -28.9 -55.0 -22.7 -63.5 1.8 34.8 52.2 27.7 65.6 -29.0 -56.8 -22.8 -65.6 1.9 35.1 53.9 27.8 67.7 -29.2 -58.7 -22.9 -67.7 28 2.0 35.4 55.0 69.8 -29.2 -60.0 -22.9 -69.8 2.1 35.6 56.1 28.1 71.6 -29.3 -61.2 -23.0 -70.6 2.2 35.8 57.1 28.2 73.3 -29.5 -62.4 -23.0 -73.3 2.3 36.1 57.7 28.3 74.9 -29.5 -63.1 -23.1 -74.9 2.4 36.6 58.2 28.3 76.4 -29.6 .63.8 -23.2 -76.4 2.5 36.5 58.7 28.4 77.7 -29.7 -64.4 -23.2 -77.7 2.6 36.7 59.2 28.5 78.8 -29.8 -65.1 -23.3 -78.8 2.7 36.8 59.6 28.6 79.7 -29.9 -65.8 -23.3 -79.7 NOTE: The above characteristics are specified under best, worse, and nominal process variation/conditions. AS4DDR32M16 Rev. 1.5 06/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 49 Austin Semiconductor, Inc. COTS COTS PEM CO SDRAM AS4DDR32M16 FIGURE 37: DATA OUTPUT TIMING - tDQSQ, tQH, and DATA VALID WINDOW NOTES: 1. 2. 3. 4. 5. 6. 7. DQ transitioning after DQS transition define tDQSQ window. LDQS defines the lower byte and UDQS defines the upper byte. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and ends with the last valid DQ transition. tQH is derived from tHP: tQH = tHP - tQHS. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active. The data valid window is derived for each DQS transition and is tQH minus tDQSQ. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS4DDR32M16 Rev. 1.5 06/06 50 Austin Semiconductor, Inc. COTS COTS PEM CO SDRAM AS4DDR32M16 FIGURE 38: DATA OUTPUT TIMING - tAC AND tDQSCK NOTES: 1. 2. 3. 4. 5. 6. 7. tDQSCK is the DQS output window relative to CK and is the “long term” component of DQS skew. DQ transitioning after DQS transition define tDQSQ window. All DQ must transition by tDQSQ after DQS transitions, regardless of tAC. tAC is the DQ output window relative to CK, and is the “long term” component of DQ skew. tLZ (MIN) and tAC (MIN) are the first valid signal transition. tHZ (MAX),and tAC (MAX) are the latest valid signal transition. READ command with CL = 2 issued at T0. FIGURE 39: DATA INPUT TIMING NOTES: 1. 2. 3. 4. tDSH (MIN) generally occurs during tDQSS (MIN). tDSS (MIN) generally occurs during tDQSS (MAX). WRITE command issued at T0. LDQS controls the lower byte and UDQS controls the upper byte. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS4DDR32M16 Rev. 1.5 06/06 51 Austin Semiconductor, Inc. INITIALIZATION COTS COTS PEM CO SDRAM AS4DDR32M16 To ensure device operation the DRAM must be initialized as described below: 1. Simultaneously apply power to VDD and VDDQ. 2. Apply VREF and then VTT power. 3. Assert and hold CKE at a LVCMOS logic low. 4. Provide stable CLOCK signals. 5. Wait at least 200µs. 6. Bring CKE high and provide at least one NOP or DESELECT command. At this point the CKE input changes from a LVCMOS input to a SSTL2 input only and will remain a SSTL_2 input unless a power cycle occurs. 7. Perform a PRECHARGE ALL command. 8. Wait at least tRP time, during this time NOPs or DESELECT commands must be given. 9. Using the LMR command program the Extended Mode Register (E0 = 0 to enable the DLL and E1 = 0 for normal drive or E1 = 1 for reduced drive, E2 through En must be set to 0; where n = most significant bit). 10. Wait at least tMRD time, only NOPs or DESELECT commands are allowed. 11. Using the LMR command program the Mode Register to set operating parameters and to reset the DLL. Note at least 200 clock cycles are required between a DLL reset and any READ command. 12. Wait at least tMRD time, only NOPs or DESELECT commands are allowed. 13. Issue a PRECHARGE ALL command. 14. Wait at least tRP time, only NOPs or DESELECT commands are allowed. 15. Issue an AUTO REFRESH command (Note this may be moved prior to step 13). 16. Wait at least tRFC time, only NOPs or DESELECT commands are allowed. 17. Issue an AUTO REFRESH command (Note this may be moved prior to step 13). 18. Wait at least tRFC time, only NOPs or DESELECT commands are allowed. 19. Although not required by the Micron device, JEDEC requires a LMR command to clear the DLL bit (set M8 = 0). If a LMR command is issued the same operating parameters should be utilized as in step 11. 20. Wait at least tMRD time, only NOPs or DESELECT commands are allowed. 21. At this point the DRAM is ready for any valid command. Note 200 clock cycles with CKE high are required between step 11 (DLL RESET) and any READ command. AS4DDR32M16 Rev. 1.5 06/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 52 Austin Semiconductor, Inc. COTS COTS PEM CO SDRAM AS4DDR32M16 FIGURE 40: Initialization Flow Diagram AS4DDR32M16 Rev. 1.5 06/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 53 Austin Semiconductor, Inc. COTS COTS PEM CO SDRAM AS4DDR32M16 FIGURE 41: INITIALIZE AND LOAD MODE REGISTERS NOTES: 1. VTT is not applied directly to the device; however, tVTD should be greater than or equal to zero to avoid device latch-up. VDDQ, VTT, and VREF, must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VDD/VDDQ are 0V, provided a minimum of 42 ohms of series resistance is used between the VTT supply and the input pin. Once initialized, VREF must always be powered with in specified range. 2. Reset the DLL with A8 = H while programming the operating parameters. 3. tMRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can be issued. 4. The two AUTO REFRESH commands at Td0 and Te0 may be applied prior to the LOAD MODE REGISTER (LMR) command at Ta0. 5. Although not required by the Micron device, JEDEC specifies issuing another LMR command (A8 = L) prior to activating any bank. If another LMR command is issued, the same operating parameters, previously issued, must be used. 6. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command, RA = Row Address, BA = Bank Address. AS4DDR32M16 Rev. 1.5 06/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 54 Austin Semiconductor, Inc. FIGURE 42: POWER-DOWN MODE COTS COTS PEM CO SDRAM AS4DDR32M16 NOTES: 1. Once initialized, VREF must always be powered with in specified range. 2. If this command is a PRECHARGE (or if the device is already in the idle state), then the power-down mode shown is precharge power-down. If this command is an ACTIVE (or if at least one row is already active), then the power-down mode shown is active power-down. 3. No column accesses are allowed to be in progress at the time power-down is entered. AS4DDR32M16 Rev. 1.5 06/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 55 Austin Semiconductor, Inc. FIGURE 43: AUTO REFRESH MODE COTS COTS PEM CO SDRAM AS4DDR32M16 NOTES: 1. PRE = PRECHARGE, ACT = ACTIVE, AR = AUTO REFRESH, RA = Row Address, BA = Bank Address. 2. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. CKE must be active during clock positive transitions. 3. NOP or COMMAND INHIBIT are the only commands allowed until after tRFC time, CKE must be active during clock positive transitions. 4. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e., must precharge all active banks). 5. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown. 6. The second AUTO REFRESH is not required and is only shown as an example of two back-to-back AUTO REFRESH commands. AS4DDR32M16 Rev. 1.5 06/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 56 Austin Semiconductor, Inc. FIGURE 44: SELF REFRESH MODE COTS COTS PEM CO SDRAM AS4DDR32M16 NOTES: 1. Clock must be stable until after the self refresh command has been registered. A change in clock frequency is allowed before Ta0, provided it is within the specified tCK limits. Regardless, the clock must be stable before exiting self refresh mode. That is, the clock must be cycling within specifications by Ta0. 2. NOPs are interchangeable with DESELECT commands, AR = AUTO REFRESH command. 3. Auto Refresh is not required at this point, but is highly recommended. 4. Device must be in the all banks idle state prior to entering self refresh mode. 5. tXSNR is required before any non-READ command can be applied. That is only NOP or DESELECT commands are allowed until Tb1. 6. tXSRD (200 cycles of a valid CK and CKE = high) is required before any READ command can be applied. 7. As a general rule, any time Self Refresh Mode is exited, the DRAM may not re-enter the Self Refresh Mode until all rows have been refreshed via the Auto Refresh command at the distributed refresh rate, tREFI, or faster. However, the following exception is allowed. Self Refresh Mode may be re-entered anytime after exiting, if the following conditions are all met: a. The DRAM had been in the Self Refresh Mode for a minimum of 200ms prior to exiting. b. tXSNR and tXSRD are not violated. c. At least two Auto Refresh commands are performed during each tREFI interval while the DRAM remains out of Self Refresh mode. 8. If the clock frequency is changed during self refresh mode, a DLL reset is required upon exit. 9. Once initialized, Vref must always be powered with in specified range. AS4DDR32M16 Rev. 1.5 06/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 57 Austin Semiconductor, Inc. COTS COTS PEM CO SDRAM AS4DDR32M16 FIGURE 45: BANK READ - WITHOUT AUTO PRECHARGE NOTES: 1. 2. 3. 4. 5. 6. 7. 8. DOn = data-out from column n; subsequent elements are provided in the programmed order. Burst length = 4 in the case shown. Disable auto precharge. “Don’t Care” if A10 is HIGH at T5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address. NOP commands are shown for ease of illustration; other commands may be valid at these times. The PRECHARGE command can only be applied at T5 if tRAS minimum is met. Refer to Figure 37 and Figure 38 for detailed DQS and DQ timing. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS4DDR32M16 Rev. 1.5 06/06 58 Austin Semiconductor, Inc. COTS COTS PEM CO SDRAM AS4DDR32M16 FIGURE 46: BANK READ - WITH AUTO PRECHARGE NOTES: 1. DOn = data-out from column n; subsequent elements are provided in the programmed order. 2. Burst length = 4 in the case shown. 3. Enable auto precharge. 4. ACT = ACTIVE, RA = Row Address, BA = Bank Address. 5. NOP commands are shown for ease of illustration; other commands may be valid at these times. 6. The READ command can only be applied at T3 if tRAP is satisfied at T3. 7. tRP starts only after tRAS has been satisfied. 8. Refer to Figure 37 and Figure 38 for detailed DQS and DQ timing. AS4DDR32M16 Rev. 1.5 06/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 59 Austin Semiconductor, Inc. COTS COTS PEM CO SDRAM AS4DDR32M16 FIGURE 47: BANK WRITE - WITHOUT AUTO PRECHARGE NOTES: 1. 2. 3. 4. 5. 6. 7. DIn = data-in. from column n; subsequent elements are provided in the programmed order. Burst length = 4 in the case shown. Disable auto precharge. “Don’t Care” if A10 is HIGH at T8. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address. NOP commands are shown for ease of illustration; other commands may be valid at these times. See Figure 39, ”Data Input Timing” for detailed DQ timing. AS4DDR32M16 Rev. 1.5 06/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 60 Austin Semiconductor, Inc. COTS COTS PEM CO SDRAM AS4DDR32M16 FIGURE 48: BANK WRITE - WITH AUTO PRECHARGE NOTES: 1. DIn = data-out from column n; subsequent elements are provided in the programmed order. 2. Burst length = 4 in the case shown. 3. Enable auto precharge. 4. ACT = ACTIVE, RA = Row Address, BA = Bank Address. 5. NOP commands are shown for ease of illustration; other commands may be valid at these times. 6. See Figure 39, ”Data Input Timing” for detailed DQ timing. AS4DDR32M16 Rev. 1.5 06/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 61 Austin Semiconductor, Inc. COTS COTS PEM CO SDRAM AS4DDR32M16 FIGURE 49: WRITE - DM OPERATION NOTES: 1. 2. 3. 4. 5. 6. 7. DIn = data-in from column n; subsequent elements are provided in the programmed order. Burst length = 4 in the case shown. Disable auto precharge. “Don’t Care” if A10 is HIGH at T8. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address. NOP commands are shown for ease of illustration; other commands may be valid at these times. See Figure 39, ”Data Input Timing” for detailed DQ timing. AS4DDR32M16 Rev. 1.5 06/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 62 Austin Semiconductor, Inc. COTS COTS PEM CO SDRAM AS4DDR32M16 FIGURE 50: 66-PIN PLASTIC TSOP (400 MIL) ASI DESIGNATOR DG NOTES: 1. All dimensions in millimeters 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. AS4DDR32M16 Rev. 1.5 06/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 63 Austin Semiconductor, Inc. ORDER CHART COTS COTS PEM CO SDRAM AS4DDR32M16 EXAMPLE: AS4DDR32M16DG-75/IT Device Number AS4DDR32M16 AS4DDR32M16 AS4DDR32M16 Package Type DG DG DG Speed ns -61 -75 -8 Process /IT /* /* 2 *AVAILABLE PROCESSES IT = Industrial Temperature Range ET = Enhanced Temperature Range XT = Extended Temperature Range -40oC to +85oC -40oC to +105oC -55oC to +125oC NOTE: 1. This is a future offering. Contact your local sales representative for more information. 2. The -6 option is available at XT only. AS4DDR32M16 Rev. 1.5 06/06 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 64