AS4DDR32M72PBG

i PEM 2.4Gb 2.4Gb SDRAM-DDR Austin Semiconductor, Inc. AS4DDR32M72PBG 32Mx72 DDR SDRAM iNTEGRATED Plastic Encapsulated Microcircuit FEATURES DDR SDRAM Data Rate = 200, 250, 266, 333Mbps Package: • 219 Plastic Ball Grid Array (PBGA), 32 x 25mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CLK and CLK#) Commands entered on each positive CLK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture (one per byte) DQS edge-aligned with data for READs; center-aligned with data for WRITEs DLL to align DQ and DQS transitions with CLK Four internal banks for concurrent operation Two data mask (DM) pins for masking write data Programmable IOL/IOH option Auto precharge option Auto Refresh and Self Refresh Modes Industrial, Enhanced and Military Temperature Ranges Organized as 32M x 72/80 Weight: AS4DDR32M72PBG 1V/ns (>2V/ns differentially). 31. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mV/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain. 32. VCC must not vary more than 4% if CKE is not active while any bank is active. 33. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by the same amount. 34. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device CLK and CLK# inputs, collectively during bank active. 35. READs and WRITEs with auto precharge are not allowed to be issued until tRAS(MIN) can be satisfied prior to the internal precharge command being issued. 36. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or 2.9 volts, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mV or 2.2 volts, whichever is more positive. 37. Normal Output Drive Curves: a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure A. b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure A. c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure B. d) The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure B. e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between .71 and 1.4, for device drainto-source voltages from 0.1V to 1.0 Volt, and at the same voltage and temperature. f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity ¡À10%, for device drain-to-source voltages from 0.1V to 1.0 Volt. 38. Reduced Output Drive Curves: a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure C. b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure C. c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure D. d) The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure B. e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between .71 and 1.4, for device drainto-source voltages from 0.1V to 1.0 Volt, and at the same voltage and temperature. f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 Volt. The voltage levels used are derived from a minimum V CC l evel and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. V IH o vershoot: V IH (MAX) = V CCQ +1.5V for a pulse width < 3ns and the pulse width can not be greater than 1/3 of the cycle rate. V CC a nd V CCQ m ust track each other. This maximum value is derived from the referenced test load. In practice, the values obtained in a typical terminated design may reflect up to 310ps less for t HZ (MAX) and the last DVW. t HZ (MAX) will prevail over t DQSCK (MAX) + t RPST (MAX) condition. t LZ (MIN) will prevail over t DQSCK (MIN) + t RPRE (MAX) condition. For slew rates greater than 1V/ns the (LZ) transition will start about 310ps earlier. During initialization, V CCQ , V TT , and V REF m ust be equal to or less than V CC + 0.3V. Alternatively, V TT m ay be 1.35V maximum during power up, even if V CC /V CCQ a re 0 volts, provided a minimum of 42 ohms of series resistance is used between the V TT s upply and the input pin. The current part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. Reserved for future use. Reserved for future use. Random addressing changing 50% of data changing at every transfer. Random addressing changing 100% of data changing at every transfer. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until t RFC h as been satisfied. I CC2N s pecifies the DQ, DQS, and DM to be driven to a valid high or low logic level. I CC2Q i s similar to I CC2F e xcept I CC2Q s pecifies the address and control inputs to remain stable. Although I CC2F , I CC2N , and I CC2Q a re similar, I CC2F i s “worst case.” Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles before any READ command. V TT i s not applied directly to the device; however, t VTD s hould be greater than or equal to zero to avoid device latch-up. V CCQ , V TT a nd V REF m ust be equal to or less than V CC + 0 .3V. Alternatively V TT m ay be 1.35V max during power-up even if V CC /V CCQ a re 0V, provided a minimum of 42 &! of series resistance is used between the V TT s upply and the input pin. Once initialized, V REF m ust always be powered within the specified range. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. FIGURE C - PULL-DOWN CHARACTERISTICS 80 FIGURE D - PULL-UP CHARACTERISTICS 0 -10 Maximum 70 60 Nominal high -20 Minimum 50 -30 Nominal low IOUT (mA) IOUT (mA) 40 Nominal low -40 30 -50 Minimum 20 -60 Nominal high 10 -70 Maximum 0 0.0 0.5 1.0 1.5 2.0 2.5 -80 0.0 0.5 1.0 1.5 2.0 2.5 VOUT (V) VCCQ - VOUT (V) AS4DDR32M72PBG Rev. 1.2 06/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 16 i PEM 2.4Gb 2.4Gb SDRAM-DDR Austin Semiconductor, Inc. AS4DDR32M72PBG PACKAGE DIMENSION: 219 PLASTIC BALL GRID ARRAY (PBGA) Bottom View 32.1 (1.264) MAX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 T R P N M L K J H G F E D C B A 19.05 (0.750) NOM 25.1 (0.988) MAX 1.27 (0.050) NOM 0.61 (0.024) NOM 219 X Ø 0.762 (0.030) NOM 19.05 (0.750) NOM 2.03 (0.080) MAX ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES AS4DDR32M72PBG Rev. 1.2 06/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 17 i PEM 2.4Gb 2.4Gb SDRAM-DDR Austin Semiconductor, Inc. AS4DDR32M72PBG ORDERING INFORMATION Part Number AS4DDR32M72-6/IT AS4DDR32M72-75/IT AS4DDR32M72-8/IT AS4DDR32M72-10/IT AS4DDR32M72-75/ET AS4DDR32M72-8/ET AS4DDR32M72-10/ET AS4DDR32M72-75/XT AS4DDR32M72-8/XT AS4DDR32M72-10/XT Core Freq. Data Transfer Rate 166 MHz 333 Mbps 133 MHz 266 Mbps 125 MHz 250 Mbps 100 MHz 200 Mbps 133 MHz 125 MHz 100 MHz 133 MHz 125 MHz 100 MHz 266 Mbps 250 Mbps 200 Mbps 266 Mbps 250 Mbps 200 Mbps Package Process 219-PBGA Industrial 219-PBGA Industrial 219-PBGA Industrial 219-PBGA Industrial 219-PBGA 219-PBGA 219-PBGA 219-PBGA 219-PBGA 219-PBGA Enhanced Enhanced Enhanced Military Military Military AS4DDR32M72PBG Rev. 1.2 06/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 18 i PEM 2.4Gb 2.4Gb SDRAM-DDR Austin Semiconductor, Inc. AS4DDR32M72PBG DOCUMENT TITLE 32M x 72 DDR SDRAM Multi-Chip Packaged in a 32mm x 25mm - 219 PBGA REVISION HISTORY Rev # 1.0 1.1 1.2 History Release Date RELEASE March 2005 added configuration addressing table September 2008 to page 1 Updated Order Chart June 2009 Changed from “Extended” to “Military” Temp Status Preliminary Preliminary Release AS4DDR32M72PBG Rev. 1.2 06/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 19