AS5C2568

SRAM S RAM Austin Semiconductor, Inc. 32K x 8 SRAM SRAM MEMORY ARRAY FEATURES • • • • • • • • • Access Times: 12, 15, & 20ns Fast output enable (tDOE) for cache applications Low active power: 400 mW (TYP) Low power standby Fully static operation, no clock or refresh required High-performance, low-power CMOS double-metal process Single +5V (+10%) Power Supply Easy memory expansion with CE\ All inputs and outputs are TTL compatible AS5C2568 PIN ASSIGNMENT (Top View) 28-PIN PSOJ (DJ) OPTIONS • Timing 12ns access* 15ns access 20ns access • Package(s)** Plastic SOJ MARKING -12 -15 -20 DJ XT IT No. 906 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 VCC 27 WE\ 26 A13 25 A8 24 A9 23 A11 22 OE\ 21 A10 20 CE\ 19 I/O7 18 I/O6 17 I/O5 16 I/O4 15 I/O3 • Operating Temperature Ranges Military -55oC to +125oC Industrial -40oC to +85oC * -12 available in IT only. ** For ceramic version of this product, see the MT5C2568 data sheet. GENERAL DESCRIPTION The Austin Semiconductor SRAM family employs high-speed, low power CMOS designs using a four-transistor memory cell. These SRAMs are fabricated using double-layer metal, double-layer polysilicon technology. For flexibility in high-speed memory applications, Austin Semiconductor offers chip enable (CE\) and output enable (OE\) capability. These enhancements can place the outputs in High-Z for additional flexibility in system design. Writing to these devices is accomplished when write enable (WE\) and CE\ inputs are both LOW. Reading is accomplished when WE\ remains HIGH and CE\ and OE\ go LOW. The device offers a reduced power standby mode when disabled. This allows system designs to achieve low standby power requirements. All devices operate from a single +5V power supply and all inputs and outputs are fully TTL compatible. For more products and information please visit our web site at www.austinsemiconductor.com AS5C2568 Rev. 2.6 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 SRAM S RAM Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM A0 Vcc AS5C2568 DECODER 256 x 1024 MEMORY ARRAY GND A14 I/O0 I/O DATA CIRCUIT I/O7 COLUMN I/O 9A128-1 CE\ OE\ CONTROL CIRCUIT WE\ TRUTH TABLE MODE STANDBY READ READ WRITE OE\ X L H X CE\ H L L L WE\ X H H L DQ HIGH-Z Q HIGH-Z D POWER STANDBY ACTIVE ACTIVE ACTIVE AS5C2568 Rev. 2.6 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 SRAM S RAM Austin Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS* Voltage on Any Input or DQ Relative to Vss..................................................................-0.5V to Vcc +0.5V Voltage on Vcc Supply Relative to Vss.......................-1V to +7V Storage Temperature..............................................-65oC to +150oC Power Dissipation.......................................................................1W Short Circuit Output Current............................................20mA Lead Temperature (soldering 10 seconds)........................+260oC Max. Junction Temperature.................................................+175oC AS5C2568 *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55oC < TC < 125oC or -40oC to +85oC; VCC = 5.0V +10%) DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage 0V