AS5LC512K8

SRAM S RAM Austin Semiconductor, Inc. 512K x 8 SRAM 3.3 VOLT HIGH SPEED SRAM with CENTER POWER PINOUT AVAILABLE AS MILITARY SPECIFICATIONS •MIL-STD-883 for Ceramic •Extended Temperature Plastic (COTS) AS5LC512K8 PIN ASSIGNMENT (Top View) 36-Pin PSOJ (DJ) 36-Pin CLCC (EC) FEATURES • Ultra High Speed Asynchronous Operation • Fully Static, No Clocks • Multiple center power and ground pins for improved noise immunity • Easy memory expansion with CE\ and OE\ options • All inputs and outputs are TTL-compatible • Single +3.3V Power Supply +/- 0.3V • Data Retention Functionality Testing • Cost Efficient Plastic Packaging • Extended Testing Over -55ºC to +125ºC for plastics 36-Pin Flat Pack (F) OPTIONS • Timing 12ns access 15ns access 20ns access 25ns access • Operating Temperature Ranges Military (-55oC to +125oC) Industrial (-40oC to +85oC) • Package(s) Ceramic Flatpack Plastic SOJ (400 mils wide) Ceramic LCC • 2V data retention/low power MARKING -12 -15 -20 -25 XT IT F DJ EC L No. 307 No. 210 GENERAL DESCRIPTION The AS5LC512K8 is a 3.3V high speed SRAM. It offers flexibility in high-speed memory applications, with chip enable (CE\) and output enable (OE\) capabilities. These features can place the outputs in High-Z for additional flexibility in system design. Writing to these devices is accomplished when write enable (WE\) and CE\ inputs are both LOW. Reading is accomplished when WE\ remains HIGH and CE\ and OE\ go LOW. As a option, the device can be supplied offering a reduced power standby mode, allowing system designers to meet low standby power requirements. This device operates from a single +3.3V power supply and all inputs and outputs are fully TTL-compatible. The AS5LC512K8DJ offers the convenience and reliability of the AS5LC512K8 SRAM and has the cost advantage of a plastic encapsulation. For more products and information please visit our web site at www.austinsemiconductor.com AS5LC512K8 Rev. 2.1 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 SRAM S RAM Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM AS5LC512K8 VCC GND INPUT BUFFER DQ8 ROW DECODER 4,194,304-BIT MEMORY ARRAY 1024 ROWS X 4096 COLUMNS A0-A18 I/O CONTROLS DQ1 CE\ OE\ COLUMN DECODER WE\ *POWER DOWN *On the low voltage Data Retention option. PIN FUNCTIONS A0 - A18 Address Inputs Write Enable Chip Enable Output Enable Data Inputs/Outputs Power Ground No Connection TRUTH TABLE MODE OE\ CE\ WE\ STANDBY X H X READ L L H NOT SELECTED H L H WRITE X L L X = Don’t Care WE\ I/O HIGH-Z Q HIGH-Z D POWER STANDBY ACTIVE ACTIVE ACTIVE CE\ OE\ I/O0 - I/O7 VCC VSS NC AS5LC512K8 Rev. 2.1 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 SRAM S RAM Austin Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS* Voltage on Vcc Supply Relative to Vss Vcc .........................................................................-.5V to 4.6V Storage Temperature .....................................-65°C to +150°C Short Circuit Output Current (per I/O)…........................20mA Voltage on any Pin Relative to Vss........................-.5V to 4.6V Maximum Junction Temperature**..............................+150°C Power Dissipation ................................................................1W AS5LC512K8 *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ** Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow, and humidity. ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55oC < TA < +125oC & -40oC < TA < +85oC ; Vcc = 3.3V +0.3%) MAX DESCRIPTION CONDITIONS CE\ < VIL; Vcc = MAX Power Supply Current: Operating f = MAX = 1/t RC Outputs Open "L" Version Only CE\ > VIH, All other inputs < VIL, Vcc = MAX, f = 0, Outputs Open Power Supply Current: Standby "L" Version Only CE\ > Vcc -0.2V; Vcc = MAX VINVcc -0.2V; f = 0 "L" Version Only ISBCLP 9 9 9 9 mA ICCSP ICCLP 80 70 60 55 mA 3, 2 60 50 40 35 mA SYM -12 -15 -20 -25 UNITS NOTES ISBTSP 20 20 20 20 mA ISBTLP ISBCSP 15 15 15 15 mA 15 15 15 15 mA

       
        
    
    
 
            *        "    "     "      CAPACITANCE PARAMETER Input Capacitance Output Capactiance AS5LC512K8 Rev. 2.1 08/09 "# $#%&   
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 '  )! CONDITIONS TA = 25 C, f = 1MHz VIN = 0 o  



    (  μ! μ!      SYMBOL CI Co MAX 9 6 UNITS pF pF NOTES 4 4 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 SRAM S RAM Austin Semiconductor, Inc. AS5LC512K8 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (-55oC < TA < +125oC or -40oC to +85oC; Vcc = 3.3V +0.3%) DESCRIPTION READ CYCLE Read Cycle Time Address Access Time Chip Enable Access Time Output Hold From Address Change Chip Enable to Output in Low-Z Chip Disable to Output in High-Z Output Enable Acess Time Output Enable to Output in Low-Z Output Disable to Output in High-Z WRITE CYCLE WRITE Cycle Time Chip Enable to End of Write Address Valid to End of Write Address Setup Time Address Hold From End of Write WRITE Pulse Width Data Setup Time Data Hold Time Write Disable to Output in Low-Z Write Enable to Output in High-Z SYM tRC tAA tACE tOH tLZCE tHZCE tAOE tLZOE tHZOE tWC tCW tAW tAS tAH tWP tDS tDH tLZWE tHZWE 12 8 8 0 0 10 6 1 2 5 0 6 15 10 10 0 0 12 7 1 2 6 2 2 6 6 0 7 20 12 12 0 0 15 8 1 2 7 -12 MIN 12 12 12 2 2 7 7 0 8 25 13 13 0 0 15 8 1 2 7 MAX MIN 15 15 15 2 2 8 8 0 9 -15 MAX MIN 20 20 20 2 2 9 9 -20 MAX MIN 25 25 25 -25 MAX UNITS NOTES ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4, 6, 7 4, 6, 7 4, 6, 7 4, 6, 7 4, 6, 7 4, 6, 7 AS5LC512K8 Rev. 2.1 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 SRAM S RAM Austin Semiconductor, Inc. AC TEST CONDITIONS Input pulse levels ...................................................... Vss to 3.0V Input rise and fall times ......................................................... 3ns Input timing reference levels ............................................... 1.5V Output reference levels ........................................................ 1.5V Output load ................................................. See Figures 1 and 2 3.3V RL = 50Ω Q ZO=50Ω AS5LC512K8 VL = 1.5V 30 pF Q 353Ω 319Ω 5 pF Fig. 1 Output Load Equivalent Fig. 2 Output Load Equivalent NOTES 1. All voltages referenced to VSS (GND). 2. ICC limit shown is for absolute worst case switching of ADDR, ADDR\, ADDR, etc. 3. ICC is dependent on output loading and cycle rates. 4. This parameter is guaranteed but not tested. 5. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. 6. tLZCE, tLZWE, tLZOE, t HZCE, tHZOE and tHZWE are specified with CL = 5pF as in Fig. 2. Transition is measured ±200mV from steady state voltage. 7. At any given temperature and voltage condition, t HZCE is less than tLZCE, and tHZWE is less than t LZWE. 8. WE\ is HIGH for READ cycle. 9. 10. 11. 12. 13. 14. 15. Device is continuously selected. Chip enables and output enables are held in their active state. Address valid prior to, or coincident with, latest occurring chip enable. t RC = Read Cycle Time. Chip enable and write enable can initiate and terminate a WRITE cycle. Output enable (OE\) is inactive (HIGH). Output enable (OE\) is active (LOW). ASI does not warrant functionality nor reliability of any product in which the junction temperature exceeds 150°C. Care should be taken to limit power to acceptable levels. DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only) DESCRIPTION Vcc for Retention Data Data Retention Current Chip Deselect to Data Operation Recovery Time AS5LC512K8 Rev. 2.1 08/09 CONDITIONS CE\ > VCC -0.2V VIN > VCC -0.2 or 0.2V Vcc = 2.0V SYM VDR ICCDR tCDR tR MIN 2 MAX UNITS V NOTES 6.5 0 20 mA ns ms 4 4, 11 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 653321 4 4 21 4321 4321 4321 4321 765412154 143 376 576 765454321321 376 765452121321 14354 52151321 32154 765414321321 14354 376 4 76 765452121321 3765 765412121321 34324 5 7654320 765 65 1 76543219876543214321 211 7214321 0 76542119876543214321 210 320987654365 7 76543219876543214321 765 76542119876543214321 210 320 765 76543219876543214321 765 VIH- 7432 565410987654321 5 7654309 543212187654321 7654309 5432121 654309 743232987654321 543212187654321 54321 7654309 565410187654321 7654121 543212187654321 54323 1 743212187654321 543212187654321 7654309 5432309 54321 tR 1. WE\ is HIGH for READ cycle. 2. Device is continuously selected. Chip enables and output enables are held in their active state. 654321 654321 654321 654321 543210987654321 543210987654321 654321 4321 543210987654321 543210987654321 543210987654321 654321 4321 4321 543210987654321 654321 654321 543210987654321 543210987654321 4321 t CDR NOTES: AS5LC512K8 Rev. 2.1 08/09 I/O, DATA IN & OUT I/O, DATA IN & OUT CE\ ADDRESS ADDRESS VCC VIL- CE\ Icc READ CYCLE NO. 11, 2 (Address Controlled, CE\ = OE\ = VIL, WE\ = VIH) Previous Data Valid Austin Semiconductor, Inc. LOW VCC DATA RETENTION WAVEFORM High-Z READ CYCLE NO. 2 (WE\ = VIH) tOH 4.5V DATA RETENTION MODE t LZCE t ACE t PU t LZOE 6 tAA VDR > 2V t AOE V ALID VDR t RC t RC Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4.5V Data Valid Data Valid t HZOE t HZCE AS5LC512K8 t PD Undefined Don’t Care SRAM S RAM 654321 654321 654321 654321 654321 t AS ADDRESS CE\ Austin Semiconductor, Inc. WRITE CYCLE NO. 11 (CE Controlled) t AS t AW t CW t WC t WP1 654 876543210987654321321 654 876543210987654321321 876543210987654321321 76543210987654321 876543210987654321321 654 8 654 0987654432109876543210987654321 321 6321210987654321098765432 543 09876564321098765432109876543211 45432109876543210987654321 09876565432109876543210987654321 4543210987654321098765432 321 09876564321098765432109876543211 4432109876543210987654321 321 I/O, DATA OUT I/O, DATA IN ADDRESS WE\ WRITE CYCLE NO. 21, 2 (Write Enabled Controlled) High-Z t AW t CW 56543210987654343 7 765 76543210987654343 5432109876543212121 765 7432109876543212121 5432109876543212121 6543210987654343 765 7432109876543212121 5432109876543212121 765 56543210987654343 76543210987654343 765 tAH 0987654321 1098 321 098765409876543210987654321 1098 098765432176543210987654321 409876543210987654321 132176543210987654321 0987654321098765432 098765109876543210987654321 1098 098765432176543210987654321 1 1. 2. NOTES: AS5LC512K8 Rev. 2.1 08/09 Chip enable and write enable can initiate and terminate a WRITE cycle. Output enable (OE\) is inactive (HIGH). I/O, DATA OUT I/O, DATA IN WE\ CE\ High-Z 7 t WC Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. t WP1 Data Valid t DS Data Valid tAH tDH tDH High-Z High-Z AS5LC512K8 SRAM S RAM SRAM S RAM Austin Semiconductor, Inc. AS5LC512K8 WRITE CYCLE NO. 31, 2, 3 (WE Controlled) t WC ADDRESS t AW t CW tAH CE\ t AS WE\ t WP2 t DS DATA IN t HZWE Data Valid t LZWE DATA OUT Data Undefined High-Z NOTES: 1. At any given temperature and voltage condition, tHZCE is less than tLZCE, and tHZWE is less than tLZWE. 2. Chip enable and write enable can initiate and terminate a WRITE cycle. 3. Output enable (OE\) is active (LOW). AS5LC512K8 Rev. 2.1 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 7654 6654321098765432321 7 76543210987654311 6543210987654321121 6543210987654323 7654 7543210987654321121 6543210987654321121 7654 76543210987654323 65432109876543223 7654 tDH 654321 654321 654321 654321 987654321876543210987654321 232187654321098765432 109 987654109876543210987654321 4321876543210987654321 2109 109 987652109876543210987654321 2109876543210987654321 109 1 987654321876543210987654321 SRAM S RAM Austin Semiconductor, Inc. AS5LC512K8 MECHANICAL DEFINITIONS* ASI Case #307 (Package Designator F) L E Pin 1 identifier area 36 1 D1 *All measurements are in inches. AS5LC512K8 Rev. 2.1 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 87654321 87654321 87654321 87654321 87654321 87654321 87654321 87654321 e b D Bottom View S Top View c Q E2 A SYMBOL A b c D D1 E E2 e L Q ASI SPECIFICATIONS MIN MAX 0.096 0.125 0.015 0.022 0.003 0.009 0.910 0.930 0.840 0.860 0.505 0.515 0.385 0.397 0.050 BSC 0.250 0.370 0.020 0.045 9 SRAM S RAM Austin Semiconductor, Inc. AS5LC512K8 MECHANICAL DEFINITIONS* Package Designator DJ SYMBOL A A1 A2 B b C D E E1 E2 e ASI SPECIFICATIONS MIN MAX 0.128 0.148 0.025 --0.082 --0.015 0.020 0.026 0.032 0.007 0.013 0.920 0.930 0.435 0.445 0.395 0.405 0.370 BSC 0.050 BSC *All measurements are in inches. AS5LC512K8 Rev. 2.1 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 10 SRAM S RAM Austin Semiconductor, Inc. AS5LC512K8 MECHANICAL DEFINITIONS* ASI Case #210 (Package Designator EC) P A Pin 1 identifier area *All measurements are in inches. AS5LC512K8 Rev. 2.1 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7654321 7654321 7654321 7654321 7654321 7654321 7654321 7654321 7654321 7654321 L2 1 D 36 L e B D1 E R A1 SYMBOL A A1 B D D1 E e L L2 P R ASI SPECIFICATIONS MIN MAX 0.080 0.100 0.054 0.066 0.022 0.028 0.910 0.930 0.840 0.860 0.445 0.460 0.050 BSC 0.100 TYP 0.115 0.135 --0.006 0.009 TYP 11 SRAM S RAM Austin Semiconductor, Inc. AS5LC512K8 ORDERING INFORMATION EXAMPLE: AS5LC512K8F-12L/XT Device Number AS5LC512K8 AS5LC512K8 AS5LC512K8 AS5LC512K8 Package Type F F F F Speed ns -12 -15 -20 -25 Options** L L L L Process /* /* /* /* EXAMPLE: AS5LC512K8DJ-20L/883C Device Number AS5LC512K8 AS5LC512K8 AS5LC512K8 AS5LC512K8 Package Type DJ DJ DJ DJ Speed ns -12 -15 -20 -25 Options** L L L L Process /* /* /* /* EXAMPLE: AS5LC512K8EC-15L/IT Device Number AS5LC512K8 AS5LC512K8 AS5LC512K8 AS5LC512K8 Package Type EC EC EC EC Speed ns -12 -15 -20 -25 Options** L L L L Process /* /* /* /* *AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Extended Temperature Range 883C = Full Military Processing1 **OPTIONS DEFINITIONS L = 2V Data Retention / Low Power -40oC to +85oC -55oC to +125oC -55oC to +125oC NOTES: 1. 883C process available with ceramic packaging only. AS5LC512K8 Rev. 2.1 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 12 SRAM S RAM Austin Semiconductor, Inc. DOCUMENT TITLE 512K x 8 SRAM 3.3 VOLT HIGH SPEED SRAM with CENTER POWER PINOUT AS5LC512K8 Rev # 2.1 History Pg 1: Changed 0.3% to 0.3V Release Date August 2009 Status Release AS5LC512K8 Rev. 2.1 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 13