AS5SS256K18

SSRAM Austin Semiconductor, Inc. 256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through FEATURES • Fast access times: 8, 10, and 15ns • Fast clock speed: 113, 100, and 66 MHz • Fast clock and OE\ access times • Single +3.3V +0.3V/-0.165V power supply (VDD) • SNOOZE MODE for reduced-power standby • Common data inputs and data outputs • Individual BYTE WRTIE control and GLOBAL WRITE • Three chip enables for simple depth expansion and address pipelining • Clock-controlled and registered addresses, data I/Os and control signals • Interally self-timed WRITE cycle • Burst control pin (interleaved or linear burst) • Automatic power-down • Low capacitive bus loading • Operating Temperature Ranges: - Military -55oC to +125oC - Industrial -40oC to +85oC NC NC NC V DD Q VSS NC NC DQb DQb VSS V DD Q DQb DQb VSS V DD NC VSS DQb DQb V DD Q VSS DQb DQb DQPb NC VSS V DD Q NC NC NC AS5SS256K18 PIN ASSIGNMENT (Top View) 100-pin TQFP SA SA CE\ CE2 NC NC bwB\ BWa\ CE2\ V DD VSS CLK GW\ BWE\ OE\ ADSC\ ADSP\ ADV\ SA SA OPTIONS • Timing 7.5ns/8ns/113 MHz 8.5ns/10ns/100 MHz 10ns/15ns/66 MHz • Packages 100-pin TQFP • Operating Temperature Ranges: - Military -55oC to +125oC - Industrial -45oC to +85oC *available as IT only. MARKING -8* -9 -10 DQ IT XT No. 1001 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 1 1 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SA NC NC V DD Q VSS NC DQPa DQa DQa VSS V DD Q DQa DQa VSS NC V DD ZZ DQa DQa V DD Q VSS DQa DQa NC NC VSS V DD Q NC NC NC **pins 42,43 reserved for future address expansion for 8Mb, 16Mb densities. For more products and information please visit our web site at www.austinsemiconductor.com GENERAL DESCRIPTION The Austin Semiconductor, Inc. Synchronous Burst SRAM family employs high-speed, low power CMOS designs that are fabricated using an advanced CMOS process. ASI’s 4Mb Synchronous Burst SRAMs integrate a 256K x 18, SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE\), two additional chip enables for easy depth expansion (CE2\, AS5SS256K18 Rev. 2.0 12/00 CE2), burst control inputs (ADSC\, ADSP\, ADV\), byte write enables (BWx\) and global write (GW\). Asynchronous inputs include the output enable (OE\), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. The data-out (Q), enabled by OE\, is also asynchronous. WRITE cycles can be from one to two bytes wide, as controlled by the write control inputs. Burst operation can be initiated with either address status processor (ADSP\) or address status controller (ADSC\) inputs. Subsequent burst addresses can be internally generated as controlled by the burst advance input (ADV\). Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During WRITE cycles on this x18 device BWa\ controls DQa pins and DQPa; BWb\ controls DQb pins and DQPb. GW\ LOW causes all bytes to be written. Parity bits are available on this device. ASI’s 4Mb Synchronous Burst SRAMs operate from a +3.3V VDD power supply, and all inputs and outputs are TTL-compatible. The device is ideally suited for 486, Pentium®, and PowerPC systems and those systems that benefit from a wide synchronous data bus. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 MODE SA SA SA SA SA1 SA0 DNU DNU VSS V DD NF** NF** SA SA SA SA SA SA SA SSRAM Austin Semiconductor, Inc. PIN DESCRIPTIONS PIN NUMBERS 37, 36, 32-35, 44-50, 80-82, 99, 100 93, 94 AS5SS256K18 SYM SA0, SA1, SA BWa\ BWb\ TYPE Input Input DESCRIPTION Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A byte write enables is LOW for a WRITE cycle and HIGH for a READ cycle. BWa\ controls DQa pins and DQPa; BWb\ controls DQb pins and DQPb. Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Global Write: This active LOW input allows a full 18-bit WRITE to occur independent of the BWE\ and BWx\ lines and must meet the setup and hold times around the rising edge of CLK. Clock: This signal registers the addresses, data, chip enables, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock’s rising edge. Synchronous Chip Enable: This active LOW input is used to enable the device and Conditions the internal use of ADSP\. CE\ is sampled only when a new external address is loaded. Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded. Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded. Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. Synchronous Address Advance: This active LOW input is used to advance the internal burst counter, controlling burst access after the external address is loaded. A HIGH on this pin effectively causes wait states to be generated (no address advance). To ensure use of correct address during WRITE cycle, ADV\ must be HIGH at the rising edge of the first clock after an ADSP\ cycle is initiated. Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ is performed using the new address, independent of the byte write enables and ADSC\, but dependent upon CE\, CE2, and CE2\. ADSP\ is ignored if CE\ is HIGH. Power-down state is entered if CE2 if LOW or CE2\ is HIGH. Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ or WRITE is performed using the new address if CE\ is LOW. ADSC\ is also used to place the chip into powerdown state when CE\ is HIGH. Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. A NC or HIGH on this pin selects INTERLEAVED BURST. Do not alter input state while device is operating. Snooze Enable: This active HIGH, asynchronous input causes the device to enter a lowpower standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored. SRAM Data I/Os: Byte "a" is DQa pins; Byte "b" is DQb pins. Input data must meet setup and hold times around the rising edge of CLK. 87 88 BWE\ GW\ Input Input 89 CLK Input 98 CE\ Input 92 97 86 83 CE2\ CE2 OE\ ADV\ Input Input Input Input 84 ADSP\ Input 85 ADSC\ Input 31 MODE Input 64 ZZ Input (a) 58, 59, 62, 63, 68, 69, 72, 73 (b) 8, 9, 12,13, 18, 19, 22, 23 74, 24 15, 41,65, 91 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 14, 17, 21, 26, 40, 55, 60, 67 71, 76, 90 38, 39 1-3, 6, 7, 16,25, 28-30, 51-53, 56,57, 66, 75, 78, 79, 95, 96 42, 43 DQa DQb Input/ Output NC/DQPa NC/DQPb VDD VDDQ VSS NC/ I/O Supply Supply Supply No Connect/Parity Data I/Os: Byte "a" is DQPa pins; Byte "b" is DQPb pins. Power Supply: See DC Electrical Characteristics and Operating Conditions for range. Isolated Output Buffer Supply: See DC Electrical Characterics and Operating Conditions for range. Ground: GND DNU NC ------- Do Not Use: These signals may either be unconnected or wired to GND to improve package heat dissipation. No Connect: These signals are not internally connected and may be connected to ground to improve package heat dissipation. No Function: These pins are internally connected to the die and will have the capacitance of input pins. It is allowable to leave these pins unconnected or driven by signals. NF AS5SS256K18 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 SSRAM Austin Semiconductor, Inc. AS5SS256K18 INTERLEAVED BURST ADDRESS TABLE (MODE=NC OR HIGH) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X…X00 X…X01 X…X10 X…X11 X…X01 X…X00 X…X11 X…X10 X…X10 X…X11 X…X00 X…X01 X…X11 X…X10 X…X01 X…X00 LINEAR BURST ADDRESS TABLE (MODE=LOW) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X…X00 X…X01 X…X10 X…X11 X…X01 X…X10 X…X11 X…X00 X…X10 X…X11 X…X00 X…X01 X…X11 X…X00 X…X01 X…X10 PARTIAL TRUTH TABLE FOR WRITE COMMANDS FUNCTION READ READ WRITE Byte "a" WRITE Byte "b" WRITE All Bytes WRITE All Bytes GW\ H H H H H L BWE\ H L L L L X BWa\ X H L H L X BWb\ X H H L L X NOTE: Using BWE\ and BWa\ through BWb\, any one or more bytes may be written. FUNCTIONAL BLOCK DIAGRAM 18 SA0, SA1, SA MODE ADV\ CLK ADDRESS REGISTER 18 2 BINARY COUNTER AND LOGIC Q0 CLR Q1 SA0-SA1 SA1' 16 18 SA0' ADSC\ ADSP\ BYTE "b" WRITE DRIVER BWb\ BYTE "b" WRITE REGISTER 9 9 9 BWa\ BWE\ GW\ CE\ CE2 CE2\ OE\ BYTE "a" WRITE REGISTER BYTE "a" WRITE DRIVER 9 256K x 9 x 2 MEMORY ARRAY 18 SENSE AMPS 18 OUTPUT BUFFERS 18 DQs DQPa DQPb 18 ENABLE REGISTER 2 INPUT REGISTERS NOTE: The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information. AS5SS256K18 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 SSRAM Austin Semiconductor, Inc. TRUTH TABLE OPERATION DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down SNOOZE MODE, Power-Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst ADDRESS USED NONE NONE NONE NONE NONE NONE EXTERNAL EXTERNAL EXTERNAL EXTERNAL EXTERNAL NEXT NEXT NEXT NEXT NEXT NEXT CURRENT CURRENT CURRENT CURRENT CURRENT CURRENT CE\ CE2\ CE2 ZZ ADSP\ ADSC\ ADV\ WRITE\ OE\ CLK H L L L L X L L L L L X X H H X H X X H H X H X X H X H X L L L L L X X X X X X X X X X X X X L X L X X H H H H H X X X X X X X X X X X X L L L L L H L L L L L L L L L L L L L L L L L X L L H H X L L H H H H H X X H X H H X X H X L X X L L X X X L L L H H H H H H H H H H H H X X X X X X X X X X X L L L L L L H H H H H H X X X X X X X X L H H H H H H L L H H H H L L X X X X X X L H X L H L H L H X X L H L H X X L-H L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ High-Z High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D AS5SS256K18 NOTES: 1. X means “Don’t Care.” \ means active LOW. H means logic HIGH. L means logic LOW. 2. For WRITE\, L means any one or more byte write enable signals (BWa\, BWb\) and BWE\ are LOW or GW\ is LOW. WRITE\ = H for a ll BWx\, BWE\, GW\ HIGH. 3. BWa\ enables WRITEs to DQas and DQPa. BWb\ enables WRITEs to DQbs and DQPb. 4. All inputs except OE\ and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE\ must be HIGH before the input data setup time and held HIGH throughout the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP\ LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE\ LOW or GW\ LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification. AS5SS256K18 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 SSRAM Austin Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS* Voltage on VDD Supply Relative to VSS............-0.5V to +4.6V Voltage on VDDQ Supply Relative to VSS.........-0.5V to +4.6V Storage Temperature (plastic) .....................-55°C to +125°C Max Junction Temperature**.......................................+150°C Short Circuit Output Current..........…...........................100mA AS5SS256K18 *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Maximum junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (-55oC < TA < +125oC and -40oC VIH; All inputs < VSS +0.2 or > VDDQ -0.2; Cycle time > KC (MIN) t ISB4 100 85 65 mA 3, 4 NOTES: 1. VDDQ = +3.3V +0.3V/-0.165V for 3.3V I/O configuration. 2. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and greater output loading. 3. “Device deselected” means device is in power-down mode as defined in the truth table. “Device selected” means device is active (not in power-down mode). 4. Typical values are measured at 3.3V, 25°C and 15ns cycle time. AS5SS256K18 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 SSRAM Austin Semiconductor, Inc. AS5SS256K18 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 1) -55oC < TA < +125oC and -40oC