AS8E512K8

EEPROM Austin Semiconductor, Inc. 512K x 8 EEPROM EEPROM Module AVAILABLE AS MILITARY SPECIFICATIONS • • SMD 5962-93091 MIL-STD-883 AS8E512K8 PIN ASSIGNMENT (Top View) 32-Pin DIP & 32-Pin SOJ (CW) A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O 0 I/O 1 I/O 2 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc WE\ A17 A14 A13 A8 A9 A11 OE\ A10 CE\ I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 FEATURES • • • • • • • • Access times of 150, 200, 250, and 300 ns JEDEC Compatible Pinout 10,000 Write Endurance Cycles 10 year Data Retention Organized as 512Kx8 Operation with single 5 volt supply Low power CMOS TTL Compatible Inputs and Outputs OPTIONS • Packaging 32 pin 600 MIL DIP Timing 150ns 200ns 250ns 300ns Operating Temperature Range -Military (-55oC to +125oC) -Industrial (-40oC to +85oC) MARKING CW No. 112 • -150 -200 -250 -300 • XT IT PIN DESCRIPTION A0 - A18 Address Inputs I/O 0 - I/O 7 Data Inputs/Outputs CE\ Chip Select OE\ Output Enable WE\ Write Enable Vcc +5.0V Power GENERAL DESCRIPTION The Austin Semiconductor, Inc. AS8E512K8 is a 4 Megabit CMOS EEPROM Module organized as 512K x 8-bits. It is built with four 128K x 8 components and a single decoder. The AS8E512K8 achieves high speed access, low power consumption and high reliability by employing advanced CMOS memory technology. Software data protection is implemented using the JEDEC Optional Standard algorithm. This military temperature grade product is ideally suited for military and space applications requiring high reliability. A0 - A16 I/O 0 - I/O 7 WE\ OE\ U1 A0 - A16 I/O 0 - I/O 7 WE\ OE\ CE\ U2 A0 - A16 I/O 0 - I/O 7 WE\ OE\ CE\ U3 A0 - A16 I/O 0 - I/O 7 WE\ OE\ CE\ U4 A0 - A16 I/O 0 - I/O 7 WE\ OE\ CE\ A17 A18 CE\ 1 of 4 Decoder For more products and information please visit our web site at www.austinsemiconductor.com Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS8E512K8 Rev. 3.1 6/05 1 EEPROM Austin Semiconductor, Inc. DEVICE OPERATION: The AS8E512K8 is an electrically erasable and programmable memory module that is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 128-byte-page register to allow writing of up to 128 bytes of data simultaneously. During a write cycle, the address and 1 to 128 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA\ polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. AS8E512K8 TOGGLE BIT: In addition to DATA\ Polling the AS8E512K8 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O 6 toggling between one and zero. Once the write has completed, I/O 6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transitions of the host power supply. The E2 module has incorporated both hardware and software features that will protect the memory against inadvertent writes. READ: The AS8E512K8 is accessed like a Static RAM. When CE\ and OE\ are low and WE\ is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE\ or OE\ is high. This dual-line control gives designers flexibility in preventing bus contention in their system. HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the AS8E512K8 in the following ways: (a) Vcc sense - if Vcc is below 3.8V (typical) the write function is inhibited; (b) Vcc power-on delay - once Vcc has reached 3.8V the device will automatically time out 5ms (typical) before allowing a write; (c) write inhibit - holding any one of OE\ low, CE\ high or WE\ high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typical) on the WE\ or CE\ inputs will not initiate a write cycle. BYTE WRITE: A low pulse on the WE\ or CE\ input with CE\ or WE\ low (respectively) and OE\ high initiates a write cycle. The address is latched on the falling edge of CE\ or WE\, whichever occurs last. The data is latched by the first rising edge of CE\ or WE\. Once a byte, word or double word write has been started it will automatically time itself to completion. SOFTWARE DATA PROTECTION: A software controlled data protection feature has been implemented on theAS8E512K8. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user and is shipped with SDP disabled, SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to Software Data Protection Algorithm). After writing the three byte command sequence and after tWC for each of the die the entire AS8E512K8 will be protected from inadvertent write operations. It should be noted, that once protected the host may still perform a byte or page write to the AS8E512K8. This is done by preceding the data to be written by the same three byte command sequence used to enable SDP. Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable SDP and SDP will protect the AS8E512K8 during power-up and power-down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation. After setting SDP, any attempt to write to the device without the three byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, read operations will effectively be polling operations. PAGE WRITE: The page write operation of the AS8E512K8 allows 1 to 128 BWDWs of data to be written into the device during a single internal programming period. Each new BWDW must be written within 150us (tBLC) of the previous BWDW. If the tBLC limit is exceeded the AS8E512K8 will cease accepting data and commence the internal programming operation. For each WE\ high to low transition during the page write operation, A7-A18 must be the same. The A0-A6 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. DATA\ POLLING: The AS8E512K8 features DATA\ Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O 7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA\ Polling may begin at anytime during the write cycle. AS8E512K8 Rev. 3.1 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 EEPROM Austin Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS* Voltage on Vcc Supply Relative to Vss Supply/Input Voltage Range1.........................-0.6V to +6.25V DC Voltage on OE\ and A9....................................-0.6V to +13.5V DC Voltage on all other pins..................................-0.6V to +6.25V DC Storage Temperature.............................................-65°C to +150°C Operating Temperature, TA (Ambient)................-55oC to +125oC Lead Temperature (soldering 10 seconds)........................+300oC Maximum Junction Temperature**....................................+165°C NOTE: 1. Including NC pins, with respect to ground. AS8E512K8 *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ** Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. PIN CAPACITANCE (f= 1MHz, T = 25° C)(1) SYMBOL CADD, OE\, WE\ CI/O CCE\ CONDITIONS VIN = 0V, f = 1MHz VOUT = 0V, f = 1MHz VIN = 0V, f = 1MHz MAX 45 50 10 UNIT pF pF pF OPERATING MODES MODE Read Write 2 CE\ VIL VIL VIH X X X OE\ VIL VIH X 1 WE\ VIH VIL X VIH X X I/O DOUT DIN High Z Standby/Write Inhibit Write Inhibit Write Inhibit Output Disable NOTE: 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. X VIL VIH High Z ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55oC