MT5C1008SOJ-55

SRAM S RAM Austin Semiconductor, Inc. 128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS •SMD 5962-89598 •MIL-STD-883 NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MT5C1008 PIN ASSIGNMENT (Top View) 32-Pin DIP (C, CW) 32-Pin CSOJ (SOJ) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE\ A13 A8 A9 A11 OE\ A10 CE\ DQ8 DQ7 DQ6 DQ5 DQ4 NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 VSS 32-Pin LCC (EC) 32-Pin SOJ (DCJ) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE\ A13 A8 A9 A11 OE\ A10 CE\ DQ8 DQ7 DQ6 DQ5 DQ4 FEATURES • • • • • • High Speed: 12, 15, 20, 25, 35, 45, 55 and 70 ns Battery Backup: 2V data retention Low power standby High-performance, low-power CMOS process Single +5V (+10%) Power Supply Easy memory expansion with CE1\, CE2, and OE\ options. • All inputs and outputs are TTL compatible 32-Pin LCC (ECA) 4 3 2 1 32 31 30 NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE\ A13 A8 A9 A11 OE\ A10 CE\ DQ8 DQ7 DQ6 DQ5 DQ4 OPTIONS • Timing 12ns access 15ns access 20ns access 25ns access 35ns access 45ns access 55ns access 70ns access • Package(s)• Ceramic DIP (400 mil) Ceramic DIP (600 mil) Ceramic LCC Ceramic LCC Ceramic Flatpack Ceramic SOJ Ceramic SOJ • 2V data retention/low power MARKING -12 (contact factory) -15 -20 -25 -35 -45 -55* -70* A7 A6 A5 A4 A3 A2 A1 A0 DQ1 5 6 7 8 9 10 11 12 13 A12 A14 A10 6 NC VCC A15 CE2 32-Pin Flat Pack (F) 29 28 27 26 25 24 23 22 21 WE \ A13 A8 A9 A11 OE \ A10 CE1\ DQ8 14 15 16 17 18 19 20 DQ2 DQ3 VSS DQ4 DQ5 DQ6 DQ7 GENERAL DESCRIPTION The MT5C1008 SRAM employs high-speed, low power CMOS designs using a four-transistor memory cell, and are fabricated using double-layer metal, double-layer polysilicon technology. For design flexibility in high-speed memory applications, this device offers dual chip enables (CE1\, CE2) and output enable (OE\). These control pins can place the outputs in High-Z for additional flexibility in system design. All devices operate from a single +5V power supply and all inputs and outputs are fully TTL compatible. Writing to these devices is accomplished when write enable (WE\) and CE1\ inputs are both LOW and CE2 is HIGH. Reading is accomplished when WE\ and CE2 remain HIGH and CE1\ and OE\ go LOW. The devices offer a reduced power standby mode when disabled, allowing system designs to achieve low standby power requirements. The “L” version offers a 2V data retention mode, reducing current consumption to 1mA maximum. C CW EC ECA F DCJ SOJ L No. 111 No. 112 No. 207 No. 208 No. 303 No. 501 No. 507 *Electrical characteristics identical to those provided for the 45ns access devices. For more products and information please visit our web site at www.austinsemiconductor.com MT5C1008 Rev. 6.5 7/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 SRAM S RAM Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM VCC GND MT5C1008 A A A A A A A A A ROW DECODER DQ8 I/O CONTROL 1,048,576-BIT MEMORY ARRAY DQ1 (LSB) CE1\ CE2 COLUMN DECODER (LSB) OE\ WE\ POWER DOWN AAAAAAAA NOTE: The two least significant row address bits (A8 and A6) are encoded using gray code. TRUTH TABLE MODE STANDBY STANDBY READ READ WRITE OE\ X X L H X CE1\ H X L L L CE2 X L H H H WE\ X X H H L DQ HIGH-Z HIGH-Z Q HIGH-Z D POWER STANDBY STANDBY ACTIVE ACTIVE ACTIVE MT5C1008 Rev. 6.5 7/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 SRAM S RAM Austin Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS* Supply Voltage Range (Vcc)...............................-.5V to +6.0V Storage Temperature ....................................-65°C to +150°C Short Circuit Output Current (per I/O)….......................20mA Voltage on any Pin Relative to Vss................-.5V to Vcc+1 V Max Junction Temperature**.......................................+150°C Power Dissipation .....................................................................1 W MT5C1008 *Stresses at or greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods will affect reliability. Refer to page 17 of this datasheet for a technical note on this subject. ** Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow, and humidity. ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55oC < TC < 125oC & -45oC to +85oC; VCC = 5.0V +10%) DESCRIPTION CONDITIONS SYM VIH VIL MIN 2.2 -0.5 -10 -10 2.4 MAX VCC+0.5 0.8 10 10 UNITS V V µA µA V NOTES 1 1, 2 Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage 0V (VCC - 0.2V) Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VIN > (VCC - 0.2V) or < 0.2V, f=0 VCC = 2V ICCDR 1.0 mA CONDITIONS SYMBOL VDR MIN 2 MAX --UNITS NOTES V tCDR tR 0 tRC --- ns ns 4 4, 11 LOW Vcc DATA RETENTION WAVEFORM VCC t DATA RETENTION MODE 4.5V CDR VDR VDR > 2V 4.5V t R