SMJ27C256-15JM

UVEPROM Austin Semiconductor, Inc. 256K UVEPROM UV Erasable Programmable Read-Only Memory AVAILABLE AS MILITARY SPECIFICATIONS • SMD 5962-86063 • MIL-STD-883 SMJ27C256 PIN ASSIGNMENT (Top View) 32-Pin DIP (J) (600 MIL) VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vcc A14 A13 A8 A9 A11 G\ A10 E\ DQ7 DQ6 DQ5 DQ4 DQ3 FEATURES • Organized 32,768 x 8 • Single +5V ±10% power supply • Pin-compatible with existing 256K ROM’s and EPROM’s • All inputs/outputs fully TTL compatible • Power-saving CMOS technology • Very high-speed SNAP! Pulse Programming • 3-state output buffers • 400-mV DC assured noise immunity with standarad TTL loads • Latchup immunity of 250 mA on all input and output pins • Low power dissipation (CMOS Input Levels) PActive - 165mW Worst Case PStandby - 1.7mW Worst Case (CMOS-input levels) Pin Name A0 - A14 DA0-DQ7 E\ G\ GND VCC VPP Function Address Inputs Inputs (programming)/Outputs Chip Enable/Power Down Output Enable Ground 5V Supply 13V Programming Power Supply GENERAL DESCRIPTION The SMJ27C256 series is a set of 262,144 bit, ultravioletlight erasable, electrically programmable read-only memories. These devices are fabricated using power-saving CMOS technology for high speed and simple interface with MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 54 TTL circuits without the use of external pullup resistors. Each output can drive one Series 54 TTL circuit without external resistors. The data outputs are 3-state for connecting multiple devices to a common bus. The SMJ27C256 is pin-compatible with 28-pin 256K ROMs and EPROMs. It is offered in a 600mil dual-in-line ceramic pagackage (J suffix) rated for operation from -55°C to 125°C. Because this EPROM operates from a single 5V supply (in the read mode), it is ideal for use in microprocessor-based systems. One other supply (13V) is needed for programming. All programming signals are TTL level. This device is programmable by the SNAP! Pulse programming algorithm. The SNAP! Pulse programming algorithm uses a VPP of 13V and a VCC of 6.5V for a nominal programming time of four seconds. For programming outside the system, existing EPROM programmers can be used. Locations can be programmed singly, in blocks, or at random. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. OPTIONS • Timing 150ns access 170ns access 200ns access 250ns access 300ns access • Package(s) Ceramic DIP (600mils) MARKING -15 -17 -20 -25 -30 J No. 110 • Operating Temperature Ranges Military (-55oC to +125oC) M For more products and information please visit our web site at www.austinsemiconductor.com SMJ27C256 Rev. 1.0 9/01 1 UVEPROM Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM* EPROM 32,768 x 8 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 E\ G\ 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 20 22 0 SMJ27C256 A 0 32,767 A A A A A A A A 11 12 13 15 16 17 18 19 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 14 [PWR DWN] & EN * This symbol is in accordance with ANSI/IEEE std 91-1984 and IEC Publication 617-12. OPERATION The seven modes of operation for the SMJ27C256 are listed in Table 1. The read mode requires a single 5V supply. All inputs are TTL level except for VPP during programming (13V for SNAP! Pulse), and (12V) on A9 for signature mode. TABLE 1. OPERATION MODES FUNCTION (PINS) E\ (20) G\ (22) VPP (1) VCC (28) A9 (24) A0 (10) READ VIL VIL VCC VCC X X MODE* OUTPUT PROGRAM SIGNATURE MODE STANDBY PROGRAMMING VERIFY DISABLE INHIBIT VIL VIL VIH VIL VIH VIH VIH VCC VCC X X High-Z X VCC VCC X X High-Z VIH VPP VCC X X Data In VIL VPP VCC X X Data Out X VPP VCC X X High-Z VID VIL VIL VCC VCC VID VIH DQ0-DQ7 Data Out (11-13, 15-19) * X can be VIL or VIH. SMJ27C256 Rev. 1.0 9/01 CODE MFG DEVICE 97 04 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 UVEPROM Austin Semiconductor, Inc. READ/OUTPUT DISABLE When the outputs of two or more SMJ27C256s are connected in parallel on the same bus, the output of any particular device in the circuit can be read with no interference from the competing outputs of the other devices. To read the output of the selected SMJ27C256, a low-level signal is applied to E\ and G\. All other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these pins. Output data is accessed at pins DQ0 through DQ7. SMJ27C256 SNAP! PULSE PROGRAMMING The SMJ27C256 EPROM is programmed by using the SNAP! Pulse programming algorithm as illustrated by the flowchart in Figure 1. This algorithm programs the device in a nominal time of 4 seconds. Actual programming time varies as a function of the programmer used. Data is presented in parallel (eight bits) on pins DQ0 to DQ7. Once addresses and data are stable, E\ is pulsed. The SNAP! Pulse programming algorithm uses initial pulses of 100 microseconds (µs) followed by a byte-verification step to determine when the addressed byte has been successfully programmed. Up to ten 100µs pulses per byte are provided before a failure is recognized. The programming mode is achieved when V PP = 1 3V, VCC= 6.5V, G\ = VIH, and E\ = VIL. More than one device can be programmed when the devices are connected in parallel. Locations can be programmed in any order. When the SNAP! Pulse programming routine is completed, all bits are verified with VCC = VPP = 5V. LATCHUP IMMUNITY Latchup immunity on the SMJ27C256 is a minimum of 250mA on all inputs and outputs. This feature provides latchup immunity beyond any potential transients at the printed circuit board level when the EPROM is interfaced to industry standard TTL or MOS logic devices. Input/output layout approach controls latchup without compromising performance or packing density. POWER DOWN Active I CC s upply current can be reduced from 25mA (SMJ27C256-15 through SMJ27C256-25) to 500µA (TTLlevel inputs) or 300µA (CMOS-level inputs) by applying a high TTL/CMOS signal to the E\ pin. In this mode all outputs are in the high-impedance state. PROGRAM INHIBIT Programming can be inhibited by maintaining a high-level input on E\. ERASURE Before programming, the SMJ27C256 is erased by exposing the chip through the transparent lid to a high-intensity ultraviolet light (wavelength 2537 Å). EPROM erasure before programming is necessary to ensure that all bits are in the logic-high state. Logic-lows are programmed into the desired locations. A programmed logic-low can be erased only by ultraviolet light. The recommended minimum exposure dose (UV intensity x exposure time) is 15W•s/cm 2. A typical 12mW/cm 2 , filterless UV lamp erases the device in 21 minutes. The lamp should be located about 2.5cm above the chip during erasure. After erasure, all bits are in the high state. It should be noted that normal ambient light contains the correct wavelength for erasure; therefore, when using the SMJ27C256, the window should be covered with an opaque label. PROGRAM VERIFY Programmed bits can be verified with VPP = 13V when G\ = VIL, and E\ = VIH. SIGNATURE MODE The signature mode provides access to a binary code identifying the manufacturer and device type. This mode is activated when A9 is forced to 12V ±0.5V. Two identifier bytes are accessed by A0 (terminal 10); i.e., A0=VIL accesses the manufacturer code, which is output on DQ0-DQ7; A0=VIH accesses the device code, which is also output on DQ0-DQ7. All other addresses must be held at VIL. Each byte contains odd parity on bit DQ7. The manufacturer code for these devices is 97h and the device code is 04h. SMJ27C256 Rev. 1.0 9/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 UVEPROM Austin Semiconductor, Inc. SMJ27C256 FIGURE 1. SNAP! PULSE PROGRAMMING FLOW CHART START Address = First Location VCC = 6.5V, VPP = 13V Program One Pulse = tW = 100µs Increment Address Program Mode Last Address? No Yes Address = First Location X=0 Program One Pulse = tW(E)PR = 100µs No Verify Byte Increment Address Fail X = X+1 X = 10? Pass Last Address? Interactive Mode No Yes VCC = VPP = 5V ± 10% Yes Device Failed Compare All Bytes to Original Data Fail Final Verification Pass Device Passed SMJ27C256 Rev. 1.0 9/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 UVEPROM Austin Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS* Supply Voltage Range, VCC**...........................-0.6V to +7.0V Supply Voltage Range, Vpp**.........................-0.6V to +14.0V Input Voltage Range, All inputs except A9**..-0.6V to +6.5V A9.....-0.6V to +13.5V Output Voltage Range**...............................-0.6V to VCC +1V Minimum Operating Free-air Temperature, TA..............-55°C Maximum Operating Case Temperature, TC...................125°C Storage Temperature Range, Tstg.....................-65°C to 150°C SMJ27C256 *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ** All voltage values are with respect to GND. RECOMMENDED OPERATING CONDITIONS VCC VPP VIH VIL VID TA TC Supply Voltage Supply Voltage Read Mode SNAP! Pulse programming algorithm Read Mode SNAP! Pulse programming algorithm TTL inputs 2 1 MIN 4.5 6.25 12.75 2 TYP 5 6.5 13 High-level input voltage Low-level input voltage Voltage level on A9 for signature mode Operating free-air temperature Operating case temperature MAX 5.5 6.75 VCC-0.6 13.25 VCC+1 VCC+1 0.8 0.2 13 UNIT V V V V V V V V V °C CMOS inputs VCC-0.2 TTL inputs -0.5 CMOS inputs -0.5 11.5 -55 +125 °C NOTES: 1. VCC must be applied before or at the same time as VPP and removed after or at the same time as VPP. The deivce must not be inserted into or removed from the board when VPP or VCC is applied. 2. VPP can be connected to VCC directly (except in the program mode). VCC supply current in this case would be ICC2 + IPP1. ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE VOH VOL II IO IPP1 IPP2 ICC1 PARAMETER High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) VPP supply current VPP supply current (during program pulse) VCC supply current (standby) 2 TEST CONDITIONS IOH = -400µA IOL = 2.1mA VI = 0V to 5.5V VO = 0V to VCC VPP = VCC = 5.5V VPP = 13V VCC = 5.5V, E\=VIH MIN 2.4 TYP 1 MAX 0.4 ±1 ±1 10 UNIT V V µA µA µA mA µA µA 35 50 500 300 TTL-Input Level CMOS-Input Level VCC = 5.5V, E\=VCC '27C256-15 '27C256-17 '27C256-20 '27C256-25 E\=VIL, VCC=5.5V tcycle = minimum, outputs open 15 ICC2 VCC supply current (active) 25 mA Output current (leakage) IOS NOTES: 1. Typical values are at TA=25°C and nominal voltages. 2. This parameter has been characterized at 25°C and is not tested. SMJ27C256 Rev. 1.0 9/01 100 mA Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 UVEPROM Austin Semiconductor, Inc. SMJ27C256 CAPACITANCE OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, f = 1MHz* PARAMETER Ci Co Input capacitance Output capacitance TEST CONDITIONS VI = 0V VO = 0V TYP** 6 10 MAX 10 14 UNIT pF pF * Capacitance measurements are made on a sample basis only. ** Typical values are at TA = 25°C and nominal voltages. SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE1,2 PARAMETER ta(A) ta(E) Access time from address Access time from E\ see Figure 2 0 0 TEST CONDITIONS 1, 2 TEST CONDITIONS 1, 2 -15 150 150 70 55 0 0 -25 -17 170 170 70 55 MIN MAX MIN MAX UNIT ns ns ns ns ns ten(G)R Output enable time from G\ Disable time of output from G\ or E\, tdis 3 whichever occurs first Output data valid time after change of tv(A) 3 address, E\, or G\, whichever occurs first PARAMETER ta(A) ta(E) Access time from address Access time from E\ -20 200 200 75 -30 300 300 120 0 0 105 MIN MAX MIN MAX MIN MAX 250 250 100 0 0 60 UNIT ns ns ns ns ns ten(G)R Output enable time from G\ Disable time of output from G\ or E\, tdis 3 whichever occurs first Output data valid time after change of tv(A) 3 address, E\, or G\, whichever occurs first see Figure 2 0 0 60 NOTES: 1.Timing measurements are made at 2V for logic high and 0.8V for logic low (see figure 2). 2. Common test conditions apply for tdis except during programming. 3. Value calculated from 0.5V delta to measured output level. This parameter is only sampled and not 100% tested. SWITCHING CHARACTERISTICS FOR PROGRAMMING: VCC = 6.5V and VPP = 13V (SNAP! Pulse), TA = 25°C tdis(G) PARAMETER Output disable time from G\ MIN 0 MAX 130 150 UNIT ns ns ten(G)W Output enable time from G\ SMJ27C256 Rev. 1.0 9/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 UVEPROM Austin Semiconductor, Inc. SMJ27C256 RECOMMENDED TIMING REQUIREMENTS FOR PROGRAMMING: VCC = 6.5 and VPP = 13 (SNAP! Pulse), TA = 25°C (See Figure 2) MIN th(A) th(D) tw(E)PR tsu(A) tsu(G) tsu(E) tsu(D) Hold Time, Address Hold Time, Data Pulse Duration, Initial Program Setup Time, Address Setup Time, G\ Setup Time, E\ Setup Time, Data 0 2 95 2 2 2 2 2 2 100 105 TYP MAX UNIT µs µs µs µs µs µs µs µs µs tsu(VPP) Setup Time, VPP tsu(VCC) Setup Time, VCC PARAMETER MEASUREMENT INFORMATION 2.08V RL = 800Ω Output Under Test CL = 100 pF1 NOTES: 1. CL includes probe and fixture capacitance. The AC testing inputs are driven at 2.4V for logic high and 0.4V for logic low. Timing measurements are made at 2V for logic high and 0.8V for logic low for both inputs and outputs. FIGURE 2. LOAD CIRCUIT AND VOLTAGE WAVEFORMS SMJ27C256 Rev. 1.0 9/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 UVEPROM Austin Semiconductor, Inc. FIGURE 3. READ-CYCLE TIMING SMJ27C256 FIGURE 4. PROGRAM-CYCLE TIMING (SNAP! PULSE PROGRAMMING) SMJ27C256 Rev. 1.0 9/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 UVEPROM Austin Semiconductor, Inc. MECHANICAL DEFINITION* SMJ27C256 ASI Case #110 (Package Designator CW) SMD 5962-86063, Case Outline X D S2 Q A L E S1 b2 e b eA c SMD SPECIFICATIONS MIN MAX SYMBOL A --0.232 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 D --1.490 E 0.500 0.610 eA 0.600 BSC e 0.100 BSC L 0.125 0.200 Q 0.015 0.060 S1 0.005 --S2 0.005 --NOTE: These dimensions are per the SMD. ASI's package dimensional limits may differ, but they will be within the SMD limits. *All measurements are in inches. SMJ27C256 Rev. 1.0 9/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 UVEPROM Austin Semiconductor, Inc. SMJ27C256 ORDERING INFORMATION EXAMPLE: SMJ27C256-30JM Device Number SMJ27C256 SMJ27C256 SMJ27C256 SMJ27C256 SMJ27C256 Speed ns -15 -17 -20 -25 -30 Package Operating Type Temp. J J J J J * * * * * *AVAILABLE PROCESSES M = Extended Temperature Range -55oC to +125oC SMJ27C256 Rev. 1.0 9/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 10 UVEPROM Austin Semiconductor, Inc. SMJ27C256 ASI TO DSCC PART NUMBER CROSS REFERENCE* ASI Package Designator J TI Part #** SMJ27C256-15JM SMJ27C256-17JM SMJ27C256-20JM SMJ27C256-25JM SMJ27C256-30JM SMD Part # 5962-8606305XA 5962-8606304XA 5962-8606301XA 5962-8606302XA 5962-8606303XA * ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD. ** Parts are listed on SMD under the old Texas Instruments part number. ASI purchased this product line in November of 1999. SMJ27C256 Rev. 1.0 9/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 11