SMJ27C512

UVEPROM Austin Semiconductor, Inc. 512K UVEPROM UV Erasable Programmable Read-Only Memory AVAILABLE AS MILITARY SPECIFICATIONS • SMD 5962-87648 • MIL-STD-883 SMJ27C512 PIN ASSIGNMENT (Top View) 28-Pin DIP (J) 600-Mils A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vcc A14 A13 A8 A9 A11 G\/VPP A10 E\ DQ7 DQ6 DQ5 DQ4 DQ3 FEATURES • Organized 65,536 x 8 • High-reliability MIL-PRF-38535 processing • Single +5V ±10% power supply • Pin-compatible with existing 512K read-only memories (ROMs) and electrically programmable ROMs (EPROMs) • All inputs/outputs fully TTL compatible • Power-saving CMOS technology • Very high-speed SNAP! Pulse Programming • 3-state output buffers • 400mV minimum DC noise immunity with standard TTL loads • Latchup immunity of 250mA on all input and output lines • Low power dissipation (CMOS input levels) PActive - 193mW (MAX) PStandby - 1.7mW (MAX) Pin Name A0 - A15 DA0-DQ7 E\ GND G\ /VPP VCC Function Address Inputs Inputs (programming)/Outputs Chip Enable/Power Down Ground Output Enable/13V Programming 5V Power Supply OPTIONS • Timing 150ns access 200ns access 250ns access • Package(s) Ceramic DIP (600mils) MARKING -15 -20 -25 GENERAL DESCRIPTION The SMJ27C512 is a set of 65536 by 8-bit (524,288-bit), ultraviolet (UV) light erasable, electrically programmable read-only memories. These devices are fabricated using power-saving CMOS technology for high speed and simple interface with MOS and bipolar circuits. All inputs (including program data inputs can be driven by Series 54 TTL circuits without the use of external pullup resistors. Each output can drive one Series 54 TTL circuit without external resistors. The data outputs are 3-state for connecting multiple devices to a common bus. The SMJ27C512 is pin-compatible with existing 28-pin 512K ROMs and EPROMs. Because this EPROM operates from a single 5V supply (in the read mode), it is ideal for use in microprocessor-based systems. One other supply (13V) is needed for programming. All programming signals are TTL level. This device is programmable by the SNAP! Pulse programming algorithm. The SNAP! Pulse programming algorithm uses a VPP of 13V and a VCC of 6.5V for a nominal programming time of seven seconds. For programming outside the system, existing EPROM programmers can be used. Locations may be programmed singly, in blocks, or at random. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. J No. 110 • Operating Temperature Ranges Military (-55oC to +125oC) M For more products and information please visit our web site at www.austinsemiconductor.com SMJ27512 Rev. 1.0 9/01 1 UVEPROM Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM* EPROM 65,536 x 8 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 E\ G\ /VPP 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 1 20 22 0 SMJ27C512 A 0 65,535 A A A A A A A A 11 12 13 15 16 17 18 19 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 15 [PWR DWN] & EN * This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. OPERATION The seven modes of operation for the SMJ27C512 are listed in Table 1. The read mode requires a single 5V supply. All inputs are TTL level except for VPP during programming (13V for SNAP! Pulse), and 12V on A9 for signature mode. TABLE 1. OPERATION MODES FUNCTION (PINS) E\ (20) G\ /VPP (22) VCC (28) A9 (24) A0 (10) READ VIL VIL VCC X X MODE* OUTPUT PROGRAM SIGNATURE MODE STANDBY PROGRAMMING VERIFY DISABLE INHIBIT VIL VIL VIH VIL VIL VIH VIH VCC X X High-Z X VCC X X High-Z VPP VCC X X Data In VIL VCC X X Data Out VPP VCC X X High-Z VID VIL VIL VCC VID VIH CODE MFG DEVICE 97h 85h DQ0-DQ7 Data Out (11-13, 15-19) * X can be VIL or VIH SMJ27512 Rev. 1.0 9/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 UVEPROM Austin Semiconductor, Inc. READ/OUTPUT DISABLE When the outputs of two or more SMJ27C512 are connected in parallel on the same bus, the output of any particular device in the circuit can be read with no interference from competing outputs of the other devices. To read the output of the selected SMJ27C512, a low-level signal is applied to the E\ and G\ /VPP. All other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these pins. Output data is accessed at pins DQ0 through DQ7. SMJ27C512 SNAP! PULSE PROGRAMMING The SMJ27C512 is programmed using the SNAP! Pulse programming algorithm as illustrated by the flowchart in Figure 1. This algorithm programs in a nominal time of seven seconds. Actual programming time varies as a function of the programmer used. Data is presented in parallel (eight bits) on pins DQ0 to DQ7. Once addresses and data are stable, E\ is pulsed. The SNAP! Pulse programming algorithm uses an initial pulse of 100µs followed by a byte verification to determine when the addressed byte has been successfully programmed. Up to ten 100µs pulses per byte are provided before a failure is recognized. The programming mode is achieved when G\ /VPP = 13V, VCC= 6.5V, and E\ = VIL. More than one device can be programmed when the devices are connected in parallel. Locations can be programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified with VCC = 5V, G\ /VPP = VIL, and E\ = VIL. LATCHUP IMMUNITY Latchup immunity on the SMJ27C512 is a minimum of 250mA on all inputs and outputs. This feature provides latchup immunity beyond any potential transients at the printed circuit board level when the EPROM is interfaced to industry-standard TTL or MOS logic devices. Input/output layout approach controls latchup without compromising performance or packing density. POWER DOWN Active ICC supply current can be reduced from 35mA to 500µA(TTL-level inputs) or 300µA (CMOS-level inputs) by applying a high TTL/CMOS signal to the E\ pin. In this mode all outputs are in the high-impedance state. PROGRAM INHIBIT Programming can be inhibited by maintaining high level input on E\. ERASURE Before programming, the SMJ27512 is erased by exposing the chip through the transparent lid to a high-intensity ultraviolet (UV) light (wavelength 2537 Å). EPROM erasure before programming is necessary to assure that all bits are in the logic-high state. Logic lows are programmed into the desired locations. A programmed logic low can be erased only by ultraviolet light. The recommended minimum exposure dose (UV intensity x exposure time) is 15 W.s/cm2. A typical 12mW/cm2, filterless UV lamp erases the device in 21 minutes. The lamp should be located about 2.5cm above the chip during erasure. After erasure, all bits are in the high state. It should be noted that normal ambient light contains the correct wavelength for erasure; therefore, when using the SMJ27C512, the window should be covered with an opaque label. PROGRAM VERIFY Programmed bits can be verified with G\ /VPP and E\ = VIL. SIGNATURE MODE The signature mode provides access to a binary code identifying the manufacturer and device type. This mode is activated when A9 (terminal 24) is forced to 12V ±0.5V. Two identifier bytes are accessed by A0 (terminal 10); i.e., A0 = VIL accesses the manufacturer code, which is output on DQ0-DQ7; A0 = VIH accesses the device code, which is also output on DQ0-DQ7. All other addresses must be held at VIL. Each byte possesses odd parity on bit DQ7. The manufacturer code for these devices is 97h and the device code is 85h. SMJ27512 Rev. 1.0 9/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 UVEPROM Austin Semiconductor, Inc. SMJ27C512 FIGURE 1. SNAP! PULSE PROGRAMMING FLOW CHART START Address = First Location VCC = 6.5V ± 0.25V, G\ /VPP = 13V ± 0.25V Program One Pulse = tW = 100µs Increment Address Program Mode Last Address? No Yes Address = First Location X=0 Program One Pulse = tW = 100µs No Verify Word Increment Address Fail X = X+1 X = 10? Pass Last Address? Interactive Mode No Yes VCC = 5V ± 0.5V, G\ /VPP = VIL Yes Device Failed Compare All Bytes to Original Data Fail Final Verification Pass Device Passed SMJ27512 Rev. 1.0 9/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 UVEPROM Austin Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS* Supply Voltage Range, VCC**...........................-0.6V to +7.0V Supply Voltage Range, Vpp**.........................-0.6V to +14.0V Input Voltage Range, All inputs except A9**....-0.6V to 6.5V A9....-0.6V to +13.5V Output Voltage Range**...............................-0.6V to VCC +1V Operating Cage Temperature Range, TC.........-55°C to 125°C Storage Temperature Range, Tstg.....................-65°C to 150°C SMJ27C512 *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ** All voltage values are with respect to GND. RECOMMENDED OPERATING CONDITIONS VCC Supply Voltage 1 G\ /VPP Supply Voltage2 Voltage level on A9 for signature mode VID VIH VIL TC High-level DC input voltage Low-level DC input voltage Operating case temperature Read Mode SNAP! Pulse programming algorithm SNAP! Pulse programming algorithm MIN 4.5 6.25 12.75 11.5 NOM 5 6.5 13 MAX 5.5 6.75 13.25 12.5 VCC+1 VCC+1 0.8 0.2 125 UNIT V V V V V V V V °C TTL CMOS TTL CMOS 2 VCC-0.2 -0.5 -0.5 -55 NOTES: 1. VCC must be applied before or at the same time as G\ /VPP and removed after or at the same time as G\ /VPP. The deivce must not be inserted into or removed from the board when G\ /VPP or VCC is applied. 2. G\ /VPP can be connected to VCC directly (except in the program mode). VCC supply current in this case is ICC + IPP. ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF OPERATING CONDITIONS VOH VOL II IO IPP ICC1 PARAMETER High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) G\ /VPP supply current (during program pulse) VCC supply current (standby) 2 TEST CONDITIONS IOH = -400µA IOL = 2.1mA VI = 0V to 5.5V VO = 0V to VCC G\ /VPP = 13V VCC = 5.5V, E\=VIH E\=VIL, VCC=5.5V MIN 2.4 TYP 1 MAX 0.4 10 10 35 70 500 325 TTL-Input Level CMOS-Input Level VCC = 5.5V, E\=VCC tcycle = minimum cycle time, outputs open 35 ICC2 VCC supply current (active) 50 NOTES: 1. Typical values are at TC=25°C and nominal voltages. 2. This parameter has been characterized at 25°C and is not production tested. SMJ27512 Rev. 1.0 9/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 UVEPROM Austin Semiconductor, Inc. PARAMETER CI CO Input capacitance Output capacitance TEST CONDITIONS VI = 0V VO = 0V G\ /VPP = 0V TYP** 6 10 20 UNIT pF pF pF SMJ27C512 CAPACITANCE OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING CASE TEMPERATURE, f = 1MHz* CG/VPP G\ /VPP input capacitance * Capacitance measurements are made on sample basis only. ** All typical values are at TC = 25°C and nominal voltages. SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING CASE TEMPERATURE PARAMETER ta(A) ta(E) ten(G) tdis tv(A) Access time from address Access time from E\ Output enable time from G\ /VPP Output disable time from G\ /VPP or E\, whichever occurs first Output data valid time after change of address, E\, or G\, whichever occurs first 3 3 TEST CONDITIONS 1,2 -15 -20 -25 MIN MAX MIN MAX MIN MAX 150 150 70 200 200 75 0 0 60 0 0 250 250 100 60 UNIT ns ns ns ns ns See Figure 2 0 0 50 NOTES: 1. Timing measurements are made at 2V for logic high and 0.8V for logic low. (see Figure 2) 2. Common test conditions apply for tdis except during programming. 3. Value calculated from 0.5V delta to measured output level. This parameter is only sampled and not 100% tested. RECOMMENDED TIMING REQUIREMENTS FOR PROGRAMMING: V CC = 6 .5V and G\ /V PP = 1 3V (SNAP! Pulse), T C = 2 5°C (see Figure 2) MIN tdis(E) th(A) th(D) th(VPP) trec(PG) tsu(A) tsu(D) tsu(Vpp) tsu(Vcc) tv(ELD) tr(PG) SMJ27512 Rev. 1.0 9/01 NOM MAX 130 UNIT ns µs µs µs Output disable time from E\ Hold Time, address Hold time, address Hold time, G\ /VPP Recovery time, G\ /VPP Setup Time, Address Setup Time, Data Setup Time, G\ /VPP Setup Time, VCC Data valid from E\ low G\ /VPP rise time 0 0 2 2 95 2 2 2 2 2 100 tw(IPGM) Pulse duration, initial program 105 µs µs µs µs µs µs 1 50 µs ns Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 UVEPROM Austin Semiconductor, Inc. PARAMETER MEASUREMENT INFORMATION 2.08V RL = 800Ω Output Under Test CL = 100 pF1 NOTES: 1. CL includes probe and fixture capacitance. SMJ27C512 FIGURE 2. LOAD CIRCUIT AND VOLTAGE WAVEFORM AC testing inputs are driven at 2.4V for logic high and 0.4V for logic low. Timing measurements are made at 2V for logic high and 0.8V for logic low for both inputs and outputs. FIGURE 3. READ-CYCLE TIMING SMJ27512 Rev. 1.0 9/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 UVEPROM Austin Semiconductor, Inc. SMJ27C512 FIGURE 4. PROGRAM-CYCLE TIMING (SNAP! PULSE PROGRAMMING) NOTES: 1. G\ /VPP = 13V and VCC = 6.5V for SNAP! Pulse programming. SMJ27512 Rev. 1.0 9/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 UVEPROM Austin Semiconductor, Inc. MECHANICAL DEFINITION* ASI Case #110 (Package Designator J) SMD 5962-87648, Case Outline X SMJ27C512 D S2 Q A L E S1 Pin 1 b2 e b eA c SYMBOL A b b2 c D E eA e L Q S1 S2 SMD SPECIFICATIONS MIN MAX --0.232 0.014 0.026 0.045 0.065 0.008 0.018 --1.490 0.500 0.610 0.600 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 --0.005 --- NOTE: These dimensions are per the SMD. ASI's package dimensional limits may differ, but they will be within the SMD limits. *All measurements are in inches. SMJ27512 Rev. 1.0 9/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 UVEPROM Austin Semiconductor, Inc. SMJ27C512 ORDERING INFORMATION EXAMPLE: SMJ27C512-25JM Device Number SMJ27C512 SMJ27C512 SMJ27C512 Speed Package Operating ns Type Temp. -15 -20 -25 J J J * * * *AVAILABLE PROCESSES M = Extended Temperature Range -55oC to +125oC SMJ27512 Rev. 1.0 9/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 10 UVEPROM Austin Semiconductor, Inc. SMJ27C512 ASI TO DSCC PART NUMBER CROSS REFERENCE* ASI Package Designator J TI Part #** SMJ27C512-15JM SMJ27C512-20JM SMJ27C512-25JM SMD Part # 5962-8764801XA 5962-8764802XA 5962-8764803XA * ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD. ** Parts are listed on SMD under the old Texas Instruments part number. ASI purchased this product line in November of 1999. SMJ27512 Rev. 1.0 9/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 11