ACML-7400, ACML-7410 and ACML-7420
3.3 V/5 V 100 MBd High Speed CMOS Digital Isolator
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
ACML-7400, ACML-7410 and ACML-7420 are multi-channel
high speed CMOS digital isolators. Using magnetic
coupling through a thick insulation barrier, the isolators
enable high speed transmissions without compromise
in isolation performance. These isolators consume low
power even at high data rates, yet provide excellent
transient immunity performance in compact surface
mount packages. The devices are qualified to a maximum
propagation delay of 36 ns and a maximum pulse width
distortion of 3 ns. They are capable of running at a 100
MBaud data rate
Dual supply voltage compatible – 3.3 V & 5 V
ACML-7400, ACML-7410 and ACML-7420 are available in
16-pin SOIC wide-body packages. They operate at dual
3.3 V/5 V supply voltages. The DC and timing specifications are specified over the temperature range of -40° C
to +105° C. ACML-7400, ACML-7410 and ACML-7420 are
built using CMOS input buffers and CMOS output drivers
to eliminate the need for both input limiters and output
pull-up resistors. Refresh circuitry is built in to ensure
DC-correctness.
Safety and Regulatory Approvals
Applications
Isolated data interfaces
Data acquisition
Digital oscilloscopes
Power meters
High speed video transmission
Wide operating temperature range (-40° C to +105° C)
Support high speed data rate of at least 100 MBd
Lower power consumption – 15 mA per channel typical
Low propagation delay: 36 ns max
Low propagation delay skew
– Channel-to-channel: 4 ns max
– Part-to-part: 8 ns max
Low pulse width distortion: 3 ns max
UL Recognised
– 5600 VRMS for 1 min. per UL1577
– CSA Component Acceptance Notice #5
IEC 60950-1
– Basic Insulation, 800 VRMS max. working voltage
– Reinforced Insulation, 400 VRMS max. working
voltage
IEC 61010-1
– Basic Insulation, 800 VRMS max. working voltage
– Reinforced Insulation, 400 VRMS max. working voltage
IEC 60601-1
– 2 Means of Patient Protection, 250 VRMS max.
working voltage
– 2 Means of Operator Protectioin, 400 VRMS max.
working voltage
High Common Mode Transient Immunity – 25 kV/s min
CMOS buffer input and output
DC correctness
Lead-free
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Device Selection Guide
Device Number
Channel Configuration
Package
ACML-7400
Quad, All-in-One
16-pin Small Outline, Wide Body
ACML-7410
Quad, Bi-directional, 3/1
16-pin Small Outline, Wide Body
ACML-7420
Quad, Bi-directional, 2/2
16-pin Small Outline, Wide Body
Ordering Information
ACML-7400, ACML-7410 and ACML-7420 are UL Recognized with 5600 VRMS for 1 minute per UL1577.
Option
Part number
RoHS Compliant
Package
Surface Mount
ACML-7400
ACML-7410
ACML-7420
-000E
Wide Body SO-16
X
-500E
X
Tape & Reel
X
UL 5600 VRMS /
1 Minute rating
Quantity
X
45 per tube
X
850 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACML-7420-500E to order product of Wide Body SO-16 package in Tape and Reel in RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
2
Functional Diagram
Quad Channel
ACML-7410
ACML-7400
ACML-7420
VDD2
VDD1
11
16
VDD2
VDD1
1
16
VDD2
GND1
22
15
15
GND2
GND1
22
15
GND2
GND1
2
15
GND2
VIN1
33
14
14
VO1
VIN1
33
14
VO1
VIN1
3
14
VO1
VIN2
44
13
13
VO2
VIN2
44
13
VO2
VIN2
4
13
VO2
VIN3
55
12
12
VO3
VIN3
55
12
VO3
VO3
5
12
VIN3
VIN4
66
11
11
VO4
VO4
66
11
VIN4
VO4
6
11
VIN4
NC
77
10
10
VOE2
VOE1
77
10
VOE2
VOE1
7
10
VOE2
GND1
88
99
GND2
GND1
88
9
GND2
GND1
8
9
GND2
Galvanic Isolation
16
16
Galvanic Isolation
Galvanic
Isolation
11
Galvanic Isolation
Galvanic
Isolation
VDD1
Pin Description
Pin
Description
VDD1, VDD2
Power supply at primary and secondary side
GND1, GND2
Ground at primary and secondary side
VIN1, VIN2, VIN3, VIN4
Input for channel 1, 2, 3 and 4
VO1, VO2, VO3, VO4
Output for channel 1, 2, 3 and 4
VOE1, VOE2
Output enable at VDD1 and VDD2 side, these pins should be connected to the respective VDD when
not in use.
No connectivity
NC
Truth Table (ACML-7410)
VDD1
VIN1,IN2,IN3
VOE1
VO4
VDD2
VIN4
VOE2
VO1, O2, O3
Remark
H
H
X
X
H
X
H
H
L
X
X
H
X
H
X
X
X
H
X
H or
NC
H or
NC
L
Z
L
X
X
X
H
X
H
H
H
X
H
H
H
X
X
H
X
L
H
L
X
X
H
X
H or
NC
H or
NC
L
Z
H
X
X
X
H
X
H
H
L
X
X
X
Input (VIN1, IN2, IN3) logic High during normal operation.
The default state for VOE2 is High state.
Input (VIN1, IN2, IN3) logic Low during normal operation.
The default state for VOE2 is High state.
Output (VO1, O2, O3) is disabled to high impedance state
when VOE2 is set to Low.
When VDD1 is not powered, the output (VO1, O2, O3)
default state is High. Output (VO1, O2, O3) typically
restored 100 s after VDD1 is restored.
Input (VIN4) logic High during normal operation.
The default state for VOE1 is High state.
Input (VIN4) logic Low during normal operation.
The default state for VOE1 is High state.
Output (VO4) is disabled to high impedance state when
VOE1 is set to Low.
When VDD2 is not powered, the output (VO4) default
state is High. Output (VO4) typically restored 100 s
after VDD2 is restored.
X means don’t care
NC means not connection.
3
L
Package Outline Drawings
ACML-7400, ACML-7410 and ACML-7420 16-Lead Surface Mount (SOIC-16) Package
0.457
(0.018)
LAND PATTERN RECOMMENDATION
0.64 (0.025)
1.270
(0.050)
16 15 14 13 12 11 10 9
TYPE NUMBER
DATE CODE
A 7400
YYWW
7.493 ± 0.254
(0.295 ± 0.010)
11.63 (0.458)
2.16 (0.085)
1 2 3 4 5 6 7 8
10.312 ± 0.254
(0.406 ± 0.10)
3.505 ± 0.127
(0.138 ± 0.005)
0.457
(0.018)
ALL LEADS
TO BE
COPLANAR
± 0.002
8.986 ± 0.254
(0.345 ± 0.010)
9°
0-8°
0.025 MIN.
10.160 ± 0.254
(0.408 ± 0.010)
0.203 ± 0.076
(0.008 ± 0.003)
STANDOFF
DIMENSIONS IN MILLIMETERS AND (INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
Recommended Pb-Free IR Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
Regulatory Information
The ACML-7400, ACML-7410 and ACML-7420 are approved by the following organizations:
UL
UL1577, component recognition program.
CSA Component Acceptance Service Notice #5A.
TUV Rheinland
IEC 60950-1
Insulation
Category
Working Voltage
4
IEC 61010-1
IEC 60601-1
Reinforced
Basic
Reinforced
Basic
2 Means of
Patient Protection
2 Means of
Operator Protection
400 VRMS
(567 VPEAK)
800 VRMS
(1132 VPEAK)
400 VRMS
(567 VPEAK)
800 VRMS
(1132 VPEAK)
250 VRMS
(354 VPEAK)
400 VRMS
(567 VPEAK)
Insulation and Safety Related Specifications
Parameter
Symbol
ACML-7400
ACML-7410
ACML-7420
Minimum External Air Gap
(Clearance)
L(101)
8.1
mm
Measured from input terminals to output terminals,
shortest distance through air.
Minimum External Tracking
(Creepage)
L(102)
8.1
mm
Measured from input terminals to output terminals,
shortest distance path along body.
0.05
mm
Through insulation distance conductor to conductor,
usually the straight line distance thickness between the
emitter and detector.
>175
V
DIN IEC 112/VDE 0303 Part 1
Minimum Internal Plastic Gap
(Internal Clearance)
Tracking Resistance
(Comparative Tracking Index)
CTI
Isolation Group
Units
Conditions
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
All creepage and clearance pertain to the isolation component itself. These dimensions are needed as a starting point
for the designer when determining the circuit insulation requirements, and not reflective of the equipment standard
requirements.
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
-55
+125
°C
Ambient Operating Temperature
TA
-40
+125
°C
Supply Voltages
VDD1, VDD2
0
6.5
Volts
Input Voltage
VI
-0.5
VDD +0.5
Volts
Output Voltage
VO
-0.5
VDD +0.5
Volts
IO
±15
mA
Human Body Model
HBM
±4
kV
Charge Device Model
CDM
±1
kV
Average Output Current
Electrostatic Discharge
Solder Reflow Temperature Profile
Please refer to Solder Reflow Temperature Profile
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Ambient Operating Temperature
TA
-40
+105
°C
Supply Voltages ( 3.3 V operation)
VDD1, VDD2
3.0
3.6
V
Supply Voltages ( 5 V operation)
VDD1, VDD2
4.5
5.5
V
Logic High Input Voltage
VIH
0.7 x VDD
VDD
V
Logic Low Input Voltage
VIL
0.0
0.3 x VDD
V
5
Notes
Electrical Specifications
The following specifications apply to ACML-7400 and are applicable to ambient temperature of -40° C ≤ TA ≤ 105° C,
input supply of 3.0 V ≤ VDD1 ≤ 3.6 V or 4.5 V ≤ VDD1 ≤ 5.5 V, and output supply of 3.0 V ≤ VDD2 ≤ 3.6 V or 4.5 V ≤ VDD2 ≤ 5.5 V.
All typical specifications at TA = +25° C.
Parameter
Symbol
Input Supply Current,
No data
Min.
Typ.
Max.
Unit
IDD1(0)
5.9*
10
mA
Input Supply Current,
25 MBd data rate
IDD1(25)
16
Input Supply Current,
100 MBd data rate
IDD1(100)
Output Supply Current,
No data
Test Conditions
Fig.
Notes
No Input
1,7
1
12.5 MHz logic
signal
1,7
2
50 MHz logic
signal
1,7
2
No Input
2,8
3
12.5 MHz logic
signal
2,8
4
50 MHz logic
signal
2,8
4
VDD1 = 5.5 V
6.8**
mA
VDD1 = 3.3 V
VDD1 = 5.0 V
17
30*
40
31**
40
IDD2(0)
12*
16
Output Supply Current,
25 MBd
IDD2(25)
15
Output Supply Current,
100 MBd data rate
IDD2(100)
Logic Input Current
IIN
-10
Logic High Output
Voltage
VOH
VDD-0.1
VDD-0.02
0.8*VDD
VDD-0.25
Logic Low Output
Voltage
VOL
mA
VDD1 = 3.6 V
VDD1 = 5.5 V
mA
VDD1 = 5.5 V
13**
mA
VDD1 = 3.3 V
VDD1 = 5.0 V
17
23*
32
30**
40
10
mA
VDD1 = 3.6 V
VDD1 = 5.5 V
A
V
IOUT = -20 A, VIN = VDD1
V
IOUT = -4 mA, VIN = VDD1
0.02
0.1
V
IOUT = 20 A, VIN = 0 V
0.25
0.8
V
IOUT = 4 mA, VIN = 0 V
* Typical data based on 3.3 V supply, ** Typical data based on 5.0 V supply
The following specifications apply to ACML-7410 and are applicable to ambient temperature of -40° C ≤ TA ≤ 105° C,
input supply of 3.0 V ≤ VDD1 ≤ 3.6 V or 4.5 V ≤ VDD1 ≤ 5.5 V, and output supply of 3.0 V ≤ VDD2 ≤ 3.6 V or 4.5 V ≤ VDD2 ≤ 5.5 V.
All typical specifications at TA = +25° C.
Parameter
Symbol
Input Supply Current,
No data
Min.
Typ.
Max.
Unit
IDD1(0)
8.4*
11.5
mA
Input Supply Current,
25 MBd data rate
IDD1(25)
15.5*
Input Supply Current,
100 MBd data rate
IDD1(100)
Output Supply Current,
No data
Fig.
Notes
No Input
3,7
1
12.5 MHz logic
signal
3,7
2
50 MHz logic
signal
3,7
2
No Input
4,8
3
12.5 MHz logic
signal
4,8
4
50 MHz logic
signal
4,8
4
VDD1 = 5.5 V
9.4**
mA
VDD1 = 3.3 V
VDD1 = 5.0 V
17**
28.5*
38
30.5**
40
IDD2(0)
9.5*
14.5
Output Supply Current,
25 MBd
IDD2(25)
15*
Output Supply Current,
100 MBd data rate
IDD2(100)
Logic Input Current
IIN
-10
Logic High Output
Voltage
VOH
VDD-0.1
VDD-0.02
0.8*VDD
VDD-0.25
Logic Low Output
Voltage
VOL
mA
VDD1 = 3.6 V
VDD1 = 5.5 V
mA
VDD1 = 5.5 V
10.4**
mA
VDD1 = 3.3 V
VDD1 = 5.0 V
17**
25*
34
30**
40
10
mA
VDD1 = 3.6 V
VDD1 = 5.5 V
A
V
IOUT = -20 A, VIN = VDD1
V
IOUT = -4 mA, VIN = VDD1
0.02
0.1
V
IOUT = 20 A, VIN = 0 V
0.25
0.8
V
IOUT = 4 mA, VIN = 0 V
* Typical data based on 3.3 V supply, ** Typical data based on 5.0 V supply
6
Test Conditions
The following specifications apply to ACML-7420 and are applicable to ambient temperature of -40° C ≤ TA ≤ 105° C,
input supply of 3.0 V ≤ VDD1 ≤ 3.6 V or 4.5 V ≤ VDD1 ≤ 5.5 V, and output supply of 3.0 V ≤ VDD2 ≤ 3.6 V or 4.5 V ≤ VDD2 ≤ 5.5 V.
All typical specifications at TA = +25° C.
Parameter
Symbol
Input Supply Current,
No data
Min.
Typ.
Max.
Unit
IDD1(0)
9.0*
13
mA
Input Supply Current,
25 MBd data rate
IDD1(25)
15*
Input Supply Current,
100 MBd data rate
IDD1(100)
Output Supply Current,
No data
mA
27*
36
30**
40
IDD2(0)
9.0*
13
Output Supply Current,
25 MBd
IDD2(25)
15*
Output Supply Current,
100 MBd data rate
IDD2(100)
Logic Input Current
IIN
-10
Logic High Output
Voltage
VOH
VDD-0.1
VDD-0.02
0.8*VDD
VDD-0.25
Logic Low Output
Voltage
VOL
mA
VDD1 = 3.6 V
VDD1 = 5.5 V
mA
Notes
No Input
5,7
1
12.5 MHz logic
signal
5,7
2
50 MHz logic
signal
5,7
2
No Input
6,8
3
12.5 MHz logic
signal
6,8
4
50 MHz logic
signal
6,8
4
VDD1 = 5.5 V
9.9**
mA
VDD1 = 3.3 V
VDD1 = 5.0 V
17**
36
mA
VDD1 = 3.6 V
VDD1 = 5.5 V
40
10
A
V
IOUT = -20 A, VIN = VDD1
V
IOUT = -4 mA, VIN = VDD1
0.02
0.1
V
IOUT = 20 A, VIN = 0 V
0.25
0.8
V
IOUT = 4 mA, VIN = 0 V
* Typical data based on 3.3 V supply, ** Typical data based on 5.0 V supply
7
VDD1 = 3.3 V
VDD1 = 5.0 V
17**
30**
Fig.
VDD1 = 5.5 V
9.9**
27*
Test Conditions
Switching Specifications
The following specifications apply to ACML-7400, ACML-7410 and ACML-7420 and are applicable to ambient temperature of -40° C ≤ TA ≤ 105° C, input supply of 3.0 V ≤ VDD1 ≤ 3.6 V or 4.5 V ≤ VDD1 ≤ 5.5 V, and output supply of 3.0 V ≤ VDD2
≤ 3.6 V or 4.5 V ≤ VDD2 ≤ 5.5 V, unless further specified. All typical specifications are at TA = +25° C.
Parameter
Symbol
Maximum Data Rate
Min.
Typ.
Max.
100
Minimum Pulse Width
Unit
Test Conditions
MBd
50 MHz Logic Signal
Fig.
Notes
10
ns
50 MHz Logic Signal
Propogation Delay Time
to Logic Low Output
tPHL
18
27
32
ns
4.5 V ≤ VDD1 = VDD2 ≤ 5.5 V, 9
CL = 15 pF
5
Propogation Delay Time
to Logic High Output
tPLH
18
27
32
ns
9
5
Pulse Width Distortion
PWD
-2
0
2
ns
11
6
Propagation Delay
Channel Skew
tCSK
0
3
ns
12
7
Propagation Delay
Part Skew
tPSK
1
5
ns
Propogation Delay Time
to Logic Low Output
tPHL
20
28
36
ns
Propogation Delay Time
to Logic High Output
tPLH
20
27.5
36
Pulse Width Distortion
PWD
-3
0.5
Propagation Delay
Channel Skew
tCSK
Propagation Delay
Part Skew
tPSK
8
CL = 15 pF
9,10
5
ns
9,10
5
3
ns
11
6
0
4
ns
12
7
1
8
ns
8
Output Rise Time (10% – 90%) tR
3
ns
CL = 15 pF
Output Fall Time (90% - 10%)
tF
3
ns
CL = 15 pF
Output Enable time
tENABLE
10
ns
VIN = 0 V or VDD
9
Output Disable time
tDISABLE
10
ns
VIN = 0 V or VDD
10
Common Mode Transient
Immunity at Logic
High Output
| CMH |
25
>40
kV/s VCM = 1000 V, TA = 25° C,
VIN = VDD VO > 0.8 x VDD
11
Common Mode Transient
Immunity at Logic
Low Output
| CML |
25
>40
kV/s VCM = 1000 V, TA = 25° C,
VIN = 0 V, VO < 0.8 V
11
8
Package Characteristics
All Typicals at TA = 25° C.
Parameters
Symbol
Min.
Input-Output Momentary
With-stand Voltage
VISO
5600
Input-Output Resistance
RI-O
Input-Output Capacitance
Typ.
Max.
Unit
Test Conditions
Notes
VRMS
RH ≤ 50%, t = 1 min,
TA = 25°C
12, 13,
14
1014
VI-O = 500 V dc
12
CI-O
1.9
pF
f = 1 MHz
12
Input Capacitance
CI
4.3
pF
Package Power Dissipation
PPD
750
mW
15
TA = 25° C
Notes:
1. IDD1(0) is the supply current consumption at VDD1 of ACML-7400, ACML-7410 and ACML-7420 when there is no signal to all inputs.
2. IDD1(F) is the supply current consumption at VDD1 of ACML-7400, ACML-7410 and ACML-7420 when inputs are switching at the specified data rate,
and outputs are switching at same data rate with no load.
3. IDD2(0) is the supply current consumption at VDD2 of ACML-7400, ACML-7410 and ACML-7420 when there is no signal to all inputs.
4. IDD2(F) is the supply current consumption at VDD2 of ACML-7400, ACML-7410 and ACML-7420 when inputs are switching at the specified data rate,
and outputs are switching at same data rate with no load.
5. tPHL propagation delay is measured from the 50% level on the falling edge of the VIN signal to the 50% level of the falling edge of the VOUT signal.
tPLH propagation delay is measured from the 50% level on the rising edge of the VIN signal to the 50% level of the rising edge of the VOUT signal.
6. PWD is defined as tPHL -tPLH.
7. tCSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between channels of the same unit at any given
temperature and supply voltages within the recommended operating conditions.
8. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature and supply
voltages within the recommended operating conditions.
9. tENABLE is the duration when VOE is set to High state and output is restored per input signal (VO = VIN).
10. tDISABLE is the duration when VOE is set to Low and VO is switched to high impedance state.
11. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VOUT > 0.8 VDD2. CML is the maximum common
mode input voltage that can be sustained while maintaining VOUT < 0.8 V. The common mode voltage slew rates apply to both rising and falling
common mode voltage edges.
12. Device considered a two-terminal device: pins 1, 2, 3, 4, 5, 6, 7, 8 shorted together and pins 9, 10, 11, 12, 13, 14, 15 and 16 shorted together.
13. In accordance with UL1577, each ACML-7400, ACML-7410 AND ACML-7420 device is proof tested by applying an insulation test voltage 6800 VRMS
for 1 second.
14. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refers to your equipment level safety specification.
15. CI is the capacitance measured at input pin.
9
Characteristic Curves
30
Idd1 5 V (0)
Idd1 5 V (25)
Idd1 5 V (100)
25
20
Idd1 3.3 V (0)
Idd1 3.3 V (25)
Idd1 3.3 V (100)
15
10
5
0
-40
-20
0
20
40
60
TA - TEMPERATURE - °C
80
IDD1 - SUPPLY CURRENT - mA
25
20
15
10
0
100
35
35
30
30
Idd1 5 V (0)
Idd1 5 V (25)
Idd1 5 V (100)
25
20
Idd1 3.3 V (0)
Idd1 3.3 V (25)
Idd1 3.3 V (100)
15
10
0
-40
-20
0
20
40
60
TA - TEMPERATURE - °C
80
10
IDD2 - SUPPLY CURRENT - mA
25
20
15
10
0
20
40
60
TA - TEMPERATURE - °C
Figure 5. Typical IDD1 of ACML-7420 vs Temperature
80
100
-40
-20
0
20
40
60
TA - TEMPERATURE - °C
Idd2 3.3V(0)
Idd2 3.3V(25)
Idd2 3.3V(100)
80
100
Figure 4. Typical IDD2 of ACML-7410 vs Temperature
30
-20
20
40
60
TA - TEMPERATURE - °C
Idd2 5V(0)
Idd2 5V(25)
Idd2 5V(100)
5
30
-40
0
15
35
5
-20
20
35
Idd1 5 V (0)
Idd1 5 V (25)
Idd1 5 V (100)
-40
Idd2 3.3 V (0)
Idd2 3.3 V (25)
Idd2 3.3 V (100)
25
0
100
Figure 3. Typical IDD1 of ACML-7410 vs Temperature
0
Idd2 5 V (0)
Idd2 5 V (25)
Idd2 5 V (100)
Figure 2. Typical IDD2 of ACML-7400 vs Temperature
5
IDD1 - SUPPLY CURRENT - mA
30
5
Figure 1. Typical IDD1 of ACML-7400 vs Temperature
10
IDD2 - SUPPLY CURRENT - mA
35
IDD2 - SUPPLY CURRENT - mA
IDD1 - SUPPLY CURRENT - mA
35
Idd1 3.3 V (0)
Idd1 3.3 V (25)
Idd1 3.3 V (100)
80
100
25
20
15
10
Idd2 5V(0)
Idd2 5V(25)
Idd2 5V(100)
5
0
-40
-20
0
20
40
60
TA - TEMPERATURE - °C
Figure 6. Typical IDD2 of ACML-7420 vs Temperature
Idd2 3.3V(0)
Idd2 3.3V(25)
Idd2 3.3V(100)
80
100
8
8
6
4
2
0
Vdd (5 V)
Vdd (3.3 V)
0
20
40
60
DATA RATE - MBd
80
IRX - SUPPLY CURRENT - mA
10
ITX - SUPPLY CURRENT - mA
10
TP - PROPAGATION DELAY - ns
TP - PROPAGATION DELAY - ns
30
28
26
-40
-20
1
0
20
40
60
TA - TEMPERATURE - °C
80
0
20
40
60
DATA RATE - MBd
80
100
0.5
0
-0.25
-20
0
20
40
60
TA - TEMPERATURE - °C
Figure 11. Typical Pulse Width Distortion vs Temperature
26
-40
-20
0
2
0.25
-0.5
-40
28
20
40
60
TA - TEMPERATURE - °C
80
100
80
100
Figure 10. Typical Propagation Delay vs Temperature
PWD (5 V)
PWD (3.3 V)
PWD (5 V/3.3 V)
PWD (3.3 V/5 V)
0.75
Tphl (5 V/3.3 V)
Tplh (5 V/3.3 V)
Tphl (3.3 V/5 V)
Tplh (3.3 V/5 V)
30
24
100
TPSK - PROPAGATION DELAY SKEW - ns
PWD - PULSE WIDTH DISTORTION - ns
Vdd (5 V)
Vdd (3.3 V)
32
Tphl (5 V)
Tplh (5 V)
Tphl (3.3 V)
Tplh (3.3 V)
Figure 9. Typical Propagation Delay vs Temperature
11
2
Figure 8. Typical Supply Current per Receive Channel vs Data Rate
32
24
4
0
100
Figure 7. Typical Supply Current per Transmit Channel vs Data Rate
6
80
100
Tpsk (5 V)
Tpsk (3.3 V)
Tpsk (5 V/3.3 V)
Tpsk (3.3 V/5 V)
1.5
1
0.5
0
-40
-20
0
20
40
60
TA - TEMPERATURE - °C
Figure 12. Typical Channel-Channel Delay Skew vs Temperature
Supply Current Consumption
It should be noted that the output supply current is
specified under no load conditions. Additional supply
current consumption from board or components loading
can be computed based on:
IDD = CVF
Where IDD is the additional supply current consumption
per output channel, C is the load capacitance, V is the
supply voltage and F is the frequency of the signal
Bypassing and PC Board Layout
The ACML-7400 series digital isolators are extremely easy
to use. No external interface circuitry is required because
ACML-7400 series use high speed CMOS IC technology
allowing CMOS logic to be connected directly to the
inputs and outputs.
As shown in Figure 13, the only external components
required for proper operation are two bypass capacitors
for decoupling the power supply. Capacitor values should
typically be 0.1 F. For each capacitor, the total lead length
between both ends of the capacitor and the power supply
pins should be as short as possible.
VDD1
VDD2
16
16
22
15
15
VIN1
33
14
14
VO1
VIN2
44
13
13
VO2
VIN3
55
12
12
VO3
VO4
66
11
11
VIN4
0.1 F
GND1
VOE1 77
88
GND1
Galvanic Isolation
11
0.1 F
GND2
10
10 VOE2
99
GND2
Figure 13. Typical Schematic of ACML-7410 on PC Board
12
Propagation Delay, Pulse-Width Distortion and
Propagation Delay Skew
Propagation Delay is a figure of merit which describes
how quickly a logic signal propagates through a system.
The propagation delay from a low to high (tPLH) is the
amount of time required for an input signal to propagate
to the output, causing the output to change from low to
high. Similarly, the propagation delay from high to low
(tPHL) is the amount of time required for the input signal
to propagate to the output, causing the output to change
from high to low. Please see Figure 14.
VDD
INPUT
50%
VIN
tPHL
tPLH
OUTPUT
90%
VOUT
10%
Figure 14. Threshold Levels of AC Parameters
0V
VOH
90%
10%
50%
VOL
Pulse-width distortion (PWD) is the difference between
tPHL and tPLH and often determines the maximum data
rate capability of a transmission system. PWD can be
expressed in percent by dividing the PWD (in ns) by the
minimum pulse width (in ns) being transmitted. Typically,
PWD on the order of 20-30% of the minimum pulse
width is tolerable. The PWD specification for ACML-7400
series is 3 ns maximum across recommended operating
conditions.
Propagation delay skew, tPSK, is an important parameter
to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If
the parallel data is sent through a group of isolators, differences in propagation delays will cause the data to
arrive at the outputs of the isolators at different times. If
this difference in propagation delay is large enough it will
determine the maximum rate at which parallel data can
be sent through the isolators.
Propagation delay skew is defined as the difference
between the minimum and maximum propagation
delays, either tPLH or tPHL for any given group of optocouplers which are operating under the same conditions (i.e.,
the same drive current, supply voltage, output load, and
operating temperature). As illustrated in Figure 15, if the
inputs of a group of isolators are switched either ON or
OFF at the same time, tPSK is the difference between the
shortest propagation delay, either tPLH or tPHL and the
longest propagation delay, either tPLH and tPHL.
The ACML-7400 series isolators offer the advantage of
guaranteed specifications for propagation delays, pulsewidth distortion, and propagation delay skew over the
recommended temperature and power supply ranges.
50%
VIN
50%
VDD2
VOUT
tPSK
VIN
50%
VOUT
50% VDD2
Figure 15. Illustration of TPSK
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved.
AV02-2675EN - May 16, 2011
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