ACNV2601-500E

ACNV2601 High Insulation Voltage 10MBd Digital Optocoupler Data Sheet Description Features The new ACNV2601 is an optically coupled gate that combines a AlGaAs light emitting diode and an integrated photo detector housed in a widebody package. The distance-through-insulation (DTI) between the emitting diode and photo-detector is at 2mm. The output of the detector IC is an open collector Schottky clamped transistor. The internal shield provides a guaranteed common mode transient immunity specification of 20 kV/μs at Vcm = 1500V • High Voltage Insulation with minimum 13mm creepage and clearance With creepage and clearance of greater than 13mm, ACNV2601 is designed to provide high isolation voltage (7500Vrms). It can withstand a continuous high working voltage of 2262 Vpeak and a surge voltage of 12,000Vpeak, meeting IEC60747-5-5, UL and CSA standard for reinforced insulation. ACNV2601 provides the high insulation voltage protection at a high data rate of 10MBd. Functional Diagram NC 1 10 Vcc Anode 2 9 Ve Cathode 3 8 Vo NC 4 NC 5 7 GND SHIELD 6 NC Truth Table (Positive Logic) LED On Off On Off On Off • 20 kV/μs Minimum Common Mode Rejection (CMR) at VCM = 1500 V • High Speed: 10 MBd Typical • TTL Compatible • Open Collector Output • Guaranteed AC and DC performance over wide temperature: -40°C to +105°C • Available in 10-Pin widebody packages • Safety Approval to be submitted for approval – Approval at 7500Vrms for 1 minute per UL1577 – CSA – IEC 60747-5-5, IEC/EN/DIN EN 60747-5-2 with Viorm =2262Vpeak Applications • High Voltage insulation • Instrument input/output isolation • Line receivers • Ground loop elimination • Isolation of high speed logic systems • Microprocessor System Interfaces ENABLE OUTPUT H H L L NC NC L H H H L H A 0.1 μF bypass capacitor must be connected between pins VCC and GND. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Ordering Information ACNV2601 is UL recognized with 7500 Vrms for 1 minute per UL1577. Option Part number RoHS Compliant ACNV2601 -000E -300E Package Surface Mount Gull Wing 500 mil DIP-10 X X X X -500E UL 7500 Vrms/ IEC 60747-5-5, 1 Minute IEC/EN/DIN EN rating 60747-5-2 Quantity Tape & Reel X X X 35 per tube X X 35 per tube X X 500 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: ACNV2601-500E to order product of 500mil DIP-10 Widebody with Gull Wing Surface Mount package in Tape and Reel packaging with both UL 7500Vrms/1min and IEC 60747-5-5, IEC/EN/DIN EN 60747-5-2 Safety Approval in RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Schematic IF ICC 10 2+ IO 8 VF – 3 SHIELD IE VE 9 7 VCC VO GND Use of a 0.1µF bypass capacitor connected between pins of 7 and 10 is recommended (see note 5). 2 10-Pin Widebody (500mils) DIP Package [13.71 ± 0.15] 0.540 ± 0.006 [11.01 ± 0.15] 0.433 ± 0.006 [11.01 ± 0.15] 0.433 ± 0.006 [3.10] 0.122 [3.90] 0.154 [0.51] 0.020 MIN [1.998] 0.08 [1.30] 0.05 TYP [5.25] 0.21 [13.01 ± 0.15] 0.512 ± 0.006 [5.25] 0.207 [13.06] 0.514 [1.78 ± 0.15] 0.070 ± 0.006 [0.48 ± 0.08] 0.019 ± 0.003 [2.54] 0.10 TYP [0.25 +0.08 -0.05 ] 0.010 +0.003 -0.002 5° T Y P Dimensions in Inches [Millimeters] 10-Pin Widebody (500mils) DIP Package with Gull Wing Surface Mount Option 300 LAND PATTERN RECOMMENDATION [11.01 ± 0.15] 0.433 ± 0.006 [16.35 ± 0.15] 0.644 ± 0.006 [2.29 ± 0.15] 0.090 ± 0.006 [14.90 ± 0.15] 0.587 ± 0.006 [1.30] 0.051 TYP [13.01 ± 0.15] 0.512 ± 0.006 [5.25] MAX 0.207 [1.78 ± 0.15] 0.070 ± 0.006 [0.75 ± 0.15] 0.030 ± 0.006 [1.00 ± 0.15] 0.039 ± 0.006 Dimension in Inches [Millimeter] 3 [2.29 ± 0.15] 0.090 ± 0.006 [1.30 ± 0.15] 0.051 ± 0.006 [13.71 ± 0.15] 0.540 ± 0.006 [0.254 +0.076 -0.051 ] 0.010 +0.003 -0.002 OM 5° N Solder Reflow Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used. Insulation and Safety Related Specifications Parameter Symbol ACNV2601 Units Conditions Minimum External Air Gap (External Clearance) L(101) 13 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (External Creepage) L(102) 13 mm Measured from input terminals to output terminals, shortest distance path along body. Minimum Internal Plastic Gap (Internal Clearance) 2.0 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. Minimum Internal Tracking (Internal Creepage) 4.6 mm Measured from input terminals to output terminals, along internal cavity. 200 V DIN IEC 112/VDE 0303 Part 1 Tracking Resistance (Comparative Tracking Index) CTI Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) IEC 60747-5-5, IEC/EN/DIN EN 60747-5-2 Insulation Characteristics* Description Symbol Characteristic Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤ 600 Vrms for rated mains voltage ≤ 1000 Vrms I – IV I – III Climatic Classification 55/105/21 Pollution Degree (DIN VDE 0110/1.89) Unit 2 Maximum Working Insulation Voltage VIORM 2262 Vpeak Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial discharge < 5 pC VPR 4241 Vpeak Input to Output Test Voltage, Method a* VIORM x 1.6 = VPR, Type and Sample Test, tm = 10 sec, Partial discharge < 5 pC VPR 3619 Vpeak Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) VIOTM 12000 Vpeak Safety-limiting values – maximum values allowed in the event of a failure. Case Temperature Input Current** Output Power** TS IS, INPUT PS, OUTPUT 150 400 1 °C mA W Insulation Resistance at TS, VIO = 500 V RS >109 Ω * Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC 60747-5-5, IEC/EN/DIN EN 60747-5-2) for a detailed description of Method a and Method b partial discharge test profiles. ** Refer to the following figure for dependence of PS and IS on ambient temperature. 4 Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature TS -55 125 °C Operating Temperature TA -40 105 °C Average Input Current IF(AVG) 20 mA Reverse Input Voltage VR 3 V Input Power Dissipation PI 40 mW Supply Voltage (1 Minute Maximum) VCC 7 V Enable Input Voltage (Not to Exceed VCC by more than 500mV) VE VCC+0.5 V Enable Input Current IE 5 mA Output Collector Current IO 50 mA Output Collector Voltage VO 7 V Output Collector Power Dissipation PO 85 mW Lead Solder Temperature TLS 245°C for 10 sec, up to seat plane Recommended Operating Conditions Parameter Symbol Min. Max. Units Input Current, Low Level Input Current, High Level IFL* 0 250 µA IFH** 9 16 mA Power Supply Voltage VCC 4.5 5.5 V Low Level Enable Voltage VEL 0 0.8 V High Level Enable Voltage VEH 2.0 VCC V Operating Temperature TA - 40 105 °C Fan Out (at RL = 1k Ω) N 5 TTL Loads Output Pull-up Resistor RL 4k Ω 330 Note 1 * The off condition can also be guaranteed by ensuring that VFL ≤0.8volts. ** The initial switching threshold is 8mA or less. It is recommended that 9mA to 16mA be used for best performance and to permit at least a 20% LED degradation guardband. 5 Electrical Specifications (DC) Over recommended operating conditions unless otherwise specified. All typicals at VCC = 5 V, TA = 25°C. Parameter Symbol High Level Output Current Min. Typ. Max. Units Test Conditions IOH 5.5 100 µA VCC = 5.5 V, VE = 2.0V VO = 5.5 V, IFL = 250 µA Input Threshold Current ITH 3.5 8 mA VCC = 5.5 V, VE = 2.0V, VO = 0.6 V, IOL > 13 mA 1, 2 12 Low Level Output Voltage VOL 0.35 0.6 V VCC = 5.5 V, VE = 2.0V, IF = 8 mA, IOL(Sinking) = 13 mA 1, 2, 3, 4 12 High Level Supply Current ICCH 7.0 12 mA VE = 0.5V 6.5 Low Level Supply Current ICCL 9.0 VE = VCC 13 mA 8.5 High Level Enable Current IEH Low Level Enable Current IEL High Level Enable Voltage VEH Low Level Enable Voltage VEL Input Forward Voltage VF Input Reverse Breakdown Voltage BVR Input Capacitance CIN Input Diode Temperature Coefficient ΔVF/ΔTA VCC = 5.5 V, VE = 2.0V -0.9 mA VCC = 5.5 V, VE = 0.5V mA VCC = 5.5 V, VE = 2.0V 0.8 mA VCC = 5.5 V, VE = 0.5V 1.85 V TA = 25°C V IR = 100 µA, TA = 25°C 60 pF f = 1 MHz, VF = 0 V -1.9 mV/°C IF = 10 mA IF = 10 mA 2.05 5 12 VCC = 5.5 V, IF = 10 mA mA 1.64 Note VCC = 5.5 V, IF = 0 mA -0.7 1.2 6 VE = VCC 2.0 1.25 VE = 0.5V Fig. 12 5 Switching Specifications (AC) Over recommended temperature (TA = -40°C to 105°C), VCC = 5 V, IF = 10mA unless otherwise specified. All typicals are at TA = 25°C, VCC = 5V. Parameter Symbol Min. Typ. Max. Units Test Conditions Propagation Delay Time to High Output Level tPLH 30 50 80 ns TA = 25°C Propagation Delay Time to Low Output Level tPHL ns TA = 25°C Pulse Width Distortion |tPHL - tPLH| 40 ns RL = 350 Ω, CL = 15 pF Propagation Delay Skew tpsk 50 ns Output Rise Time (10%-90%) Tr 120 35 55 80 Fig. RL = 350Ω, CL = 15 pF Note 6, 7, 8 3, 12 4,12 120 5 25 ns 6, 7, 8, 9 6, 12 5, 6, 12 10 12 10 12 Output Fall Time (10%-90%) Tf 10 ns Propagation Delay Time of Enable from VEH to VEL tELH 30 ns RL = 350 Ω, CL = 15 pF, VEL = 0V, VEH = 3V 11, 12 7 Propagation Delay Time of Enable from VEL to VEH tEHL 20 ns RL = 350 Ω, CL = 15 pF, VEL = 0V, VEH = 3V 11, 12 8 Output High Level Common Mode Transient Immunity |CMH| 20 25 kV/µs VCC = 5 V, IF = 0 mA, VO(MIN) = 2 V, RL = 350 Ω, TA = 25°C, VCM = 1500 V 13 Output Low Level Common Mode Transient Immunity |CML| 20 25 kV/µs VCC = 5 V, IF = 10 mA, VO(MAX) = 0.8 V, RL = 350 Ω, TA = 25°C, VCM = 1500 V Parameter Symbol Min. Typ. Units Test Conditions Input-Output Insulation VISO 7500 Vrms RH < 50% for 1 min. TA = 25°C 13, 14 Input-Output Resistance RI-O 1012 Ω VI-O = 500 V 13 Input-Output Capacitance CI-O pF f = 1 MHz, TA = 25°C 13 9, 11, 12 10, 11, 12 All typicals at TA = 25°C. 0.5 Max. 0.6 Fig. Note Notes: 1. Peaking circuits may produce transient input currents up to 50mA, 50ns maximum pulse width, provided average current does not exceed 20mA. 2. By passing of power supply line is required, with a 0.1µF ceramic disc capacitor adjacent to each optocoupler as illustrated in Figure 15. Total lead length between both ends of the capacitor and the isolator pins should ot exceed 20mm. 3. The tPLH propagation delay is measured from the 5 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of the output pulse. 4. The tPHL propagation delay is measured from the 5 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of the output pulse. 5. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature and specified test conditions. 6. See application section titled “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information. 7. The tELH enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V point on the rising edge of the output pulse. 8. The tEHL enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point on the falling edge of the output pulse. 9. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state (i.e., VO > 2.0 V). 10. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., VO < 0.8 V). 11. For sinusoidal voltages, (|dVCM | / dt)max = πfCMVCM(p-p). 12. No external pull up is required for a high logic state on the enable input. If the VE pin is not used, tying VE to VCC will result in improved CMR performance. 13. Device considered a two-terminal device: pins 1, 2, 3, 4 and 5 shorted together, and pins 6, 7, 8, 9 and 10 shorted together. 14. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 9000 Vrms for one second (leakage detection current limit, II-O ≤ 5 μA). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC 60747-5-5, IEC/ EN/DIN EN 60747-5-2 Insulation Characteristics Table, if applicable. 7 6 6 VO - OUTPUT VOLTAGE - V 5 ITH - INPUT THRESHOLD CURRENT - mA VCC = 5V TA = 25°C 4 RL = 350 Ω 3 RL = 1k Ω 2 RL = 4k Ω 1 0 0 1 2 3 4 IF - FORWARD INPUT VOLTAGE - mA 0.6 0.5 I0 = 16 mA IOL - LOW LEVEL OUTPUT CURRENT - mA VOL - Low Level Output Voltage - V VCC = 5.5 V VE = 2.0 V IF = 8.0 mA 0.7 I0 = 13 mA 0.4 0.3 0.2 I0 = 9.6 mA 0.1 -60 -40 I0 = 6.4 mA -20 0 20 40 TA - TEMPERATURE - °C 60 80 100 120 1 VCC = 5.0 V VE = 0.6 V -60 -40 -20 0 20 40 60 TA - TEMPERATURE - °C 80 100 120 100.000 10.000 1.000 0.100 0.010 0.001 TA = 25°C 1.2 1.3 1.4 1.5 1.6 VF - FORWARD VOLTAGE - V Figure 5. Typical input diode forward characteristic. VCC = 5.5 V VE = 2.0 V VOL = 0.6 V 60 IF = 14-16 mA 50 40 IF = 10 mA IF = 8 mA 30 20 -60 -40 -20 0 20 40 60 TA - TEMPERATURE - °C 80 Figure 4. Typical low level output current vs. temperature. 1000.000 IF - FORWARD CURRENT - mA 2 70 Figure 3. Typical low level output voltage vs. temperature. 8 RL = 350 Ω, 1k Ω, 4k Ω 3 Figure 2. Typical input threshold current vs. temperature. 0.8 0 4 0 5 Figure 1. Typical output voltage vs. forward input voltage current. 5 1.7 1.8 100 120 +5 V IF PULSE GEN. ZO = 50Ω tf = tr = 5 ns INPUT MONITORING NODE RM 1 10 2 9 3 8 4 7 SHIELD 5 0.1µF BYPASS *CL IS APPROXIMATELY 15 pF WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE. RL OUTPUT VO MONITORING NODE *CL IF = 10 mA IF = 5 mA INPUT IF tPHL tPLH OUTPUT VO 6 1.5 V Figure 6. Test circuit for tPHL and tPLH 90 VCC = 5.0 V TA = 25°C 90 tPLH, RL = 4kΩ 80 tp - PROPAGATION DELAY - ns tp - PROPAGATION DELAY - ns 100 70 tPLH, RL = 1kΩ 60 tPHL, RL = 350Ω 50 40 tPLH, RL = 350Ω 30 20 -60 -40 -20 tPHL, RL = 1kΩ 4kΩ 0 20 40 60 TA - TEMPERATURE - °C 80 100 40 35 30 25 20 15 10 5 0 -5 -10 50 tPHL, RL = 1kΩ 40 8 9 tPHL, RL = 4kΩ 10 11 12 13 IF - PULSE INPUT CURRENT - mA 14 15 300 RL = 4kΩ 250 VCC = 5.0 V IF = 10.0 mA RL = 350Ω -60 -40 -20 RL = 1kΩ 0 20 40 60 TA - TEMPERATURE - °C Figure 9. Typical pulse width distortion vs. temperature. 9 tPLH, RL = 350Ω tPLH, RL = 1kΩ tPHL, RL = 350Ω 60 Figure 8. Typical propagation delay vs. pulse input current. tr, tf - RISE,FALL TIME - ns PWD - PULSE WIDTH DISTORTION - ns Figure 7. Typical propagation delay vs. temperature. VCC = 5.0 V TA = 25°C 70 30 120 tPLH, RL = 4kΩ 80 80 100 120 RL = 4kΩ 200 tRISE tFALL VCC = 5.0 V IF = 10.0 mA 150 100 RL = 1kΩ 50 0 RL = 350Ω -60 -40 -20 RL = 350Ω, 1kΩ, 4kΩ 0 20 40 60 TA - TEMPERATURE - °C Figure 10. Typical rise and fall time vs. temperature. 80 100 120 PULSE GEN. ZO = 50Ω tf = tr = 5 ns INPUT VE MONITORING NODE +5 V 10 mA IF 1 10 2 9 3 8 4 SHIELD 5 7 0.1µF BYPASS *CL RL 3.0 V 1.5 V INPUT VE OUTPUT VO MONITORING NODE tEHL tELH OUTPUT VO 6 *CL IS APPROXIMATELY 15 pF WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE. Figure 11. Test circuit for tEHL and tELH. tE - ENABLE PROPAGATION DELAY - ns 100 VCC = 5.0 V VEH = 3.0 V VEL = 3.0 V tELH, RL = 4kΩ IF = 10.0 mA 80 60 tELH, RL = 1kΩ 40 tELH, RL = 350Ω 20 tELH, RL = 350Ω, 1kΩ, 4kΩ 0 -60 -40 -20 0 20 40 60 TA - TEMPERATURE - °C 80 Figure 12. Typical enable propagation delay vs. temperature. 10 100 120 1.5 V SINGLE CHANNEL IF B A VFF 1 10 2 9 3 8 4 SHIELD 5 +5 V 0.1 µF BYPASS 7 RL OUTPUT VO MONITORING NODE VCM 6 VO VCM + – PULSE GENERATOR ZO = 50 Ω VO VCM (PEAK) 0V = 0 mA 5 V SWITCH AT A: IF 0.5 V VO (MIN.) SWITCH AT B: IF = 10 mA VO (MAX.) OUTPUT POWER - PS, INPUT CURRENT - IS Figure 13. Test circuit for common mode transient immunity and typical waveforms. 1100 1000 900 800 700 600 500 400 300 200 100 0 PS (mW) IS (mA) 0 25 50 75 100 125 Ts - CASE TEMPERATURE - °C 150 175 Figure 14. Thermal derating curve, dependence of safety limiting value with case temperature per IEC 60747-5-5, IEC/EN/DIN EN 60747-5-2. GND BUS (BACK) VCC BUS (FRONT) NC 0.1 µF NC NC ENABLE OUTPUT NC 10 mm MAX. (SEE NOTE 5) SINGLE CHANNEL DEVICE ILLUSTRATED. Figure 15. Recommended printed circuit board layout. For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved. AV02-2456EN - August 31, 2011 CMH CML