ACNV4506-500E

ACNV4506 Intelligent Power Module and Gate Drive Interface Optocouplers Data Sheet Description Features The ACNV4506 device contains a GaAsP LED optically coupled to an integrated high gain photo detector. Minimized propagation delay difference between devices makes these optocouplers excellent solutions for improving inverter efficiency through reduced switching dead time. Specifications and performance plots are given for typical IPM applications. • Performance Specified for Common IPM Applications Over Industrial Temperature Range. Functional Diagram • Available in Widebody DIP10 and GulWing packages with 13.0 mm creepage and clearance. N.C. 1 Specifications CATHODE 3 8 VO Note: A 0.1 µF bypass capacitor must be connected between pins 7 and 10. Truth Table LED VO ON LOW OFF HIGH • High CTR. 6 N.C. 9 VL N.C. 5 • Very High Common Mode Rejection (CMR) 7 Ground ANODE 2 SHIELD • Minimized Pulse Width Distortion (PWD) • Safety Approval (pending): – UL Recognized with 7500 Vrms for 1 minute per UL1577. – CSA Approved. – IEC/EN/DIN EN 60747-5-2 Approved with VIORM = 2262Vpeak. 10 VCC 20kΩ N.C. 4 • Short Maximum Propagation Delays • Wide operating temperature range: –40°C to 105°C. • Typical propagation delay tPHL = 200 ns, tPLH = 350 ns • Typical Pulse Width Distortion (PWD) = 150 ns. • 30 kV/µs minimum common mode rejection (CMR) at VCM = 1500 V. • CTR = 90%(typ) at IF = 10mA Applications • IPM Isolation • Isolated IGBT/MOSFET Gate Drive • AC and Brushless DC Motor Drives • Industrial Inverters CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Ordering Information ACNV4506 is pending UL recognition with 7500Vrms for 1 minute per UL1577. Option Part number RoHS Compliant Package ACNV4506 -000E 500 mil -300E DIP-10 -500E Surface Mount Gull Wing X X X X Tape &Reel X UL 7500Vrms/ 1 Minute rating IEC/EN/DIN EN 60747-5-2 Quantity X X 35 per tube X X 35 per tube X X 500 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: ACNV4506-500E to order product of 500mil DIP-10 Widebody with Gull Wing Surface Mount package in Tape and Reel packaging with both UL 7500Vrms/1min and IEC/EN/DIN EN60747-5-2 Safety Approval in RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. 2 Package Outline Drawings ACNV4506 Widebody 500Mils DIP10 Package, 13.0 mm clearance [13.69 ± 0.15] 0.539 ± 0.006 [11.01 ± 0.15] 0.433 ± 0.006 [13.01 ± 0.15] 0.512 ± 0.006 [1.30] 0.05 TYP [11.01 ± 0.15] 0.433 ± 0.006 [3.10] 0.122 [3.90] 0.154 [1.998] 0.08 [5.25] 0.21 [0.51] 0.020 MIN [5.25] 0.207 [13.06] 0.514 [1.78 ± 0.15] 0.070 ± 0.006 [0.48 ± 0.08] 0.019 ± 0.003 [2.54] 0.10 TYP [0.25 +0.08 -0.05 ] 0.010 +0.003 -0.002 5° T Y P Dimensions in Inches [Millimeters] ACNV4506 Widebody 500Mils GulWing Tape & Reel Package, 13.0 mm clearance LAND PATTERN RECOMMENDATION [11.01 ± 0.15] 0.433 ± 0.006 [16.35 ± 0.15] 0.644 ± 0.006 [2.29 ± 0.15] 0.090 ± 0.006 [14.90 ± 0.15] 0.587 ± 0.006 [1.30] 0.051 TYP [13.01 ± 0.15] 0.512 ± 0.006 [5.25] MAX 0.207 [1.78 ± 0.15] 0.070 ± 0.006 [0.75 ± 0.15] 0.030 ± 0.006 [1.00 ± 0.15] 0.039 ± 0.006 Dimension in Inches [Millimeter] 3 [2.29 ± 0.15] 0.090 ± 0.006 [1.30 ± 0.15] 0.051 ± 0.006 [13.71 ± 0.15] 0.540 ± 0.006 [0.254 +0.076 -0.051 ] 0.010 +0.003 -0.002 OM 5° N Solder Reflow Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used. Regulatory Information The ACNV4506 is pending approval from the following organizations: IEC CSA IEC/EN/DIN EN 60747-5-2:2009 Approval under CSA Component Acceptance Notice #5, File CA 88324. UL Approval under UL 1577, component recognition program up to VISO = 7500 VRMS. File E55361. Table 1. IEC/EN/DIN EN 60747-5-2 Insulation Characteristics* (ACNV4506) Description Symbol Climatic Classification (IEC 68 Part I) Characteristic Unit 55/105/21 Maximum Working Insulation Voltage VIORM 2262 Vpeak Input to Output Test Voltage, Method b* VIORM x 1.875=VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC VPR 4242 Vpeak Input to Output Test Voltage, Method a* VIORM x 1.6=VPR, Type and Sample Test, tm=10 sec, Partial discharge < 5 pC VPR 3619 Vpeak Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) VIOTM 12000 Vpeak Safety-limiting values – maximum values allowed in the event of a failure (also see Figure 13). Case Temperature Input Current Output Power TS IS, INPUT PS, OUTPUT 115 400 1 °C mA W Insulation Resistance at TS, VIO = 500 V RS >109 Ω * Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/DIN EN 60747-5-2) for a detailed description of Method a and Method b partial discharge test profiles. 4 Table 2. Insulation and Safety Related Specifications Parameter Symbol ACNV4506 Units Conditions Minimum External Air Gap (External Clearance) L(101) 13.0 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (External Creepage) L(102) 13.0 mm Measured from input terminals to output terminals, shortest distance path along body. Minimum Internal Plastic Gap (Internal Clearance) 2 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. Minimum Internal Tracking (Internal Creepage) NA mm Measured from input terminals to output terminals, along internal cavity. >175 V DIN IEC 112/VDE 0303 Part 1 Tracking Resistance (Comparative Tracking Index) CTI Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Table 3. Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature Tstorage -55 125 °C Operating Temperature TA -40 105 °C Average Input Current IF(avg) 25 mA 1 Peak Input Current (50% duty cycle, 3.0 V IF = 10 mA, VO < 1.0 V VCC = 15.0 V, CL = 100 pF, VCM = 1500 VP-P, TA = 25°C Fig. Note 8 8, 9 6 11 12 * All typical values at 25°C, VCC = 15 V. Table 8. Package Characteristics Parameter Symbol Min. Input-Output Momentary Withstand Voltage VISO 7500 Input-Output Resistance RI-O Input-Output Capacitance CI-O Max. Units Test Conditions Vrms RH < 50%, t = 1 min, TA = 25°C Fig. Note 6, 7 1012 Ω VI-O = 500 Vdc 6 0.6 pF Freq=1 MHz 6 Notes: 1. Derate linearly above 90°C free-air temperature at a rate of 0.8 mA/°C. 2. Derate linearly above 90°C free-air temperature at a rate of 1.6 mA/°C. 3. Derate linearly above 90°C free-air temperature at a rate of 3.0 mW/°C. 4. Derate linearly above 90°C free-air temperature at a rate of 4.2 mW/°C. 5. CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current (IO) to the forward LED input current (IF) times 100. 6. Device considered a two-terminal device: Pins 1-5 shorted together and Pins 6-10 shorted together. 7. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 7500 VRMS for 1 minute (leakage detection current limit, II-O ≤ 5 μA). 8. Pulse: f = 20 kHz, Duty Cycle = 10%. 9. Use of a 0.1 μF bypass capacitor connected between pins 7 and 10 can improve performance by filtering power supply line noise. 10. The difference between tPLH and tPHL between any two parts under the same test condition. (See IPM Dead Time and Propagation Delay Specifications section.) 11. Common mode transient immunity in a Logic High level is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in a Logic High state (i.e., VO > 3.0 V). 12. Common mode transient immunity in a Logic Low level is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in a Logic Low state (i.e., VO < 1.0 V). 13. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH| for any given device. 7 1.02 105°C 25°C 8 -40°C 6 4 2 VO = 0.6 V 0 0 5 10 15 IF - FORWARD LED CURRENT - mA 0.98 0.96 0.94 0.9 -40 -20 0 20 40 60 TA – TEMPERATURE – °C 80 100 IF - INPUT FORWARD CURRENT-mA VF = 0.8 V VCC = VO = 4.5 V OR 30 V 3.5 3 2.5 2 1.5 30 V 1 4.5 V 0.5 -40 -20 0 20 40 60 TA – TEMPERATURE – °C 80 1 + VF – 1 0.1 0.01 TA = 25°C 1 1.2 1.4 1.6 1.8 VF - INPUT FORWARD VOLTAGE - V Figure 4. Input Current vs. Forward Voltage 10 IF(ON) = 10 mA + - Π IF 10 0.001 100 Figure 3. High Level Output Current vs. Temperature 0.1µF 20kΩ 2 9 3 8 4 7 SHIELD 5 If tf VO VOUT + V = 15 CC CL* VTHHL * TOTAL LOAD CAPACITANCE 6 tPHL tr 90% 90% 10% 10% VTHLH tPLH Figure 5. Propagation Delay Test Circuit 1 IF 10 8 + VFF A 4 VCM 9 3 5 - 0.1µF 20kΩ 2 B 100 Figure 2. Normalized Output Current vs. Temperature 4 0 IF = 10 mA VO = 0.6 V 0.92 20 Figure 1. Typical Transfer Characteristics IOH - HIGH LEVEL OUTPUT CURRENT - µA 1 NORMALIZED OUTPUT CURRENT IO - OUTPUT CURRENT - mA 10 8 SHIELD VOUT + V = 15 CC 100 pF * 7 * 100 pF TOTAL 6 CAPACITANCE δV = VCM δt ∆t OV ∆t VO SWITCH AT A: IF = 0 mA VO VCC 2 5 6 1 9 3 VFF VOUT + V = 15 CC 100 pF * 8 4 + tPLH VCM 0.1µF 20kΩ 2 A tPHL 10 IF B CAPACITANCE SHIELD 7 ∆t VCC SWITCH AT A: IF = 0 mA VO + - - OV VO * 100 pF TOTAL 6 CAPACITANCE 5 δV = VCM δt ∆t VOL SWITCH AT B: IF = 10 mA VCM = 1500V Π Figure 6. CMR Test Circuit and Waveforms 500 IF = 10 mA VCC = 15 V CL = 100 pF RL = 20 kΩ (EXTERNAL) 400 tP - PROPAGATION DELAY - ns tP - PROPAGATION DELAY - ns 500 tPLH 300 200 100 tPHL -40 -20 0 20 40 60 TA - TEMPERATURE - °C 80 Figure 7. Propagation Delay with External 20 kΩ RL vs. Temperature 800 tPLH 600 400 200 0 tPHL 0 10 20 30 RL – LOAD RESISTANCE – kΩ Figure 9. Propagation Delay vs. Load Resistance 9 300 tPHL 200 -40 1400 IF = 10 mA VCC = 15 V CL = 100 pF TA = 25°C 40 tPLH -20 0 20 40 TA - TEMPERATURE - °C 60 80 100 Figure 8. Propagation Delay with Internal 20 kΩ RL vs. Temperature tP - PROPAGATION DELAY - ns tP - PROPAGATION DELAY - ns 1000 400 100 100 IF = 10 mA VCC = 15 V CL = 100 pF RL = 20 kΩ (INTERNAL) 50 IF = 10 mA VCC = 15 V RL = 20 kΩ TA = 25°C 1200 1000 tPLH 800 600 400 tPHL 200 0 0 100 200 300 400 CL - LOAD CAPACITANCE - pF Figure 10. Propagation Delay vs. Load Capacitance 500 500 IF = 10 mA CL = 100 pF RL = 20 kΩ TA = 25°C 2000 tP - PROPAGATION DELAY - ns tP - PROPAGATION DELAY - ns 2500 1500 1000 tPLH 500 400 tPLH VCC = 15 V CL = 100 pF RL = 20 kΩ TA = 25°C 300 200 tPHL tPHL 0 0 5 10 15 20 VCC - SUPPLY VOLTAGE - V 25 30 OUTPUT POWER - PS, INPUT CURRENT - IS Figure 11. Propagation Delay vs. Supply Voltage 1100 1000 900 800 700 600 500 400 300 200 100 0 PS (mW) IS (mA) 0 10 20 30 40 50 60 70 80 90 100 110 120 TS - CASE TEMPERATURE - °C Figure 13. Dependence of Safety Limiting Values on Temperatures (Thermal Derating Curves) 10 100 0 5 10 15 IF - FORWARD LED CURRENT - mA Figure 12. Propagation Delay vs. Input Current 20 Applications Information LED Drive Circuit Considerations For Ultra High CMR Performance Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure 15. The ACNV4506 improve CMR performance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. However, this shield does not eliminate the capacitive coupling between the LED and the optocoupler output pin and output ground as shown in Figure 16. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off ) during common mode transients. For example, the recommended application circuit (Figure 14), can achieve 30 kV/µs CMR while minimizing component complexity. Note that a CMOS gate is recommended in Figure 14 to keep the LED off when the gate is in the high state. Another cause of CMR failure for a shielded optocoupler is direct coupling to the optocoupler output pins through CLEDO1 in Figure 16. Many factors influence the effect and magnitude of the direct coupling including: the position of the LED current setting resistor and the value of the capacitor at the optocoupler output (CL). 1 +5 V 310Ω CMOS 9 3 8 VOUT CL* 4 + VCC = 15V - 7 SHIELD *100 pF TOTAL 6 CAPACITANCE 5 Figure 14. Recommended LED Drive Circuit 1 10 20kΩ CLEDP 2 3 9 8 CLEDN 4 7 5 6 Figure 15. Optocoupler Input to Output Capacitance Model for Unshielded Optocouplers 1 2 A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. The recommended minimum LED current of 10 mA provides adequate margin over the maximum ITH of 5.0 mA (see Figure 1) to achieve 30 kV/µs CMR. 3 11 0.1µF 2 CMR With The LED On (CMRL) The placement of the LED current setting resistor effects the ability of the drive circuit to keep the LED on during transients and interacts with the direct coupling to the optocoupler output. For example, the LED resistor in Figure 17 is connected to the anode. Figure 18 shows the AC equivalent circuit for Figure 17 during common mode transients. During a +dVCM/dt in Figure 18, the current available at the LED anode (Itotal) is limited by the series resistor. The LED current (IF) is reduced from its DC value by an amount equal to the current that flows through CLEDP and CLEDO1. The situation is made worse because the current through CLEDO1 has the effect of trying to pull the output high (toward a CMR failure) at the same time the LED current is being reduced. For this reason, the recommended LED drive circuit (Figure 14) places the current setting resistor in series with the LED cathode. Figure 19 10 20kΩ 4 10 20kΩ CLEDP 9 CLED01 8 CLEDN 7 SHIELD 5 6 Figure 16. Optocoupler Input to Output Capacitance Model for Shielded Optocouplers 1 10 0.1µF 20kΩ +5 V 310Ω CMOS 2 9 3 8 4 5 SHIELD VOUT + - VCC = 15V CL* 7 *100 pF TOTAL 6 CAPACITANCE Figure 17. LED Drive Circuit with Resistor Connected to LED Anode (Not Recommended) is the AC equivalent circuit for Figure 14 during common mode transients. In this case, the LED current is not reduced during a +dVCM/dt transient because the current flowing through the package capacitance is supplied by the power supply. During a -dVCM/dt transient, however, the LED current is reduced by the amount of current flowing through CLEDN. But, better CMR performance is achieved since the current flowing in CLEDO1 during a negative transient acts to keep the output low. 1 2 300Ω + Since the open collector drive circuit, shown in Figure 20, cannot keep the LED off during a +dVCM/dt transient, it is not desirable for applications requiring ultra high CMRH performance. Figure 21 is the AC equivalent circuit for Figure 20 during common mode transients. Essentially all the current flowing through CLEDN during a +dVCM/dt transient must be supplied by the LED. CMRH failures can occur at dv/dt rates where the current through the LED and CLEDN exceeds the input threshold. Figure 22 is an alternative drive circuit which does achieve ultra high CMR performance by shunting the LED in the off state. 9 CLED01 3 CLEDN I * 4 CLEDN - VOUT 8 20kΩ 100 pF 7 SHIELD 5 CMR With The LED Off (CMRH) 6 * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW FOR +dVCM/dt TRANSIENTS. ** OPTIONAL CLAMPING DIODE FOR IMPROVED CMH PERFORMANCE. VR < VF (OFF) DURING +dVCM/dt. + - A high CMR LED drive circuit must keep the LED off (VF ≤ VF(OFF)) during common mode transients. For example, during a +dVCM/dt transient in Figure 19, the current flowing through CLEDN is supplied by the parallel combination of the LED and series resistor. As long as the voltage developed across the resistor is less than VF(OFF) the LED will remain off and no common mode failure will occur. Even if the LED momentarily turns on, the 100 pF capacitor from pins 8-7 will keep the output from dipping below the threshold. The recommended LED drive circuit (Figure 14) provides about 10 V of margin between the lowest optocoupler output voltage and a 3 V IPM threshold during a 30 kV/µs transient with VCM = 1500 V. Additional margin can be obtained by adding a diode in parallel with the resistor, as shown by the dashed line connection in Figure 19, to clamp the voltage across the LED below VF(OFF). VR** 10 20kΩ CLEDP VCM Figure 19. AC Equivalent Circuit for Figure 14 during Common Mode Transients 1 10 20kΩ +5 V Q1 2 9 3 8 4 7 SHIELD 5 6 Figure 20. Not Recommended Open Collector LED Drive Circuit 1 2 Q1 300Ω 3 4 10 20kΩ CLEDP CLED01 9 8 CLEDN I CLEDN* SHIELD 5 20kΩ VOUT 7 100 pF 6 + - VCM 1 ITOTAL* 300Ω IF 2 3 4 10 ICLEDP CLEDP * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW FOR +dVCM/dt TRANSIENTS. 20kΩ CLED01 9 8 CLEDN SHIELD 100 pF +5 V 1 10 20kΩ 6 2 9 * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW DURING +dVCM/dt 3 8 + - 5 7 Figure 21. AC Equivalent Circuit for Figure 20 during Common Mode Transients VOUT VCM 4 Figure 18. AC Equivalent Circuit for Figure 17 during Common Mode Transients 5 SHIELD 7 6 Figure 22. Recommended LED Drive Circuit for Ultra High CMR 12 IPM Dead Time and Propagation Delay Specifications The ACNV4506 includes a Propagation Delay Difference specification intended to help designers minimize “dead time” in their power inverter designs. Dead time is the time period during which both the high and low side power transistors (Q1 and Q2 in Figure 23) are off. Any overlap in Q1 and Q2 conduction will result in large currents flowing through the power devices between the high and low voltage motor rails. To minimize dead time the designer must consider the propagation delay characteristics of the optocoupler as well as the characteristics of the IPM IGBT gate drive circuit. Considering only the delay characteristics of the optocoupler (the characteristics of the IPM IGBT gate drive circuit can be analyzed in the same way) it is important to know the minimum and maximum turn on (tPHL) and turn-off (tPLH) propagation delay specifications, preferably over the desired operating temperature range. The limiting case of zero dead time occurs when the input to Q1 turns off at the same time that the input to Q2 turns on. This case determines the minimum delay between LED1 turn-off and LED2 turn-on, which is related to the worst case optocoupler propagation delay waveforms, as shown in Figure 24. A minimum dead time of zero is achieved in Figure 24 when the signal to turn on LED2 is delayed by (tPLH max - tPHL min) from the LED1 turn off. Note that the propagation delays used to calculate PDD are taken at equal temperatures since the optocouplers under consideration are typically mounted in close proximity to each other. (Specifically, previous equation are not the same as the tPLH max and tPHL min, over the full operating temperature range, specified in the data sheet.) This delay is the maximum value for the propagation delay difference specification which is specified at 450 ns for the ACNV4506 over an operating temperature range of -40°C to 105°C. Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time occurs in the highly unlikely case where one optocoupler with the fastest tPLH and another with the slowest tPHL are in the same inverter leg. The maximum dead time in this case becomes the sum of the spread in the tPLH and tPHL propagation delays as shown in Figure 25. The maximum dead time is also equivalent to the difference between the maximum and minimum propagation delay difference specifications. The maximum dead time (due to the optocouplers) for the ACNV4506 are 600 ns (= 450 ns - (-150 ns)) over an operating temperature range of -40°C to 105°C. IPM ILED1 +5 V 1 2 310Ω CMOS ILED2 CMOS 8 SHIELD 1 10 20kΩ 3 5 Figure 23. Typical Application Circuit VOUT1 +HV Q1 7 6 M M VCC2 0.1µF 9 8 SHIELD VCC1 0.1µF 7 6 4 13 9 5 2 310Ω 20kΩ 3 4 +5 V 10 Q2 VOUT2 ACNV4506 ACNV4506 ACNV4506 ACNV4506 ACNV4506 -HV ILED1 ILED1 Q1 OFF VOUT1 VOUT2 Q1 ON Q1 OFF VOUT1 VOUT2 Q2 OFF Q1 ON Q2 OFF Q2 ON ILED2 Q2 ON ILED2 tPLH MAX. tPLH MIN. tPHL MIN. tPLH MAX. PDD* MAX. = (tPLH-tPHL) MAX. = tPLH MAX. - tPHL MIN. PDD* MAX. *PDD = PROPAGATION DELAY DIFFERENCE tPHL MIN. tPHL MAX. Note: The propagation delays used to calculate PDD are taken at equal temperatures. MAX. DEAD TIME Figure 24. Minimum LED Skew for Zero Dead Time MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) = (tPLH MAX. - tPLH MIN.) + (tPHL MAX. - tPHL MIN.) = (tPLH MAX. - tPHL MIN.) - (tPLH MIN. - tPHL MAX.) = PDD* MAX. - PDD* MIN. *PDD = PROPAGATION DELAY DIFFERENCE Note: The propagation delays used to calculate the maximum Dead time are taken at equal temperatures. Figure 25. Waveforms for Deadtime Calculation For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved. AV02-2483EN - August 31, 2011