ACPL-3130/J313, ACNW3130
Very High CMR 2.5 Amp Output Current IGBT Gate Driver Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
The ACPL-3130 contains a GaAsP LED while the ACPLJ313 and the ANCW3130 contain an AlGaAs LED. The LED
is optically coupled to an integrated circuit with a power
output stage. These optocouplers are ideally suited for
driving power IGBTs and MOSFETs used in motor control
inverter applications. The high operating voltage range
of the output stage provides the drive voltages required
by gate controlled devices. The voltage and current
supplied by these optocouplers make them ideally suited
for directly driving IGBTs with ratings up to 1200 V/100 A.
For IGBTs with higher ratings, the ACPL-3130 series can be
used to drive a discrete power stage which drives the IGBT
gate. The ANCW3130 has the highest insulation voltage of
VIORM = 1414 Vpeak in the IEC/EN/DIN EN 60747-5-2. The
ACPL-J313 has an insulation voltage of VIORM = 891 Vpeak
and the VIORM = 630 Vpeak is also available with the ACPL3130 (Option 060).
•
•
•
•
Functional Diagram
N/C
1
8 V CC
ANODE
2
7 VO
CATHODE
3
6 VO
N/C
4
SHIELD
5 V EE
ACPL-3130 and ACPL-J313
N/C
1
8 V CC
ANODE
2
7 VO
CATHODE
3
6 N/C
N/C
4
5 V EE
SHIELD
High speed response.
Very high CMR.
Bootstrappable supply current.
Safety Approval (pending):
UL Recognized
- 3750 Vrms for 1 min. for ACPL-3130/J313.
- 5000 Vrms for 1 min. For ACNW3130
CSA Approval
IEC/EN/DIN EN 60747-5-2 Approved
- VIORM = 630 Vpeak for ACPL-3130 (Option 060)
- VIORM = 891 Vpeak for ACPL-J313
- VIORM = 1414 Vpeak for ACNW3130
Specifications
• 2.5 A maximum peak output current.
• 2.0 A minimum peak output current.
• 40 kV/µs minimum Common Mode Rejection (CMR) at
VCM = 1500 V
• 0.5 V maximum low level output voltage (VOL) eliminates
need for negative gate drive
• ICC = 5 mA maximum supply current
• Under Voltage Lock-Out protection (UVLO) with
hysteresis
• Wide operating VCC range: 15 to 30 Volts
• 500 ns maximum switching speeds
• Industrial temperature range: -40°C to 100°C
Applications
• IGBT/MOSFET gate drive
• AC/Brushless DC motor drives
• Industrial inverters
• Switching Power Supplies (SPS)
ACNW3130
Note: A 0.1 µF bypass capacitor must be connected between pins VCC and VEE.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Truth Table
LED
VCC – VEE
“POSITIVE GOING”
(i.e., TURN-ON)
VCC – VEE
“NEGATIVE GOING”
(i.e., TURN-OFF)
VO
OFF
0 - 30 V
0 - 30 V
LOW
ON
0 - 11 V
0 - 9.5 V
LOW
ON
11 - 13.5 V
9.5 - 12 V
TRANSITION
ON
13.5 - 30 V
12 - 30 V
HIGH
Ordering Information
ACPL-3130 and ACPL-J313 are UL Recognized with 3750 Vrms for 1 minute per UL1577. ACNW3130 is UL Recognized
with 5000Vrms for 1 minute per UL1577.
Option
Part number
RoHS Compliant
Package
Surface
Mount
Gull
Wing
Tape
& Reel
IEC/EN/DIN EN
60747-5-2
-000E
50 per tube
-300E
ACPL-3130
-500E
-060E
ACPL-J313
X
X
X
X
X
-560E
X
X
-300E
-500E
-000E
ACNW3130
300mil
DIP-8
X
-360E
-000E
-300E
-500E
Quantity
300mil
DIP-8
400mil
DIP-8
X
X
X
X
X
X
X
X
50 per tube
X
X
X
X
1000 per reel
X
50 per tube
X
50 per tube
X
1000 per reel
X
50 per tube
X
50 per tube
X
1000 per reel
X
42 per tube
X
42 per tube
X
750 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-3130-560E to order product of 300mil DIP Gull Wing Surface Mount package in Tape and Reel packaging with
IEC/EN/DIN EN 60747-5-2 Safety Approval in RoHS compliant.
Example 2:
ACPL-3130-000E to order product of 300mil DIP package in tube packaging and RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and RoHS
compliant option will use ‘-XXXE‘.
Package Outline Drawings
ACPL-3130 Outline Drawing (Standard DIP Package / 300mil DIP)
7.62 ± 0.25
(0.300 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
8
TYPE NUMBER
7
6
5
6.35 ± 0.25
(0.250 ± 0.010)
OPTION CODE*
DATE CODE
A XXXXZ
YYWW
1
2
3
4
1.78 (0.070) MAX.
1.19 (0.047) MAX.
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
5 TYP.
3.56 ± 0.13
(0.140 ± 0.005)
4.70 (0.185) MAX.
0.51 (0.020) MIN.
2.92 (0.115) MIN.
1.080 ± 0.320
(0.043 ± 0.013)
DIMENSIONS IN MILLIMETERS AND (INCHES).
* MARKING CODE LETTER FOR OPTION NUMBERS.
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
0.65 (0.025) MAX.
2.54 ± 0.25
(0.100 ± 0.010)
NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.
ACPL-3130 Gull Wing Surface Mount Option 300 Outline Drawing
LAND PATTERN RECOMMENDATION
9.65 ± 0.25
(0.380 ± 0.010)
8
7
6
1.016 (0.040)
5
6.350 ± 0.25
(0.250 ± 0.010)
1
2
3
10.9 (0.430)
4
1.27 (0.050)
1.19
(0.047)
MAX.
1.780
(0.070)
MAX.
9.65 ± 0.25
(0.380 ± 0.010)
7.62 ± 0.25
(0.300 ± 0.010)
3.56 ± 0.13
(0.140 ± 0.005)
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.25
(0.025 ± 0.010)
0.635 ± 0.130
2.54
(0.025 ± 0.005)
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
2.0 (0.080)
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
12 ˚ NOM.
ACPL-J313 Outline Drawing (300mil DIP)
7.62 ± 0.25
(0.300 ± 0.010)
9.80 ± 0.25
(0.386 ± 0.010)
8
TYPE NUMBER
7
6
5
6.35 ± 0.25
(0.250 ± 0.010)
DATE CODE
A XXXX
YYWW
1
2
3
4
1.78 (0.070) MAX.
1.19 (0.047) MAX.
5 TYP.
3.56 ± 0.13
(0.140 ± 0.005)
4.70 (0.185) MAX.
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
0.51 (0.020) MIN.
2.92 (0.115) MIN.
1.080 ± 0.320
(0.043 ± 0.013)
DIMENSIONS IN MILLIMETERS AND (INCHES).
OPTION NUMBERS 300 AND 500 NOT MARKED.
0.65 (0.025) MAX.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
2.54 ± 0.25
(0.100 ± 0.010)
ACPL-J313 Gull Wing Surface Mount Option 300 Outline Drawing
LAND PATTERN RECOMMENDATION
9.80 ± 0.25
(0.386 ± 0.010)
8
7
6
1.016 (0.040)
5
6.350 ± 0.25
(0.250 ± 0.010)
1
2
3
10.9 (0.430)
4
1.27 (0.050)
1.19
(0.047)
MAX.
1.780
(0.070)
MAX.
9.65 ± 0.25
(0.380 ± 0.010)
7.62 ± 0.25
(0.300 ± 0.010)
3.56 ± 0.13
(0.140 ± 0.005)
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.25
(0.025 ± 0.010)
0.635 ± 0.130
2.54
(0.025 ± 0.005)
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.
2.0 (0.080)
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
12 ˚ NOM.
ACNW3130 Outline Drawing (8-Pin Wide Body Package / 400mil DIP)
11.00 MAX.
(0.433)
11.15 ± 0.15
(0.442 ± 0.006)
8
7
6
9.00 ± 0.15
(0.354 ± 0.006)
5
TYPE NUMBER
A
ACNWXXXX
DATE CODE
YYWW
1
2
3
4
10.16 (0.400)
TYP.
1.55
(0.061)
MAX.
7 TYP.
+ 0.076
0.254 - 0.0051
+ 0.003)
(0.010 - 0.002)
5.10 MAX.
(0.201)
3.10 (0.122)
3.90 (0.154)
0.51 (0.021) MIN.
2.54 (0.100)
TYP.
1.78 ± 0.15
(0.070 ± 0.006)
DIMENSIONS IN MILLIMETERS (INCHES).
0.40 (0.016)
0.56 (0.022)
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
ACNW3130 Gull Wing Surface Mount Option 300 Outline Drawing
11.15 ± 0.15
(0.442 ± 0.006)
8
7
6
LAND PATTERN RECOMMENDATION
5
9.00 ± 0.15
(0.354 ± 0.006)
1
2
3
13.56
(0.534)
4
1.3
(0.051)
2.29
(0.09)
12.30 ± 0.30
(0.484 ± 0.012)
1.55
(0.061)
MAX.
11.00 MAX.
(0.433)
4.00 MAX.
(0.158)
1.78 ± 0.15
(0.070 ± 0.006)
2.54
(0.100)
BSC
0.75 ± 0.25
(0.030 ± 0.010)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
1.00 ± 0.15
(0.039 ± 0.006)
+ 0.076
0.254 - 0.0051
+ 0.003)
(0.010 - 0.002)
7 NOM.
Recommended Solder Reflow Temperature Profile
300
PREHEATING RATE 3 °C + 1 °C/–0.5 °C/SEC.
REFLOW HEATING RATE 2.5 °C ± 0.5 °C/SEC.
200
PEAK
TEMP.
245 °C
PEAK
TEMP.
240 °C
TEMPERATURE (°C)
2.5 C ± 0.5 °C/SEC.
30
SEC.
160 °C
150 °C
140 °C
PEAK
TEMP.
230 °C
SOLDERING
TIME
200 °C
30
SEC.
3 °C + 1 °C/–0.5 °C
100
PREHEATING TIME
150 °C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
0
50
100
150
200
250
TIME (SECONDS)
NOTE: NON-HALIDE FLUX SHOULD BE USED.
Recommended Pb-Free IR Profile
tp
Tp
TEMPERATURE
TL
Tsmax
* 260 +0/-5 °C
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
15 SEC.
217 °C
150 - 200 °C
RAMP-UP
3 °C/SEC. MAX.
RAMP-DOWN
6 °C/SEC. MAX.
Tsmin
ts
PREHEAT
60 to 180 SEC.
25
tL
60 to 150 SEC.
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C
NOTE: NON-HALIDE FLUX SHOULD BE USED.
* RECOMMENDED PEAK TEMPERATURE FOR WIDEBODY 400mils PACKAGE TO BE 245 °C
Regulatory Information
The ACPL-3130/J313 and ACNW3130 are pending approval by the following organizations:
IEC/EN/DIN EN 60747-5-2 (ACPL-3130 Option 060
only, ACPL-J313 and ACNW3130)
Approval under:
IEC 60747-5-2 :1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01
UL
Approval under UL 1577, component recognition
program, File E55361.
CSA
Approval under CSA Component Acceptance Notice #5,
File CA 88324.
Table 1. IEC/EN/DIN EN 60747-5-2 Insulation Characteristics*
Description
Symbol
ACPL-3130
Option 060
ACPL-J313
ACNW3130
I – IV
I – IV
I – III
I – IV
I – IV
I – III
I – III
I – IV
I – IV
I – IV
I – IV
I – III
55/100/21
55/100/21
55/100/21
2
2
2
VIORM
630
891
1414
Vpeak
Input to Output Test Voltage, Method b* VIORM x 1.875=VPR,
100% Production Test with tm=1 sec, Partial discharge < 5 pC
VPR
1181
1670
2652
Vpeak
Input to Output Test Voltage, Method a* VIORM x 1.5=VPR,
Type and Sample Test, tm=60 sec, Partial discharge < 5 pC
VPR
945
1336
2121
Vpeak
VIOTM
6000
6000
8000
Vpeak
TS
IS, INPUT
PS, OUTPUT
175
230
600
175
400
600
150
400
700
°C
mA
mW
RS
>109
>109
>109
W
Installation classification per DIN VDE 0110/1.89, Table 1
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for rated mains voltage ≤������
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Vrms
for rated mains voltage ≤������
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Vrms
for rated mains voltage ≤������
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Vrms
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Vrms
Climatic Classification
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Highest Allowable Overvoltage
(Transient Overvoltage tini = 10 sec)
Safety-limiting values – maximum values allowed in the event of a
failure, also see Figure 41 and 42.
Case Temperature
Input Current
Output Power
Insulation Resistance at TS, VIO = 500 V
Unit
* Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/DIN
EN 60747-5-2) for a detailed description of Method a and Method b partial discharge test profiles.
Note: These optocouplers are suitable for “safe electrical isolation” only within the safety limit data. Maintenance of the safety data shall be ensured by
means of protective circuits. Surface mount classification is Class A in accordance with CECC 00802.
Table 2. Insulation and Safety Related Specifications
Parameter
Symbol
ACPL-3130
ACPL-J313
ACNW3130
Units
Conditions
Minimum External Air
Gap (Clearance)
L(101)
7.1
7.4
9.6
mm
Measured from input terminals to output
terminals, shortest distance through air.
Minimum External
Tracking (Creepage)
L(102)
7.4
8.0
10.0
mm
Measured from input terminals to output
terminals, shortest distance path along body.
0.08
0.5
1.0
mm
Through insulation distance conductor to
conductor, usually the straight line distance
thickness between the emitter and detector.
> 175
> 175
> 200
V
DIN IEC 112/VDE 0303 Part 1
IIIa
IIIa
IIIa
Minimum Internal
Plastic Gap (Internal
Clearance)
Tracking Resistance
(Comparative Tracking
Index)
Isolation Group
CTI
Material Group (DIN VDE 0110, 1/89, Table 1)
All Avago data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting
point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum
creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance path along
the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. There are recommended techniques
such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances
will also change depending on factors such as pollution degree and insulation level.
Table 3. Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
-55
125
°C
Operating Temperature
TA
-40
100
°C
Average Input Current
IF(AVG)
25
mA
Peak Transient Input Current
( 5 V
9, 17, 25
ACPL-J313
1.0
5.0
mA
IO = 0 mA, VO > 5 V
10, 18, 25
2.3
8.0
mA
IO = 0 mA, VO > 5 V
11, 17, 25
V
IO = 0 mA, VO > 5 V
0.5
VCC-4
ACNW3130
Input Reverse
Breakdown Voltage
BVR
UVLO Hysteresis
Typ.
Max.
2.0
2.0
DVF/DTA
UVLO Threshold
Min.
2.0
Temperature
Coefficient of
Input Forward
Voltage
Input Capacitance
Device
CIN
VCC-3
0.8
2
5, 6, 22
2
ACPL-3130
1.2
1.5
1.8
V
IF = 10 mA
19
ACPL-J313
1.2
1.6
1.95
V
IF = 10 mA
20
ACNW3130
1.2
1.6
1.95
V
IF = 10 mA
20
ACPL-3130
-1.6
mV/°C
IF = 10 mA
ACPL-J313
-1.3
mV/°C
IF = 10 mA
ACNW3130
-1.3
mV/°C
IF = 10 mA
ACPL-3130
5
V
IR = 10 µA
ACPL-J313
3
V
IR = 100 µA
ACNW3130
3
V
IR = 100 µA
ACPL-3130
60
pF
f = 1 MHz, VF = 0 V
ACPL-J313
70
pF
f = 1 MHz, VF = 0 V
ACNW3130
70
pF
f = 1 MHz, VF = 0 V
VUVLO+
11.0
12.3
13.5
V
IF = 10 mA, VO > 5 V
26, 38
VUVLO–
9.5
10.7
12.0
V
IF = 10 mA, VO > 5 V
26, 38
V
IF = 10 mA, VO > 5 V
26, 38
UVLOHYS
1.6
5
6, 7
Table 6. Switching Specifications (AC)
Over recommended operating conditions (TA = -40 to 100°C, for ACPL-3130,ACPL-J313 IF(ON) = 7 to 16mA, for ACNW3130
IF(ON) = 10 to 16mA, VF(OFF) = -3.6 to 0.8 V, VCC = 15 to 30 V, VEE = Ground) unless otherwise specified. All typical values at
TA = 25°C and VCC - VEE = 30 V, unless otherwise noted.
Parameter
Symbol
Min.
Typ.
Max.
Units Test Conditions
Propagation Delay Time
to High Output Level
tPLH
0.10
0.30
0.50
µs
Propagation Delay Time
to Low Output Level
tPHL
0.10
0.30
0.50
µs
Pulse Width Distortion
PWD
0.3
µs
Propagation Delay
Difference Between Any
Two Parts or Channels
(tPHL – tPLH)
0.35
µs
39, 40
27
Rg = 10 W,
Cg = 10 nF,
f = 10 kHz,
Duty Cycle = 50%
Fig.
Note
12,13,
14, 15,
16, 27
16
17
PDD
-0.35
Rise Time
tR
0.1
µs
Fall Time
tF
0.1
µs
UVLO Turn On Delay
tUVLO ON
0.8
µs
IF = 10 mA, VO > 5 V
12
26
UVLO Turn Off Delay
tUVLO OFF
0.6
µs
IF = 10 mA, VO > 5 V
26
Output High Level
Common Mode
Transient Immunity
|CMH|
40
50
kV/
µs
TA = 25°C,
IF = 10 to 16 mA,
VCM = 1500 V, VCC = 30 V
27
13, 14
Output Low Level
Common Mode
Transient Immunity
|CML|
40
50
kV/
µs
TA = 25°C, VF = 0 V,
VCM = 1500 V
VCC = 30 V
27
13, 15
Table 7. Package Characteristics
Over recommended temperature (TA = -40 to 100°C) unless otherwise specified. All typicals at TA = 25°C.
Parameter
Symbol
Device
Min.
Input-Output
Momentary
Withstand Voltage**
VISO
ACPL-3130
Resistance
(Input-Output)
RI-O
Typ.
Max.
Units
Test Conditions
3750
Vrms
8, 11
ACPL-J313
3750
Vrms
ACNW3130
5000
Vrms
RH < 50%,
t = 1 min.,
TA = 25°C
11
ACPL-3130
1012
W
VI-O = 500 V
ACPL-J313
1012
W
VI-O = 500 V
1013
W
VI-O = 500 V,
TA = 25°C
W
VI-O = 500 V,
TA = 100°C
ACNW3130
1012
1011
Capacitance
(Input-Output)
CI-O
LED-to-Case
Thermal Resistance
qLC
467
LED-to-Detector
Thermal Resistance
qLD
442
Detector-to-Case
Thermal Resistance
qDC
126
Fig.
9, 11
10, 11
ACPL-3130
0.6
pF
Freq=1 MHz
ACPL-J313
0.8
pF
Freq=1 MHz
ACNW3130
0.5
pF
Freq=1 MHz
°C/W
°C/W
Thermocouple
32
located at center
underside of package 32
°C/W
32
0.6
Note
** The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Avago Application
Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.”
10
-1
-2
-3
-4
-40 -20
0
20
40
60
80
100
1.6
1.4
1.2
1.0
-40 -20
20
40
60
80
100
Figure 2. IOH vs. Temperature.
I OL - OUTPUT LOW CURRENT - A
0.15
0.10
0.05
-20
0
20
40
60
T A - TEMPERATURE - °C
Figure 4. VOL vs. Temperature.
80
100
100 °C
25 °C
-40 °C
-2
-3
-4
I F = 7 to 16 mA
V CC = 15 to 30 V
V EE = 0 V
-5
-6
0
2
1
-20
0
20
40
60
T A - TEMPERATURE - °C
Figure 5. IOL vs. Temperature.
0.5
1.0
1.5
2.0
2.5
I OH - OUTPUT HIGH CURRENT - A
4
V F (OFF) = -3.0 TO 0.8 V
V OUT = 2.5 V
V CC = 15 TO 30 V
V EE = 0 V
3
0
-40
-1
Figure 3. VOH vs. IOH.
4
V F (OFF) = -3.0 TO 0.8 V
I OUT = 100 mA
V CC = 15 TO 30 V
V EE = 0 V
0.20
0
-40
0
T A - TEMPERATURE - °C
0.25
V OL - OUTPUT LOW VOLTAGE - V
1.8
T A - TEMPERATURE - °C
Figure 1. VOH vs. Temperature.
11
I F = 7 to 16 mA
V OUT = (V CC - 4 V)
V CC = 15 to 30 V
V EE = 0 V
(V OH - V CC ) - OUTPUT HIGH VOLTAGE DROP - V
2.0
I F = 7 to 16 mA
I OUT = -100 mA
V CC = 15 to 30 V
V EE = 0 V
V OL - OUTPUT LOW VOLTAGE - V
0
I OH - OUTPUT HIGH CURRENT - A
(V OH - V CC ) - HIGH OUTPUT VOLTAGE DROP - V
Notes:
1. Derate linearly above 70° C free-air temperature at a rate of 0.3 mA/°C.
2. Maximum pulse width = 10 µs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak
minimum = 2.0 A. See Applications section for additional details on limiting IOH peak.
3. Derate linearly above 70° C free-air temperature at a rate of 4.8 mW/°C.
4. Derate linearly above 70° C free-air temperature at a rate of 5.4 mW/°C. The maximum LED junction temperature should not exceed 125°C.
5. Maximum pulse width = 50 µs, maximum duty cycle = 0.5%.
6. In this test VOH is measured with a dc load current. When driving capacitive loads VOH will approach VCC as IOH approaches zero amps.
7. Maximum pulse width = 1 ms, maximum duty cycle = 20%.
8. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥�������
�� 4500
������
Vrms for 1 second (leakage detection
current limit, II-O ��
≤�������
5
������
µA).
9. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥�������
�� 4500
������
Vrms for 1 second (leakage detection
current limit, II-O ��
≤�������
5
������
µA).
10. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥�������
�� 6000
������
Vrms for 1 second (leakage detection
current limit, II-O ��
≤�������
5
������
µA).
11. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
12. The difference between tPHL and tPLH between any two ACPL-3130, ACPL-J313 or ACNW3130 parts under the same test condition.
13. Pins 1 and 4 need to be connected to LED common.
14. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output
will remain in the high state (i.e., VO > 15.0 V).
15. Common mode transient immunity in a low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output
will remain in a low state (i.e., VO < 1.0 V).
16. This load condition approximates the gate load of a 1200 V/75A IGBT.
17. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH| for any given device.
80
100
V F(OFF) = -3.0 to 0.8 V
V CC = 15 to 30 V
V EE = 0 V
3
2
1
0
100 °C
25 °C
-40 °C
0
0.5
1.0
1.5
2.0
I OL - OUTPUT LOW CURRENT - A
Figure 6. VOL vs. IOL.
2.5
3.5
I CC - SUPPLY CURRENT - mA
3.0
2.5
V CC = 30 V
V EE = 0 V
I F = 10 mA for I CCH
I F = 0 mA for I CCL
1.5
-40 -20
0
20
40
60
80
3.0
2.5
1.5
100
I F = 10 mA for I CCH
I F = 0 mA for ICCL
T A = 25 °C
V EE = 0 V
2.0
15
T A - TEMPERATURE - °C
3
2
1
0
20
40
60
80
100
T A - TEMPERATURE - °C
Figure 10. IFLH vs. Temperature. (ACPL-J313)
400
300
200
100
T PLH
T PHL
6
8
10
12
14
I F - FORWARD LED CURRENT - mA
Figure 13. Propagation Delay vs. IF.
12
16
4
3
2
1
0
-40 -20
500
V CC = 15 TO 30 V
V EE = 0 V
OUTPUT = OPEN
4
3
2
1
0
-40
-20
0
20
40
60
80
400
80
100
T PLH
T PHL
20
40
60
T PLH
T PHL
200
15
25
20
30
Figure 12. Propagation Delay vs. VCC.
500
200
0
60
V CC - SUPPLY VOLTAGE - V
I F = 10 mA
V CC = 30 V, V EE = 0 V
Rg = 10 Ω , Cg = 10 nF
DUTY CYCLE = 50%
f = 10 kHz
-40 -20
40
300
100
100
300
100
20
I F = 10 mA
T A = 25 °C
Rg = 10 �
Cg = 10 nF
DUTY CYCLE = 50%
f = 10 kHz
T A - TEMPERATURE - ° C
400
0
Figure 9. IFLH vs. Temperature. (ACPL-3130)
5
500
V CC = 30 V, V EE = 0 V
Rg = 10 Ω, Cg = 10 nF
T A = 25 °C
DUTY CYCLE = 50%
f = 10 kHz
V CC = 15 TO 30 V
V EE = 0 V
OUTPUT = OPEN
T A - TEMPERATURE - °C
Figure 11. IFLH vs. Temperature. (ACNW3130)
T p - PROPAGATION DELAY - ns
T p - PROPAGATION DELAY - ns
500
I FLH - LOW TO HIGH CURRENT THRESHOLD - mA
I FLH - LOW TO HIGH CURRENT THRESHOLD - mA
V CC = 15 TO 30 V
V EE = 0 V
OUTPUT = OPEN
-20
30
Figure 8. ICC vs. VCC.
5
0
-40
25
V CC - SUPPLY VOLTAGE - V
Figure 7. ICC vs. Temperature.
4
20
5
T p - PROPAGATION DELAY - ns
2.0
I CCH
I CCL
T p - PROPAGATION DELAY - ns
I CC - SUPPLY CURRENT - mA
I CCH
I CCL
I FLH - LOW TO HIGH CURRENT THRESHOLD - mA
3.5
80
100
T A - TEMPERATURE - °C
Figure 14. Propagation Delay vs. Temperature.
V CC = 30 V, V EE = 0 V
T A = 25 °C
I F = 10 mA
Cg = 10 nF
DUTY CYCLE = 50%
f = 10 kHz
400
300
200
100
T PLH
T PHL
0
10
20
30
40
Rg - SERIES LOAD RESISTANCE - Ω
Figure 15. Propagation Delay vs. Rg.
50
400
300
200
100
30
35
25
30
20
15
10
5
T PLH
T PHL
0
20
40
60
80
V O - OUTPUT VOLTAGE - V
V CC = 30 V, V EE = 0 V
T A = 25 °C
I F = 10 mA
Rg = 10 �
DUTY CYCLE = 50%
f = 10 kHz
V O - OUTPUT VOLTAGE - V
T p - PROPAGATION DELAY - ns
500
0
100
0
1
Cg - LOAD CAPACITANCE - nF
IF
+
10
VF
-
1.0
0.1
0.01
0.001
1.10
1.20
1.30
1.40
1.50
3
+
VF
-
1.0
0.1
0.01
1.2
1.3
1.4
1.5
1.6
V F - FORWARD VOLTAGE - VOLTS
Figure 20. IF vs. VF. (ACPL-J313 / ACNW3130)
1
8
0.1 µF
2
+
−
7
I F = 7 to
16 mA
3
6
4
5
8
2
7
3
6
4
5
0.1 µF
I OH
I OL
+
2.5 V
+
-
4V
+ V CC = 15
− to 30 V
Figure 21. IOH Test Circuit.
1
15
10
V CC = 15
to 30 V
0
0
1
2
3
4
5
I F - FORWARD LED CURRENT - mA
IF
10
0.001
1.60
Figure 19. IF vs. VF. (ACPL-3130)
13
5
T A = 25 °C
100
V F - FORWARD VOLTAGE - VOLTS
Figure 22. IOL Test Circuit.
4
1000
T A = 25°C
100
2
Figure 17. Transfer Characteristics (ACPL-3130 /
ACNW3130)
I F - FORWARD CURRENT - mA
I F - FORWARD CURRENT - mA
1000
20
5
I F - FORWARD LED CURRENT - mA
Figure 16. Propagation Delay vs. Cg.
25
1.7
Figure 18. Transfer Characteristics (ACPL-J313)
8
1
0.1 µF
2
7
8
2
7
0.1 µF
V OH
I F = 7 to
16 mA
+ V CC = 15
Ð to 30 V
6
3
1
5
3
6
4
5
V OL
Figure 24. VOL Test Circuit.
Figure 23. VOH Test Circuit.
8
1
1
8
2
7
0.1 µF
2
0.1 µF
7
IF
3
6
4
5
VO > 5 V
+
-
V CC = 15
to 30 V
1
10 KHz
50% DUTY
CYCLE
3
6
4
5
VO > 5 V
8
0.1 µF
I F = 7 to 16 mA
500 Ω
I F = 10 mA
Figure 26. UVLO Test Circuit.
Figure 25. IFLH Test Circuit.
+
-
V CC = 15
to 30 V
+
-
100 mA
4
100 mA
2
+
-
7
IF
V CC = 15
to 30 V
tr
VO
3
6
90%
10 Ω
50%
V OUT
10 nF
4
tf
10%
5
t PLH
t PHL
Figure 27. tPLH, tPHL, tr, and tf Test Circuit and Waveforms.
V CM
IF
5V
+
-
1
∆t
0.1 µF
A
B
∆V
8
2
VO
6
4
5
+
-
V CC = 30 V
VO
Figure 28. CMR Test Circuit and Waveforms.
14
V OH
SWITCH AT A: I F = 10 mA
SWITCH AT B: I F = 0 mA
-
+
�t
∆t
VO
V CM = 1500 V
V CM
0V
7
3
=
V OL
+
-
V CC
Applications Information
Eliminating Negative IGBT Gate Drive (Discussion applies to
ACPL-3130, ACPL-J313, and ACNW3130)
To keep the IGBT firmly off, the ACPL-3130 has a very
low maximum VOL specification of 0.5 V. The ACPL-3130
realizes this very low VOL by using a DMOS transistor
with 1 W (typical) on resistance in its pull down circuit.
When the ACPL-3130 is in the low state, the IGBT gate is
shorted to the emitter by Rg + 1 W. Minimizing Rg and
the lead inductance from the ACPL-3130 to the IGBT gate
and emitter (possibly by mounting the ACPL-3130 on a
small PC board directly above the IGBT) can eliminate the
need for negative IGBT gate drive in many applications as
shown in Figure 29. Care should be taken with such a PC
board design to avoid routing the IGBT collector or emitter
traces close to the ACPL-3130 input as this can result in
unwanted coupling of transient signals into the ACPL3130 and degrade performance. (If the IGBT drain must
be routed near the ACPL-3130 input, then the LED should
be reverse-biased when in the off state, to prevent the
transient signals coupled from the IGBT drain from turning
on the ACPL-3130.)
+5 V
1
Selecting the Gate Resistor (Rg) to Minimize IGBT Switching
Losses. (Discussion applies to ACPL-3130, ACPL-J313 and
ACNW3130)
Step 1: Calculate Rg minimum from the IOL peak specification. The
IGBT and Rg in Figure 30 can be analyzed as a simple RC circuit
with a voltage supplied by the ACPL-3130.
Rg ≥
15 + 5 − 2
2.5
= 7.2Ω ∼
= 8Ω
=
The VOL value of 2 V in the previous equation is a
conservative value of VOL at the peak current of 2.5A (see
Figure 6). At lower Rg values the voltage supplied by the
ACPL-3130 is not an ideal voltage step. This results in
lower peak currents (more margin) than predicted by this
analysis. When negative gate drive is not used VEE in the
previous equation is equal to zero volts.
8
270 �
0.1 µF
CONTROL
INPUT
74XXX
OPEN
COLLECTOR
2
7
3
6
4
5
VCC − VEE − VOL
IOLPEAK
+
-
V CC = 18 V
+ HVDC
Rg
Q1
3-PHASE
AC
Q2
- HVDC
Figure 29. Recommended LED Drive and Application Circuit.
+5 V
1
270 Ω
CONTROL
INPUT
74XXX
OPEN
COLLECTOR
8
0.1 µF
2
7
3
6
+
-
Q1
3-PHASE
AC
Q2
- HVDC
V EE = -5 V
5
Figure 30. ACPL-3130 Typical Application Circuit with Negative IGBT Gate Drive.
15
+ HVDC
Rg
+
4
V CC = 15 V
Step 2: Check the ACPL-3130 Power Dissipation and Increase Rg if
Necessary. The ACPL-3130 total power dissipation (PT) is equal to
the sum of the emitter power (PE) and the output power (PO):
PT = PE + PO
PE = IF • VF • DutyCycle
PO = PO(BIAS) + PO(SWITCHING) = ICC • VCC + ESW (R g ; Q g )• f
PE Parameter
Description
IF
LED Current
VF
LED On Voltage
Duty Cycle
Maximum LED Duty Cycle
PO Parameter
Description
ICC
Supply Current
VCC
Positive Supply Voltage
VEE
Negative Supply Voltage
ESW(Rg,Qg)
Energy Dissipated in the ACPL-3130 for
each IGBT Switching Cycle (See Figure 31)
f
Switching Frequency
For the circuit in Figure 30 with IF (worst case) = 16 mA, Rg
PE = 16mA •� 1.8V•� 0.8 = 23mW
PO = 4.25mA •� 20V + 5.2µJ�•20kHz
= 85mW + 104mW
= 189mW
> 178mW(PO (MAX) @85°C = 250mW - 15°C•� 4.8mW/ °C)
The value of 4.25 mA for ICC in the previous equation was
obtained by derating the ICC max of 5 mA (which occurs at
-40°C) to ICC max at 85˚C (see Figure 7).
PO ( SWITCHING MAX ) = PO ( MAX ) - PO ( BIAS )
= 178mW - 85mW
= 93mW
PO ( SWITCHING MAX )
f
93mW
=
= 4.65µW
20kHz
ESW ( MAX ) =
16
Since PO for this case is greater than PO(MAX), Rg must be
increased to reduce the ACPL-3130 power dissipation.
For Qg = 500 nC, from Figure 31, a value of ESW = 4.65 µW
gives a Rg = 10.3 Ω.
Esw - ENERGY PER SWITCHING CYCLE - µJ
= 8 W, Max Duty Cycle = 80%, Qg = 500 nC, f = 20 kHz and
TA max = 85˚C:
14
Qg = 100 nC
Qg = 500 nC
12
Qg = 1000 nC
10
V CC = 19 V
V EE = -9 V
8
6
4
2
0
0
10
20
30
40
50
Rg - GATE RESISTANCE - Ω
Figure 31. Energy Dissipated in the ACPL-3130 for Each IGBT Switching
Cycle.
Thermal Model
(Discussion applies to ACPL-3130, ACPL-J313 and ACNW3130)
θ� LD = 442 °C/W
T JE
θDC = 126 °C/W
For example, given PE = 45 mW, PO = 250 mW, TA = 70°C
and qCA = 83°C/W:
TC
θCA = 83 °C/W*
TJE = PE • 339°C/W + PD•140°C/W + TA
= 45mW• 339°C/W + 250mW • 140°C/W + 70°C = 120°C
TA
TJE = LED junction temperature
TJD = detector IC junction temperature
TC = case temperature measured at the center of the
package bottom
qLC = LED-to-case thermal resistance
qLD = LED-to-detector thermal resistance
qDC = detector-to-case thermal resistance
qCA = case-to-ambient thermal resistance
*qCA will depend on the board design and the placement
of the part.
Figure 32. Thermal Model.
The steady state thermal model for the ACPL-3130 is
shown in Figure 32. The thermal resistance values given
in this model can be used to calculate the temperatures
at each node for a given operating condition. As shown
by the model, all heat generated flows through qCA which
raises the case temperature TC accordingly. The value of
qCA depends on the conditions of the board design and is,
therefore, determined by the designer. The value of qCA =
83°C/W was obtained from thermal measurements using a
2.5 x 2.5 inch PC board, with small traces (no ground plane),
a single ACPL-3130 soldered into the center of the board
and still air. The absolute maximum power dissipation
derating specifications assume a qCA value of 83°C/W.
From the thermal mode in Figure 32 the LED and detector
IC junction temperatures can be expressed as:
(
TJE = PE • (θLC || (θLD + θDC ) + θCA ) + PD •
TJD = PE •
17
(
TJE = PE • (256°C/W + θCA ) + PD • (57°C/W + θCA ) + TA
TJD = PE • (57°C/W + θCA ) + PD • (111°C/W + θCA ) + TA
T JD
θLC = 467 °C/W
Inserting the values for qLC and qDC shown in Figure 32
gives:
)
)
θLC• θDC
+ θCA + TA
θLC + θDC + θLD
θ LC• θ DC
+ θCA + PD • (θDC || (θLD + θLC ) + θCA ) + TA
θLC + θDC + θLD
TJD = PE •140°C/W + PD • 194°C/W + TA
= 45mW • 140°C/W + 250mW • 194°C/W + 70°C
TJE and TJD should be limited to 125°C based on the
board layout and part placement (qCA) specific to the
application
LED Drive Circuit Considerations for Ultra High CMR Performance. (Discussion applies to ACPL-3130, ACPL-J313,
and ACNW3130)
Without a detector shield, the dominant cause of
optocoupler CMR failure is capacitive coupling from the
input side of the optocoupler, through the package, to the
detector IC as shown in Figure 33. The ACPL-3130 improves
CMR performance by using a detector IC with an optically
transparent Faraday shield, which diverts the capacitively
coupled current away from the sensitive IC circuitry.
However, this shield does not eliminate the capacitive
coupling between the LED and optocoupler pins 5-8
as shown in Figure 34. This capacitive coupling causes
perturbations in the LED current during common mode
transients and becomes the major source of CMR failures
for a shielded optocoupler. The main design objective of a
high CMR LED drive circuit becomes keeping the LED in the
proper state (on or off ) during common mode transients.
For example, the recommended application circuit
(Figure 29), can achieve 40 kV/µs CMR while minimizing
component complexity.
Techniques to keep the LED in the proper state are discussed in the next two sections.
3
C LEDP
A high CMR LED drive circuit must keep the LED off (VF
≤ VF(OFF)) during common mode transients. For example,
during a -dVcm/dt transient in Figure 35, the current
flowing through CLEDP also flows through the RSAT and
VSAT of the logic gate. As long as the low state voltage
developed across the logic gate is less than VF(OFF), the LED
will remain off and no common mode failure will occur.
+5 V
8
1
+
V SAT
-
C LEDP
2
5
C LEDO1
8
C LEDP
7
0.1
µF
7
3
6
C LEDN
4
C LEDN
SHIELD
4
SHIELD
5
+ V CM
Figure 35. Equivalent Circuit for Figure 29 During Common Mode Transient.
The open collector drive circuit, shown in Figure 36,
cannot keep the LED off during a +dVcm/dt transient, since
all the current flowing through CLEDN must be supplied
by the LED, and it is not recommended for applications
requiring ultra high CMRL performance. Figure 37 is an
alternative drive circuit which, like the recommended
application circuit (Figure 29), does achieve ultra high CMR
performance by shunting the LED in the off state.
1
8
+5 V
5
2
Q1
3
C LEDP
C LEDN
7
6
I LEDN
4
SHIELD
5
Figure 36. Not Recommended Open Collector Drive Circuit.
18
¥¥¥
¥¥¥
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING
- dV CM /dt.
6
Figure 34. Optocoupler Input to Output Capacitance Model for Shielded
Optocouplers.
V CC = 18 V
Rg
C LEDO2
3
+
-
I LEDP
6
C LEDN
Figure 33. Optocoupler Input to Output Capacitance Model for Unshielded Optocouplers.
2
CMR with the LED Off (CMRL)
7
4
1
A high CMR LED drive circuit must keep the LED on during
common mode transients. This is achieved by overdriving
the LED current beyond the input threshold so that it is not
pulled below the threshold during a transient. A minimum
LED current of 10 mA provides adequate margin over the
maximum IFLH of 5 mA to achieve 40 kV/μs CMR.
8
1
2
CMR with the LED On (CMRH)
1
8
+5 V
C LEDP
2
3
7
6
C LEDN
4
5
SHIELD
Figure 37. Recommended LED Drive Circuit for Ultra-High CMR.
Under Voltage Lockout Feature. (Discussion applies to
ACPL-3130, ACPL-J313, and ACNW3130)
The ACPL-3130 contains an under voltage lockout (UVLO)
feature that is designed to protect the IGBT under fault
conditions which cause the ACPL-3130 supply voltage
(equivalent to the fully-charged IGBT gate voltage) to
drop below a level necessary to keep the IGBT in a low
resistance state. When the ACPL-3130 output is in the high
state and the supply voltage drops below the ACPL-3130
VUVLO– threshold (9.5 < VUVLO– < 12.0) the optocoupler
output will go into the low state with a typical delay, UVLO
Turn Off Delay, of 0.6 µs.
When the ACPL-3130 output is in the low state and the
supply voltage rises above the ACPL-3130 VUVLO+ threshold
(11.0 < VUVLO+ < 13.5) the optocoupler output will go into
the high state (assumes LED is “ON”) with a typical delay,
UVLO Turn On Delay of 0.8 µs.
V O - OUTPUT VOLTAGE - V
14
12
(12.3, 10.8)
10
(10.7, 9.2)
8
6
4
2
0
(10.7, 0.1)
0
5
10
(12.3, 0.1)
15
(V CC - V EE ) - SUPPLY VOLTAGE - V
Figure 38. Under Voltage Lock Out.
20
Dead Time and Propagation Delay Specifications. (Discussion applies to ACPL-3130, ACPL-J313, and ACNW3130)
The ACPL-3130 includes a Propagation Delay Difference
(PDD) specification intended to help designers minimize
“dead time” in their power inverter designs. Dead time
is the time period during which both the high and low
side power transistors (Q1 and Q2 in Figure 29) are off.
Any overlap in Q1 and Q2 conduction will result in large
currents flowing through the power devices between the
high and low voltage motor rails.
I LED1
V OUT1
V OUT2
I LED2
Q1 ON
Q1 OFF
Q2 ON
Q2 OFF
t PHL MAX
t PLH MIN
PDD* MAX = (t PHL - t PLH ) MAX = t PHL MAX - t PLH MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Figure 39. Minimum LED Skew for Zero Dead Time.
To minimize dead time in a given design, the turn on of
LED2 should be delayed (relative to the turn off of LED1)
so that under worst-case conditions, transistor Q1 has just
turned off when transistor Q2 turns on, as shown in Figure
35. The amount of delay necessary to achieve this condition
is equal to the maximum value of the propagation delay
difference specification, PDDMAX, which is specified to be
350 ns over the operating temperature range of -40°C to
100°C.
Delaying the LED signal by the maximum propagation
delay difference ensures that the minimum dead time is
zero, but it does not tell a designer what the maximum
dead time will be. The maximum dead time is equivalent
to the difference between the maximum and minimum
propagation delay difference specifications as shown in
Figure 40. The maximum dead time for the ACPL-3130 is
700 ns (= 350 ns - (-350 ns)) over an operating temperature
range of - 40°C to 100°C.
Note that the propagation delays used to calculate PDD
and dead time are taken at equal temperatures and test
conditions since the optocouplers under consideration
are typically mounted in close proximity to each other and
are switching identical IGBTs.
19
V OUT1
V OUT2
I LED2
Q1 ON
OUTPUT POWER - P S , INPUT CURRENT - I S
I LED1
Q1 OFF
Q2 ON
Q2 OFF
t PHL MIN
t PHL MAX
800
P S (mW)
I S (mA) FOR ACPL-3130
OPTION 060
I S (mA) FOR ACPL-J313
700
600
500
400
300
200
100
t PLH
0
0
25
MIN
t PLH MAX
PDD* MAX
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (t PHL MAX - t PHL MIN ) + (t PLH MAX - t PLH MIN )
= (t PHL MAX - t PLH MIN ) - (t PHL MIN - t PLH MAX )
= PDD* MAX - PDD* MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Figure 40. Waveforms for Dead Time.
75
100 125 150 175 200
Figure 41. Thermal Derating Curve, Dependence of Safety Limiting Value
with Case Temperature per IEC/EN/DIN EN 60747-5-2 for ACPL-3130 (option 060) and ACPL-J313.
OUTPUT POWER - P S , INPUT CURRENT - I S
(t PHL- t PLH ) MAX
50
T S - CASE TEMPERATURE - °C
1000
P S (mW)
I S (mA)
900
800
700
600
500
400
300
200
100
0
0
25
50
75
100
125
150
175
T S - CASE TEMPERATURE - °C
Figure 42. Thermal Derating Curve, Dependence of Safety Limiting Value
with Case Temperature per IEC/EN/DIN EN 60747-5-2 for ACNW3130.
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www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2005-2008 Avago Technologies, Limited. All rights reserved. Obsoletes AV01-0630EN
AV02-0156EN - June 18, 2008
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