ACPL-074L-500E

ACPL-071L and ACPL-074L Single-channel and Dual-channel High Speed 15 MBd CMOS optocoupler with Glitch-Free Power-Up Feature Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features The ACPL-071L (single-channel) and ACPL-074L (dualchannel) are 15 MBd CMOS optocouplers in SOIC-8 package. The optocouplers utilize the latest CMOS IC technology to achieve outstanding performance with very low power consumption. Basic building blocks of ACPL-071L and ACPL-074L are high speed LEDs and CMOS detector ICs. Each detector incorporates an integrated photodiode, a high speed transimpedance amplifier, and a voltage comparator with an output driver. • +3.3V and +5 V CMOS compatibility • 30 ns max. pulse width distortion • 40ns max. propagation delay (for 3.3V supply voltage) • 30 ns max. propagation delay skew • High speed: 15 MBd min • 10 kV/µs minimum common mode rejection • –40 to 105°C temperature range • Glitch-Free Power-Up Feature Applications • Safety and regulatory approvals: • Digital field bus isolation: - UL recognized: 3750 V rms for 1 min. per UL 1577 • CANBus, RS485, USB • Multiplexed data transmission - CSA component acceptance Notice #5 • Computer peripheral interface - IEC/EN/DIN EN 60747-5-5 • Microprocessor system interface • DC/DC converter Functional Diagram ACPL-074L ACPL-071L NC 1 8 VDD ANODE 2 7 NC 6 Vo CATHODE 3 NC 4 SHIELD 5 GND ANODE1 1 8 VDD 7 Vo1 CATHODE1 2 CATHODE2 3 6 Vo2 ANODE2 4 SHIELD TRUTH TABLE LED OFF ON VO, OUTPUT H L 5 GND A 0.1uF bypass capacitor must be connected between pins 5 and 8. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Ordering Information ACPL-071L/074L are UL Recognized with 3750 Vrms for 1 minute per UL1577. Option Part number RoHS Compliant Package -000E ACPL-071L -500E -060E ACPL-074L Surface Mount SO-8 X -000E X -500E X SO-8 X X 1500 per reel X 100 per tube X 1500 per reel 100 per tube X X X Quantity 100 per tube X X -560E IEC/EN/DIN EN 60747-5-5 X -560E -060E Tape & Reel X 1500 per reel X 100 per tube X 1500 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: ACPL-071L-500E to order product of Small Outline SO-8 package in Tape and Reel packaging in RoHS compliant. Example 2: ACPL-074L-000E to order product of Small Outline SO-8 package in tube packaging and RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Reflow Soldering Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used. Regulatory Information The ACPL-071L and ACPL-074L have been approved by the following organizations: UL CSA IEC/EN/DIN EN 60747-5-5 2 Recognized under UL 1577, component recognition program, File E55361. Approved under CSA Component Acceptance Notice #5, File CA88324. Package Dimensions ACPL-071L and ACPL-074L (Small Outline S0-8 Package) LAND PATTERN RECOMMENDATION 8 7 6 5 5.994 ± 0.203 (0.236 ± 0.008) 3.937 ± 0.127 (0.155 ± 0.005) PIN ONE 1 2 3 7.49 (0.295) 4 0.406 ± 0.076 (0.016 ± 0.003) 1.9 (0.075) 1.270 BSC (0.050) 0.64 (0.025) * 5.080 ± 0.127 (0.200 ± 0.005) 3.175 ± 0.127 (0.125 ± 0.005) 7 1.524 (0.060) 45 X 0.432 (0.017) 0~7 0.228 ± 0.025 (0.009 ± 0.001) 0.203 ± 0.102 (0.008 ± 0.004) * TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH) 5.207 ± 0.254 (0.205 ± 0.010) 0.305 MIN. (0.012) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX. OPTION NUMBER 500 NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX. Package Marking ACPL-071L and ACPL-074L (Small Outline S0-8 Package) Device Part Number Lead Free Pin 1 Dot 3 NNNN Z YYWW EEE • Test Rating Code Date Code Lot ID Insulation and Safety Related Specifications Parameter Symbol Value Units Conditions Minimum External Air Gap (Clearance) L(I01) 4.9 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (Creepage) L(I02) 4.8 mm Measured from input terminals to output terminals, shortest distance path along body. Minimum Internal Plastic Gap (Internal Clearance) 0.08 mm Insulation thickness between emitter and detector; also known as distance through insulation. Tracking Resistance CTI (Comparative Tracking Index) ≥175 Volts DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) All Avago Technologies data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. There are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level. 4 IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* Description Symbol Option 060 Installation classification per DIN VDE 0110, Table 1 for rated mains voltage ≤ 150 Vrms for rated mains voltage ≤ 300 Vrms for rated mains voltage ≤ 600 Vrms I – IV I – IV I – III Climatic Classification 40/85/21 Pollution Degree (DIN VDE 0110/39) 2 Unit Maximum Working Insulation Voltage VIORM 567 Vpeak Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC VPR 1063 Vpeak Input to Output Test Voltage, Method a* VIORM x 1.6 = VPR, Type and Sample Test, tm=10 sec, Partial discharge < 5 pC VPR 907 Vpeak Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) VIOTM 6000 Vpeak Safety-limiting values – maximum values allowed in the event of a failure. Case Temperature Input Current Output Power TS IS, INPUT PS, OUTPUT 150 150 600 °C mA mW Insulation Resistance at TS, VIO = 500 V RS ≥109 Ω Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature TS –55 +125 °C Ambient Operating Temperature TA –40 +105 °C Supply Voltages VDD 0 6.0 Volts Output Voltage VO –0.5 VDD +0.5 Volts Average Forward Input Current IF - 20.0 mA Average Output Current Io - 10.0 mA Input Power Dissipation PI 35 mW 100 mW Output Power Dissipation PO Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane Solder Reflow Temperature Profile See Reflow Soldering Profile Recommended Operating Conditions Parameter Symbol Min. Max. Units Ambient Operating Temperature TA –40 +105 °C Supply Voltages VDD 4.5 5.5 V 3.0 3.6 V Input Current (ON) IF 12 18 mA Supply Voltage Slew Rate[1] SR 0.5 500 V/ms 5 Electrical Specifications Over recommended temperature (TA = –40°C to +105°C), 3.0V ≤ VDD ≤ 3.6V and 4.5 V ≤ VDD ≤ 5.5 V. All typical specifications are at TA=+25°C, VDD= +3.3V. Parameter Symbol Input Forward Voltage Input Reverse Breakdown Voltage Part Number Min. Typ. Max. Units Test Conditions VF 1.3 1.5 1.8 V IF = 14mA BVR 5.0 V IR = 10 µA Logic High Output Voltage VOH VDD-1 VDD-0.3 V IF = 0, IO = -4 mA, VDD=3.3V VDD-1 VDD-0.2 V IF = 0, IO = -4 mA, VDD=5V Logic Low Output Voltage VOL Input Threshold Current ITH Logic Low Output Supply Current IDDL Logic Low Output Supply Current IDDH 0.35 0.8 V IF = 14mA, IO =4mA, VDD=3.3V 0.2 0.8 V IF = 14mA, IO = 4mA, VDD=5V 4.5 8.8 mA IOL = 20 µA ACPL-071L 4.1 6.0 mA IF = 14 mA ACPL-074L 8.3 12.0 mA IF = 14 mA ACPL-071L 3.8 6.0 mA IF = 0 ACPL-074L 7.6 12.0 mA IF = 0 Switching Specifications Over recommended temperature (TA = –40°C to +105°C), 3.0V ≤ VDD ≤ 3.6V and 4.5 V ≤ VDD ≤ 5.5 V. All typical specifications are at TA=+25°C, VDD = +3.3V. Parameter Symbol Propagation Delay Time to Logic Low Output[2] tPHL Propagation Delay Time to Logic High Output[2] Min. tPLH Typ. Max. Units Test Conditions 29 40 ns IF = 14mA, CL= 15pF, VDD=3.3V CMOS Signal Levels 50 ns IF = 14mA, CL= 15pF, VDD=5V CMOS Signal Levels 40 ns IF = 14mA, CL= 15pF, VDD=3.3V, CMOS Signal Levels 50 ns IF = 14mA, CL= 15pF, VDD=5V, CMOS Signal Levels 22 Pulse Width tPW 66.7 Pulse Width Distortion[3] |PWD | 0 ns 7 25 ns IF = 14mA, CL= 15pF, VDD=3.3V, CMOS Signal Levels 30 ns IF = 14mA, CL= 15pF, VDD=5V, CMOS Signal Levels 30 ns IF = 14mA, CL= 15pF CMOS Signal Levels Propagation Delay Skew[4] tPSK Output Rise Time (10% – 90%) tR 20 ns IF = 14mA, CL= 15pF CMOS Signal Levels Output Fall Time (90% - 10%) tF 25 ns IF = 14mA, CL= 15pF CMOS Signal Levels Common Mode Transient Immunity at Logic High Output[5] | CMH | 10 15 kV/µs VCM = 1000 V, TA = 25°C, IF = 0 mA Common Mode Transient Immunity at Logic Low Output[6] | CML | 10 15 kV/µs VCM = 1000 V, TA = 25°C, IF = 14 mA 6 Package Characteristics All Typical at TA = 25°C. Parameter Symbol Input-Output Insulation II-O Input-Output Momentary Withstand Voltage VISO Input-Output Resistance R I-O Input-Output Capacitance C I-O Min. Typ. Max. Units Test Conditions 1.0 µA 45% RH, t = 5 s VI-O = 3 kV DC, TA = 25°C Vrms RH ≤ 50%, t = 1 min., TA = 25°C 10 12 W V I-O = 500 V dc 0.6 pF f = 1 MHz, TA = 25°C 3750 Notes: 1. Slew rate of supply voltage ramping is recommended to ensure no glitch more than 1V to appear at the output pin. 2. tPHL propagation delay is measured from the 50% level on the rising edge of the input pulse to the 50% level of the falling edge of the VO signal. tPLH propagation delay is measured from the 50% level on the falling edge of the input pulse to the 50% level of the rising edge of the VO signal. 3. PWD is defined as |tPHL - tPLH|. 4. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the recommended operating conditions. 5. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state. 6. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state. 6 IF -FORWARD CURRENT-mA 100 TA=25°C VF 10 Ith -INPUT THRESHOLD CURRENT-mA IF 1 0.1 0.01 0.001 1.1 1.2 1.3 1.4 1.5 V F -FORWARD VOLTAGE-V IDDH-LOGIC HIGH OUTPUT SUPPLY CURRENT -mA Figure 1. Typical input diode forward characteristic. 10 8 6 4 0 VDD=5.0V VDD=3.3V -40 -20 0 20 40 60 T A -TEMPERATURE-o C 80 100 Figure 3. Typical logic high O/P supply current vs. temperature for ACPL-074L. 7 4 3 I oL =20uA 2 5V 3.3V 1 -40 -20 0 20 40 60 TA -TEMPERATURE-o C 80 100 120 Figure 2. Typical input threshold current vs. temperature. 12 2 5 0 1.6 IDDl -LOGIC LOW OUTPUT SUPPLY CURRENT-mA 1000 12 10 8 6 4 VDD=5.0V VDD=3.3V 2 0 -40 -20 0 20 40 60 T A -TEMPERATURE-oC 80 100 Figure 4. Typical logic low O/P supply current vs. temperature for ACPL-074L. TPHL CH1 TPLH CH2 TPLH CH1 PWD CH2 9 10 11 12 13 14 IF – PULSE INPUT CURRENT – mA 15 16 Figure 5. Typical switching speed vs. pulse input current at 5V supply voltage. V F -FORWARD VOLTAGE-V TPHL CH1 35 30 25 20 15 10 5 0 TPHL CH2 TPLH CH2 TPLH CH1 PWD CH1 PWD CH2 VDD=3.3V TA=25°C 6 7 8 9 10 11 12 13 14 IF – PULSE INPUT CURRENT – mA 15 16 Figure 6. Typical switching speed vs. pulse input current at 3.3V supply voltage. Bypassing and PC Board Layout 1.6 The ACPL-071L and ACPL-074L optocouplers are extremely easy to use. ACPL-071L and ACPL-074L provide CMOS logic output due to the high-speed CMOS IC technology used. 1.55 1.5 The external components required for proper operation are the input limiting resistor and the output bypass capacitor. Capacitor values should be between 0.01 µF and 0.1 µF. 1.45 1.4 -20 0 20 40 60 TA -TEMPERATURE-oC 80 100 Figure 7 Typical VF vs. temperature. 8 1 GND1 3 7 NC 6 5 4 C VDD VO GND2 ACPL-071L C = 0.01mF to 0.1mF Figure 8. Recommended printed circuit board layout For each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm. IF1 1 8 GND 1 2 7 GND 1 3 IF2 4 XXX YWW 2 XXX YWW IF 8 50 45 40 Application Information 1.65 1.35 -40 tp– PROPAGATION DELAY; PWD-PULSE WIDTH DISTORTION – ns tp – PROPAGATION DELAY; PWD-PULSE WIDTH DISTORTION – ns 50 45 40 35 TPHL CH2 30 25 20 15 PWD CH1 10 VDD=5V 5 TA=25°C 0 6 7 8 VDD VO1 VO2 6 5 ACPL-074L C GND 2 Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from low to high (tPLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (tPHL) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see Figure 9). Pulse-width distortion (PWD) results when tPLH and tPHL differ in value. PWD is defined as the difference between tPLH and tPHL and often PWD is defined as the difference between tPLH and tPHL and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20-30% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS232, RS422, T-1, etc.). Propagation delay skew, tPSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, IF either tPLH or tPHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same supply voltage, output load, and operating temperature). As illustrated in Figure 10, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, tPSK is the difference between the shortest propagation delay, either tPLH or tPHL, and the longest propagation delay, either tPLH or tPHL. As mentioned earlier, tPSK can determine the maximum parallel data transmission rate. Figure 10 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 10 shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tPSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. DATA 50% INPUTS 50%, CMOS VO CLOCK tPSK IF 50% DATA OUTPUTS VO Figure 9. Propagation delay and skew waveform 9 50%, CMOS tPSK CLOCK tPSK Figure 10. Parallel data transmission example Powering Sequence VDD needs to achieve a minimum level of 3.0V before powering up the output connecting component. Input Limiting Resistors ACPL-071L and ACPL-074L are direct current driven (Figure 8), and thus eliminate the need for input power supply. To limit the amount of current flowing through the LED, it is recommended that a 210ohm resistor is connected in series with anode of LED (i.e. Pin 2 for ACPL-071L and Pin 1 and 4 for ACPL-074L) at 5V input signal. At 3.3V input signal, it is recommended to connect 80ohm resistor in series with anode of LED. t p - PROPAGATION DELAY; PWD-PULSE WIDTH DISTORTION -ns The recommended limiting resistors are based on the assumption that the driver output impedence is 50Ω (as shown in Figure 11). 35.00 tPHL 30.00 25.00 20.00 15.00 With peaking cap Without peaking cap tPLH tPHL tPLH 10.00 5.00 0.00 -40 |PWD| -20 0 20 40 60 TA - TEMPERATURE - o C (i) VDD=3.3V, Cpeak=100pF, Rlimit=80Ω 80 100 Speed Improvement A peaking capacitor can be placed across the input current limit resistor (Figure 11) to achieve enhanced speed performance. The value of the peaking cap is dependent to the rise and fall time of the input signal and supply voltages and LED input driving current (If ). Figure 12 shows significant improvement of propagation delay and pulse with distortion with added peak capacitor at driving current of 14mA and 3.3V or 5V power supply. Cpeak R drv =50Ω + VDD2 R limit V in GND1 GND 2 SHIELD Figure 11 Connection of peaking capacitor (Cpeak) in parallel of the input limiting resistor (Rllimit) to improve speed performance 30.00 tPHL 25.00 20.00 15.00 10.00 With peaking cap Without peaking cap tPHL 5.00 0.00 -40 tPLH tPLH |PWD| -20 0 20 40 60 TA - TEMPERATURE - o C (ii) VDD=5V, Cpeak=100pF, Rlimit=210Ω Figure 12. Improvement of tp and PWD with added 100pF peaking capacitor in parallel of input limiting resistor. 10 VO 0.1µF - t p - PROPAGATION DELAY; PWD-PULSE WIDTH DISTORTION -ns The tPSK specified optocouplers offer the advantages of guaranteed specifications for propagation delays, pulsewidth distortion and propagation delay skew over the recommended temperature, and power supply ranges. 80 100 Rlimit VCM A B V DD2 IF V O monitoring VCM 0.1µF note VO VCM (PEAK) 0V VDD SWITCH AT A: I F = 0 mA SWITCH AT B: I F = 14 mA GND 2 SHIELD Pulse Gen. Zo=50Ω + VO VO (min.) VO (max.) GND2 - Figure 13. Test circuit for common mode transient immunity and typical waveforms. Rtotal is the total resistance of the driver output impedence (which is assumed to be 50 Ω) and the limiting resistor (Rtotal=Rdrv+Rlimit) . For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2014 Avago Technologies. All rights reserved. AV02-0963EN - June 24, 2014 CM H CM L