ACPL-312T
Automotive IGBT Gate Drive Optocoupler
with R2Coupler™ Isolation and 2.5 Amp Output Current
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
The ACPL-312T device contains an AlGaAs LED. The LED
is optically coupled to an integrated circuit with a power
output stage. This automotive optocoupler is ideally suited for driving power IGBTs and MOSFETs used in automotive motor control inverter and DC-DC converters applications. The high operating voltage range of the output
stage provides the drive voltages required by gate controlled devices. The voltage and current supplied by these
optocouplers make them ideally suited for directly driving IGBTs with ratings up to 1200 V/100 A. For IGBTs with
higher ratings, the ACPL-312T series can be used to drive a
discrete power stage which drives the IGBT gate.
x 2.5 A maximum peak output current
Avago R2Coupler isolation products provide the reinforced insulation and reliability needed for critical in automotive and high temperature industrial applications.
x 500 ns maximum switching speeds
Functional Diagram
x Qualified to AEC-Q100 Test Guidelines
x 2.0 A minimum peak output current
x 25 kV/μs minimum Common Mode Rejection (CMR) at
VCM = 1500 V
x 0.5 V maximum low level output voltage (VOL) Eliminates need for negative gate drive
x ICC = 5 mA maximum supply current
x Under Voltage Lock-Out protection (UVLO) with
hysteresis
x Wide operating VCC range: 15 to 30 Volts
x Automotive temperature range:
-40°C to 125°C
x Safety Approval:
ACPL-312T-000E
UL Recognized 3750 Vrms for 1 min. (5kV for option
x20E available upon request).
N/ C 1
8 V CC
ANODE 2
7 VO
CATHODE 3
6 VO
Applications
5 V EE
x Automotive Motor/DC-DC Converter
N/C
4
SHIELD
CSA
IEC/EN/DIN EN 60747-5-2
x Automotive Isolated IGBT/MOSFET Gate Drive
x AC and Brushless DC Motor Drives
TRUTH TABLE
LED
OFF
ON
ON
ON
VCC - VEE
“POSITIVE GOING”
(i.e., TURN-ON)
VCC - VEE
“NEGATIVE GOING”
(i.e., TURN-OFF)
0 - 30 V
0 - 30 V
0 - 11 V
0 - 9.5 V
11 - 13.5 V
9.5 - 12 V
13.5 - 30 V
12 - 30 V
x Industrial Inverters Systems
x Switch mode power supplies
VO
LOW
LOW
TRANSITION
HIGH
A 0.1 μF bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
Part
Number
Options
RoHS Compliant
Package
-000E
DIP 8
-300E
DIP 8
Gullwing
ACPL-312T
-500E
Surface Mount
Gullwing
Tape & Reel
Quantity
50 per tube
X
X
X
X
50 per tube
X
1000 per reel
Note:- option x20E for UL1577 5000Vrms for 1minute will be offered upon request
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-312T-500E to order product of gullwing DIP-8 package in Tape and Reel packaging with RoHS compliant.
Example 2:
ACPL-312T-000E to order product of DIP-8 package in tube packaging with RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Package Outline Drawings
ACPL-312T-000E standard DIP8 package
7.62 ± 0.25
(0.300 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
TYPE NUMBER
8
7
6
5
1.19 (0.047) MAX.
2
3
6.35 ± 0.25
(0.250 ± 0.010)
DATE CODE
A 312T
YYWW
EE
1
OPTION CODE*
4
1.78 (0.070) MAX.
5° TYP.
3.56 ± 0.13
(0.140 ± 0.005)
4.70 (0.185) MAX.
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
0.51 (0.020) MIN.
2.92 (0.115) MIN.
1.080 ± 0.320
(0.043 ± 0.013)
2
0.65 (0.025) MAX.
2.54 ± 0.25
(0.100 ± 0.010)
DIMENSIONS IN MILLIMETERS AND (INCHES).
* MARKING CODE LETTER FOR OPTION NUMBERS.
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
Gull Wing Surface Mount Option 300E and 500E
LAND PATTERN RECOMMENDATION
9.65 ± 0.25
(0.380 ± 0.010)
8
6
7
Extended
Date Code
1.016 (0.040)
5
A 312T
YYWW
EE
1
3
2
6.350 ± 0.25
(0.250 ± 0.010)
10.9 (0.430)
4
1.27 (0.050)
9.65 ± 0.25
(0.380 ± 0.010)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
2.0 (0.080)
7.62 ± 0.25
(0.300 ± 0.010)
3.56 ± 0.13
(0.140 ± 0.005)
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.25
(0.025 ± 0.010)
0.635 ± 0.130
2.54
(0.025 ± 0.005)
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
12° NOM.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
Regulatory Information
Recommended Pb-Free IR Profile
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
TEMPERATURE
The ACPL-312T-000E is approved by the following organizations:
20-40 SEC.
260 +0/-5 °C
Tp
217 °C
TL
Tsmax
Tsmin
tp
RAMP-UP
3 °C/SEC. MAX.
RAMP-DOWN
6 °C/SEC. MAX.
150 - 200 °C
Recognized under UL 1577, component recognition
program up to VISO = 3750 VRMS
CSA
CSA Component Acceptance Notice #5, File CA88324.
ts
PREHEAT
60 to 180 SEC.
tL
60 to 150 SEC.
IEC/EN/DIN EN 60747-5-2
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884Teil 2):2003-01
25
t 25 °C to PEAK
TIME
Notes:
The time from 25 °C to peak temperature = 8 minutes max.
Tsmax = 200 °C, Tsmin = 150 °C
Non-halide flux should be used
3
UL
Insulation and Safety Related Specifications
Parameter
Symbol
Value
Units
Conditions
Minimum External Air Gap
(Clearance)
L(101)
7.1
mm
Measured from input terminals to output terminals, shortest
distance through air.
Minimum External Tracking
(Creepage)
L(102)
7.4
mm
Measured from input terminals to output terminals, shortest
distance path along body.
Minimum Internal Plastic Gap
(Internal Clearance)
0.08
mm
Through insulation distance conductor to conductor, usually the
straight line distance thickness between the emitter and detector.
Tracking Resistance
CTI
(Comparative Tracking Index)
>175
Volts
DIN IEC 112/VDE 0303 Part 1
Isolation Group
(DIN VDE0109)
IIIa
All Avago data sheets report the creepage and clearance
inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit
board, minimum creepage and clearance requirements
must be met as specified for individual equipment standards. For creepage, the shortest distance path along the
Material Group (DIN VDE 0110)
surface of a printed circuit board between the solder fillets
of the input and output leads must be considered. There
are recommended techniques such as grooves and ribs
which may be used on a printed circuit board to achieve
desired creepage and clearances. Creepage and clearance
distances will also change depending on factors such as
pollution degree and insulation level.
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics
Description
Symbol
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤150 V rms
for rated mains voltage ≤300 V rms
for rated mains voltage ≤3450V rms
for rated mains voltage ≤3600V rms
for rated mains voltage ≤1000V rms
ACPL-312T
Units
I-IV
I-IV
I-III
Climatic Classification
55/125/21
Pollution Degree (DIN VDE 0110/1.89)
2
Maximum Working Insulation Voltage
VIORM
630
VPEAK
Input to Output Test Voltage, Method b†
VIORM x 1.875 = VPR, 100% Production
Test tm = 1 sec, Partial Discharge < 5 pC
VPR
1181
VPEAK
Input to Output Test Voltage, Method a†
VIORM x 1.5 = VPR, 100% Type and Sample Test
tm = 60 sec, Partial Discharge < 5 pC
VPR
945
VPEAK
Highest Allowable Overvoltage†
(Transient Overvoltage, tini = 10 sec)
VIOTM
6000
VPEAK
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Thermal Derating curve, Figure 11.)
Case Temperature
Input Current
Output Power
Ts
Is, INPUT
Ps,OUTPUT
175
230
600
°C
mA
mW
Insulation Resistance at TS, V10 = 500 V
RIO
≥109
Ω
4
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
-55
125
°C
Operating Temperature
TA
-40
125
°C
Average Input Current
IF(AVG)
20
mA
Peak Transient Input Current
( 5 V
Threshold Input Voltage
High to Low
VFHL
0.8
Input Forward Voltage
VF
1.2
Temperature Coefficient of
Forward Voltage
ΔVF/ΔTA
Input Reverse Breakdown Voltage
BVR
Input Capacitance
CIN
UVLO Threshold
VUVLO+
11.0
12.3
VUVLO–
9.5
10.7
UVLO Hysteresis
V
1.5
1.95
IF = 10 mA
mV/°C
IF = 10 mA
V
IR = 10 μA
pF
f = 1 MHz, VF = 0 V
13.5
V
12.0
V
VO > 5 V,
IF = 10 mA
5.0
70
1.6
UVLOHYS
9
V
-1.6
9, 15,
21
16
22, 34
V
*All typical values at TA = 25°C and VCC - VEE = 30 V, unless otherwise noted.
AC Electrical Specifications
Over recommended operating conditions
(TA = -40 to 125°C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.6 to 0.8 V, VCC = 15 to 30 V, VEE = Ground) unless otherwise specified.
Parameter
Symbol
Min.
Typ.*
Max.
Units
Test Conditions
Propagation Delay Time to
High Output Level
tPLH
0.10
0.30
0.50
μs
Propagation Delay Time to
Low Output Level
tPHL
0.10
0.30
0.50
μs
Rg = 10 Ω, Cg = 10 nF, f = 10 10, 11,
kHz, Duty Cycle = 50%
12,13,
14, 23
Pulse Width Distortion
PWD
0.3
μs
Propagation Delay Difference
Between Any Two Parts
PDD
-0.35
(tPHL - tPLH)
0.35
μs
35, 36
Rise Time
Tr
0.1
μs
23
Fall Time
Tf
0.1
μs
UVLO Turn On Delay
tUVLO ON
0.8
μs
VO > 5 V, IF = 10 mA
UVLO Turn Off Delay
tUVLO OFF
0.6
μs
VO < 5 V, IF = 10 mA
Output High Level Common
Mode Transient Immunity
|CMH|
25
35
kV/μs
TA = 25°C, IF = 10 to 16 mA,
VCM = 1500 V, VCC = 30 V
Output Low Level Common
Mode Transient Immunity
|CML|
25
35
kV/μs
TA = 25°C, VCM = 1500 V, VF =
0 V, VCC = 30 V
*All typical values at TA = 25°C and VCC - VEE = 30 V, unless otherwise noted.
6
Fig.
Note
16
17
12
22
15
24
13, 14
13, 15
Package Characteristics
Parameter
Symbol
Min.
Typ.*
Input-Output Momentary
Withstand Voltage**
VISO
3750
Resistance (Input-Output)
RI-O
1012
Max.
Units
Test Conditions
Fig.
VRMS
RH < 50%, t = 1 min.
TA = 25°C
8, 11
Ω
VI-O = 500 VDC
11
18
Capacitance (Input-Output)
CI-O
0.8
pF
ƒ = 1 MHz
LED-to-Case Thermal
Resistance
TLC
467
°C/W
Thermocouple located at
28
center underside of package
LED-to-Detector Thermal
Resistance
TLD
442
°C/W
Detector-to-Case Thermal
Resistance
TDC
126
°C/W
Note
*All typicals at TA = 25°C.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage
rating. For the continuous voltage rating refers to your equipment level safety specification or Avago Application Note 1074 entitled “Optocoupler
Input-Output Endurance Voltage.”
Notes:
1. Derate linearly above 70°C free-air temperature at a rate of 0.0727 mA/°C. '
2. Maximum pulse width = 10 μs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak
minimum = 2.0 A. See Applications section for additional details on limiting IOH peak.
3. Derate linearly above 70°C free-air temperature at a rate of 5.0 mW/°C.
4. Derate linearly above 70°C free-air temperature at a rate of 5.0 mW/°C. The maximum LED junction temperature should not exceed 150°C.
5. Maximum pulse width = 50 μs, maximum duty cycle = 0.5%.
6. In this test VOH is measured with a dc load current. When driving capacitive loads VOH will approach VCC as IOH approaches zero amps.
7. Maximum pulse width = 1 ms, maximum duty cycle = 20%. 8. In accordance with UL1577, each optocoupler is proof tested by applying an
insulation test voltage ≥4500 Vrms for 1 second (leakage detection current limit, II-O ≤ 5 μA).
8. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥4500 Vrms for 1 second (leakage detection
current limit, II-O ≤ 5 μA).
9. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥6000 Vrms for 1 second (leakage detection
current limit, II-O ≤ 5 μA).
10. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
11. The difference between tPHL and tPLH between any two ACPL-312T parts under the same test condition.
12. Pins 1 and 4 need to be connected to LED common.
13. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output
will remain in the high state (i.e., VO > 15.0 V).
14. Common mode transient immunity in a low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output
will remain in a low state (i.e., VO < 1.0 V).
15. This load condition approximates the gate load of a 1200 V/75A IGBT.
16. Pulse Width Distortion (PWD) is defined as |tPHL-tPLH| for any given device.
7
2.00
IF = 7 to 16 mA
IOUT = -100 mA
V CC = 15 to 30 V
V EE = 0 V
-1
I OH – OUTPUT HIGH CURRENT – A
(VOH – V CC ) – HIGH OUTPUT VOLTAGE DROP – V
0
-2
-3
-40
0
20
40
60
80
T A – TEMPERATURE – °C
100
120
V OL – OUTPUT LOW VOLTAGE – V
(VOH – V CC ) – OUTPUT HIGH VOLTAGE DROP – V
-1
-2
-3
IF = 7 to 16 mA
V CC = 15 to 30 V
V EE = 0 V
-6
0.0
0.5
1.0
1.5
2.0
IOH – OUTPUT HIGH CURRENT – A
2.5
-40
-20
0
20 40
60 80
T A – TEMPERATURE – °C
100
120 140
0.20
0.15
V F (OFF) = -3.0 TO 0.8 V
IOUT = 100 mA
V CC = 15 TO 30 V
V EE = 0 V
0.10
0.05
0.00
3.0
-40
-20
0
20
40
60 80
T A – TEMPERATURE – °C
100
120 140
Figure 4. VOL vs. temperature.
3.00
4.50
V OL – OUTPUT LOW VOLTAGE – V
IOL – OUTPUT LOW CURRENT – A
1.75
0.25
125°C
-40°C
25°C
Figure 3. VOH vs. IOH.
2.50
2.00
1.50
V F (OFF) = -3.0 TO 0.8 V
V OUT = 2.5 V
V CC = 15 TO 30 V
V EE = 0 V
1.00
0.50
0.00
-40
-20
0
20
40
60 80
T A – TEMPERATURE – °C
Figure 5. IOL vs. temperature.
8
1.80
Figure 2. IOH vs. temperature.
0
-5
1.85
140
Figure 1. VOH vs. temperature.
-4
1.90
1.70
-20
IF = 7 to 16 mA
IOUT = -100 mA
V CC = 15 to 30 V
V EE = 0 V
1.95
100
120
140
25°C
-40°C
125°C
4.00
3.50
3.00
2.50
2.00
V F(OFF) = -3.0 to 0.8 V
V CC = 15 to 30 V
V EE = 0 V
1.50
1.00
0.50
0.00
0.0
Figure 6. VOL vs. IOL.
1.0
2.0
3.0
IOL – OUTPUT LOW CURRENT – A
4.0
2.8
Iccl
Icch
3.00
ICC – SUPPLY CURRENT – mA
ICC – SUPPLY CURRENT – mA
3.50
2.50
V CC = 30 V
V EE = 0 V
IF = 10 mA for I CCH
IF = 0 mA for I CCL
2.00
Iccl
Icch
2.6
IF = 10 mA for I CCH
IF = 0 mA for I CCL
T A = 25 °C V EE = 0 V
2.5
2.4
1.50
-40
-20
0
20 40
60 80
T A – TEMPERATURE – °C
100
120
15
140
20
25
V CC – SUPPLY VOLTAGE – V
1.20
500
Tplh
T p – PROPAGATION DELAY – ns
1.00
0.80
0.60
0.40
V CC = 15 TO 30 V
V EE = 0 V
OUTPUT = OPEN
0.20
0.00
Tphl
400
300
IF = 10 mA T A = 25 °C
Rg = 10 :
Cg = 10 nF
DUTY CYCLE = 50%
f = 10 kHz
200
100
-40
-20
0
20 40 60
80 100
T A – TEMPERATURE – °C
120
15
140
20
25
V CC – SUPPLY VOLTAGE – V
500
500
Tphl
Tp – PROPAGATION DELAY – ns
T p – PROPAGATION DELAY – ns
Tphl
Tplh
400
300
V CC = 30 V, V EE = 0 V
Rg = 10 : , Cg = 10 nF
T A = 25 °C
DUTY CYCLE = 50%
f = 10 kHz
200
100
6
8
10
12
14
IF – FORWARD LED CURRENT – mA
Figure 11. Propagation delay vs. IF.
30
Figure 10. Propagation delay vs. VCC.
Figure 9. IFLH vs. temperature.
9
30
Figure 8. ICC vs. VCC.
Figure 7. ICC vs. temperature.
IFLH – LOW TO HIGH CURRENT THRESHOLD – mA
2.7
Tplh
400
300
IF = 10 mA
V CC = 30 V, V EE = 0 V
Rg = 10 : , Cg = 10 nF
DUTY CYCLE = 50%
f = 10 kHz
200
100
16
-40
-20
0
20 40 60
80 100
T A – TEMPERATURE – °C
Figure 12. Propagation delay vs. temperature.
120
140
500
500
400
T p – PROPAGATION DELAY – ns
Tp – PROPAGATION DELAY – ns
Tphl
Tplh
300
V CC = 30 V, V EE = 0 V
T A = 25 °C I F = 10 mA
Cg = 10 nF
DUTY CYCLE = 50%
f = 10 kHz
200
100
0
10
20
30
40
Rg – SERIES LOAD RESISTANCE – :
Tplh
300
V CC = 30 V, V EE = 0 V
T A = 25 °C IF = 10 mA
Cg = 10 nF
DUTY CYCLE = 50%
f = 10 kHz
200
100
0
20
40
60
80
100
Cg – LOAD CAPACITANCE – nF
Figure 14. Propagation delay vs. Cg.
100
30
o
T A = 25 C
25
IF - FORWARD CURRENT - mA
V O – OUTPUT VOLTAGE – V
400
50
Figure 13. Propagation delay vs. Rg.
20
15
10
5
0
0
1
2
3
4
IF – FORWARD LED CURRENT – mA
Figure 15. Transfer characteristics.
10
Tphl
5
10
1
0.1
0.01
1.2
1.3
1.4
1.5
V F - Forward Voltage - VOLTS
Figure 16. Input current vs. forward voltage.
1.6
I F = 7 to
16 mA
1
8
0.1 μF
2
7
3
+
– 4V
V CC = 15
+
– to
30 V
6
1
8
0.1 μF
2
7
3
6
4
5
I OH
4
5
+ V CC = 15
– to 30 V
2.5 V +
–
Figure 18. IOL Test circuit.
Figure 17. IOH test circuit.
I F = 7 to
16 mA
I OL
1
8
0.1 μF
2
7
3
6
VOH
+ V CC =15
– to 30 V
1
8
0.1 μF
2
7
3
6
4
5
100 mA
+ V CC = 15
– to 30 V
VOL
100 mA
4
5
Figure 20. VOL Test circuit.
Figure 19. VOH Test circuit.
IF
1
8
0.1 μF
2
7
3
6
4
5
Figure 21. IFLH Test circuit.
11
I F = 10 mA
VO > 5 V
V CC = 15
+
– to
30 V
1
8
0.1 μF
2
7
3
6
4
5
Figure 22. UVLO test circuit.
V O > 5V
+
– V CC
1
8
0.1 μF
I F = 7 to 16 mA
10 KHz
50% DUTY
CYCLE
+ 500 :
–
2
V CC = 15
+ to
30 V
–
7
IF
tr
tf
VO
3
6
90%
10 :
4
50%
10%
V OUT
10 nF
5
t PLH
t PHL
Figure 23. tPLH, tPHL, tr, and tf test circuit and waveforms.
V CM
IF
5V +
–
1
8
2
7
0.1 μF
A
B
G V V CM
=
G t 't
0V
VO
3
6
4
5
+
–
V CC = 30 V
't
VO
SWITCH AT A: I F = 10 mA
VO
SWITCH AT B: I F = 0 mA
–
+
= 1500V
V CM
Figure 24. CMR test circuit and waveforms.
12
V OH
V OL
Applications Information
Eliminating Negative IGBT Gate Drive ACPL-312T
To keep the IGBT firmly off, the ACPL-312T has a very low
maximum VOL specification of 0.5 V. The ACPL-312T realizesthis very low VOL by using a DMOS transistor with 1 Ω
(typical) on resistance in its pull down circuit. When the
ACPL-312T is in the low state, the IGBT gate is shorted to
the emitter by Rg + 1 Ω. Minimizing Rg and the lead inductance from the ACPL-312T to the IGBT gate and emitter
(possibly by mounting the ACPL-312T on a small PC board
directly above the IGBT) can eliminate the need for nega-
tive IGBT gate drive in many applications as shown in Figure 25. Care should be taken with such a PC board design
to avoid routing the IGBT collector or emitter traces close
to the ACPL-312T input as this can result in unwanted coupling of transient signals into the ACPL-312T and degrade
performance. (If the IGBT drain must be routed near the
ACPL-312T input, then the LED should be reverse-biased
when in the off state, to prevent the transient signals coupled from the IGBT drain from turning on the ACPL-312T).
ACPL-312T
+5 V
8
0.1 μF
1
270 :
2
7
CONTROL
INPUT
3
6
CMOS
DRIVER
4
5
+
–
V CC = 18 V
+ HVDC
Rg
Q1
3-PHASE
AC
Q2
- HVDC
Figure 25. Recommended LED drive and application circuit.
Selecting the Gate Resistor (Rg) to Minimize IGBT Switching
Losses.
Step 1: Calculate Rg Minimum from the IOL Peak Specification. The IGBT and Rg in Figure 26 can be analyzed as
a simple RC circuit with a voltage supplied by the HCPL3120.
Rg ≥
=
(VCC −V EE − 2V )
(VCC −V EE −VOL )
=
I OLPEAK
I OLPEAK
(15 + 5 − 2)
2. 5 A
The VOL value of 2 V in the previous equation is a conservative value of VOL at the peak current of 2.5A (see Figure
6). At lower Rg values the voltage supplied by the ACPL312T is not an ideal voltage step. This results in lower peak
currents (more margin) than predicted by this analysis.
When negative gate drive is not used VEE in the previous
equation is equal to zero volts.
R g = 7. 2Ω # 8Ω
+5V
1
270:
2
8
0.1 μF
7
+
–
V CC = 15 V
+ HVDC
Rg
CONTROL
INPUT
3
6
CMOS
DRIVER
4
5
+
–
Figure 26. ACPL-312T typical application circuit with negative IGBT gate drive.
13
Q1
V EE = -5 V
3-PHASE
AC
Q2
- HVDC
Step 2: Check the ACPL-312T Power Dissipation and Increase Rg
if Necessary.
P0 Parameter
Description
The ACPL-312T total power dissipation (PT ) is equal to the
sum of the emitter power (PE) and the output power (PO):
ICC
Supply Current
VCC
Positive Supply Voltage
VEE
Energy Dissipated in the
ACPL-312T for each IGBT
Switching Cycle
(See Figure 27)
= PE + PO
PE
= IF .VF .Duty Cycle
PO
= PO(BIAS) + PO (SWITCHING)
= ICC.(VCC - VEE) + ESW(RG, QG).f
For the circuit in Figure 26 with IF (worst case) = 16 mA, Rg
= 8 Ω, Max Duty Cycle = 80%, Qg = 500 nC, f = 20 kHz and
TA max = 85C:
PE
= 16 mA.1.8 V.0.8 = 23 mW
PO
= 4.25 mA . 20 V + 5.2 μJ . 20 kHz
= 85 mW + 104 mW
= 189 mW
> 178 mW (PO(MAX) @ 85C
= 250 mW-15C*4.8 mW/C)
The value of 4.25 mA for ICC in the previous equation was
obtained by derating the ICC max of 5 mA (which occurs
at -40°C) to ICC max at 125C (see Figure 7). Since PO for
this case is greater than PO(MAX), Rg must be increased to
reduce the ACPL-312T power dissipation.
PO(SWITCHING MAX)
= PO(MAX) - PO(BIAS)
= 178 mW - 85 mW
= 93 mW
ESW(MAX) =
PO( SWITCHINGMAX)
f
93mW
20 kHz
= 4.65 μW
=
For Qg = 500 nC, from Figure 27, a value of ESW = 4.65 μW
gives a Rg = 10.3 Ω.
PE Parameter
Description
IF
LED Current
VF
LED On Voltage
Duty Cycle
Maximum LED Duty Cycle
14
ESW(Rg,Qg)
f
Esw – ENERGY PER SWITCHING CYCLE – μJ
PT
Switching Frequency
Qg = 100 nC
Qg = 500 nC
Qg = 1000 nC
14
12
10
V CC = 19 V
V EE = -9 V
8
6
4
2
0
0
10
20
30
40
Rg – GATE RESISTANCE – :
50
Figure 27. Energy dissipated in the ACPL-312T for each IGBT switching cycle.
Thermal Model
The steady state thermal model for the ACPL-312T is
shown in Figure 28. The thermal resistance values given
in this model can be used to calculate the temperatures
at each node for a given operating condition. As shown
by the model, all heat generated flows through TCA which
raises the case temperature TC accordingly. The value of
TCA depends on the conditions of the board design and
is, therefore, determined by the designer. The value of TCA
= 83°C/W was obtained from thermal measurements using a 2.5 x 2.5 inch PC board, with small traces (no ground
plane), a single ACPL-312T soldered into the center of
the board and still air. The absolute maximum power dissipation de-rating specifications assume a TCA value of
83°C/W. From the thermal mode in Figure 28 the LED and
detector IC junction temperatures can be expressed as:
For example, given PE = 30 mW, PO = 230 mW, TA = 100°C
and TCA = 83°C/W:
TJE = PE .(θ LD ||θ DC ) +θ CA )
θ LC * θ DC
+ PD .
+θ CA + T A
θ LC +θ DC + θ LD
TJE
= PE.339°C/W + PD.140°C/W + TA
= 30 mW@339°C/W + 230 mW .140°C/W + 100°C
θ LC * θ DC
+θ CA
θ LC +θ DC +θ LD
+ PD .(θ DC ||θ LD ) +θ LC ) +TA
= 142°C
TJD = PE .
TJD
= 30 mW.140°C/W + 230 mW.194°C/W + 100°C
Inserting the values for TLC and TDC shown in Figure 28
gives:
TJE
= PE.(256°C/W + TCA) + PD.(57°C/W + TCA) + TA
TJD
= PE.(57°C/W + TCA) + PD.(111°C/W + TCA) + TA
TLD = 442 °C/W
T JE
TLC = 467 °C/W
T JD
TDC = 126 °C/W
TC
T CA = 83 °C/W*
TA
= PE.140°C/W + PD.194°C/W + TA
T JE
T JD
TC
TLC
TLD
TDC
TCA
* TCA
= 149°C
TJE and TJD should be limited to 150°C based on the board
layout and part placement (TCA) specific to the application.
= LED junction temperature
= detector IC junction temeperature
= case temperature measured at the ce nter of the package bottom
= LED-to-case thermal resistance
= LED-to-detector thermal resistance
= detector-to-case thermal resistance
= case-to-ambient thermal resistance
will depend on the board design and the placement of the part.
Figure 28. Thermal model.
LED Drive Circuit Considerations for Ultra High CMR Performance.
Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input
side of the optocoupler, through the package, to the detector IC as shown in Figure 29. The ACPL-312T improves
CMR performance by using a detector IC with an optically
transparent Faraday shield, which diverts the capacitively
coupled current away from the sensitive IC circuitry. However, this shield does not eliminate the capacitive coupling
between the LED and optocoupler pins 5-8 as shown in
1
2
C LEDP
Figure 30. This capacitive coupling causes perturbations
in the LED current during common mode transients and
becomes the major source of CMR failures for a shielded
optocoupler. The main design objective of a high CMR
LED drive circuit becomes keeping the LED in the proper
state (on or off ) during common mode transients. For example, the recommended application circuit (Figure 25),
can achieve 25 kV/μs CMR while minimizing component
complexity. Techniques to keep the LED in the proper
state are discussed in the next two sections.
8
1
7
2
6
3
5
4
C LEDO1
8
C LEDP
7
C LEDO2
3
4
C LEDN
Figure 29. Optocoupler input to output capacitance model for unshielded
optocouplers.
15
C LEDN
SHIELD
6
5
Figure 30. Optocoupler input to output capacitance model for shielded
optocouplers.
CMR with the LED On (CMRH).
A high CMR LED drive circuit must keep the LED on during
common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that
it is not pulled below the threshold during a transient. A
minimum LED current of 10 mA provides adequate margin over the maximum IFLH of 5 mA to achieve 25 kV/
μs CMR. CMR with the LED Off (CMRL). A high CMR LED
drive circuit must keep the LED off (VF ≤ VF(OFF)) during
common mode transients. For example, during a -dVcm/dt
transient in Figure 31, the current flowing through CLEDP
also flows through the RSAT and VSAT of the logic gate. As
+5V
1
8
C LEDP
2
+
V SAT
–
long as the low state voltage developed across the logic
gate is less than VF(OFF), the LED will remain off and no
common mode failure will occur. The open collector drive
circuit, shown in Figure 32, cannot keep the LED off during
a +dVcm/dt transient, since all the current flowing through
CLEDN must be supplied by the LED, and it is not recommended for applications requiring ultra high CMRL performance. Figure 33 is an alternative drive circuit which,
like the recommended application circuit (Figure 25), does
achieve ultra high CMR performance by shunting the LED
in the off state.
7
1
0.1
μF + V CC = 18 V
–
8
+5V
2
C LEDP
3
ttt
6
C LEDN
4
Rg
5
SHIELD
ttt
Q1
3
4
C LEDN
I LEDN
SHIELD
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING –d VCM /dt.
+–
V CM
Figure 31. Equivalent circuit for figure 25 during common mode transient.
1
8
+5V
2
3
4
C LEDP
C LEDN
SHIELD
7
6
5
Figure 33. Recommended LED drive circuit for ultra-high CMR.
16
7
I LEDP
Figure 32. Not recommended open collector drive circuit.
6
5
The ACPL-312T contains an under voltage lockout (UVLO)
feature that is designed to protect the IGBT under fault
conditions which cause the ACPL-312T supply voltage
(equivalent to the fully-charged IGBT gate voltage) to
drop below a level necessary to keep the IGBT in a low resistance state. When the ACPL-312T output is in the high
state and the supply voltage drops below the ACPL-312T
VUVLO– threshold (9.5 < VUVLO– < 12.0) the optocoupler
output will go into the low state with a typical delay, UVLO
Turn Off Delay, of 0.6 μs. When the ACPL-312T output is in
the low state and the supply voltage rises above the ACPL-312T VUVLO+ threshold (11.0 < VUVLO+ < 13.5) the optocoupler output will go into the high state (assumes LED is
“ON”) with a typical delay, UVLO Turn On Delay of 0.8 μs.
14
V O – OUTPUT VOLTAGE – V
12
(12.3, 10.8)
10
(10.7, 9.2)
8
6
4
2
(10.7, 0.1)
0
0
(12.3, 0.1)
5
10
15
(VCC - V EE ) – SUPPLY VOLTAGE – V
Figure 34. Under voltage lock out.
The ACPL-312T includes a Propagation Delay Difference
(PDD) specification intended to help designers minimize
“dead time” in their power inverter designs. Dead time is
the time period during which both the high and low side
power transistors (Q1 and Q2 in Figure 25) are off. Any
overlap in Q1 and Q2 conduction will result in large currents flowing through the power devices between the
high and low voltage motor rails.
To minimize dead time in a given design, the turn on of
LED2 should be delayed (relative to the turn off of LED1)
so that under worst-case conditions, transistor Q1 has just
turned off when transistor Q2 turns on, as shown in Figure
35. The amount of delay necessary to achieve this condition is equal to the maximum value of the propagation
delay difference specification, PDDMAX, which is specified
to be 350 ns over the operating temperature range of 40°C to 125°C. Delaying the LED signal by the maximum
propagation delay difference ensures that the minimum
dead time is zero, but it does not tell a designer what the
maximum dead time will be. The maximum dead time is
equivalent to the difference between the maximum and
minimum propagation delay difference specifications
as shown in Figure 36. The maximum dead time for the
ACPL-312T is 700 ns (= 350 ns - (-350 ns)) over an operating temperature range of -40°C to 125°C.
Note that the propagation delays used to calculate PDD
and dead time are taken at equal temperatures and test
conditions since the optocouplers under consideration
are typically mounted in close proximity to each other and
are switching identical IGBTs.
I LED1
I LED1
VOUT 1
20
Dead Time and Propagation Delay Specifications
VOUT 1
Q1 ON
Q1 ON
Q1 OFF
Q1 OFF
VOUT 2
I LED2
Q2 OFF
Q2 ON
VOUT 2
I LED2
tPHL MAX
tPLH MIN
PDD* MAX = (tPHL- tPLH )MAX =tPHL MAX - tPLH MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Figure 35. Minimum LED skew for zero dead time.
Q2 ON
Q2 OFF
tPHL MIN
tPHL MAX
tPLH
MIN
tPLH MAX
(tPHL- tPLH) MAX
PDD* MAX
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (tPHL MAX - tPHL MIN) + (tPLH MAX- tPLH MIN)
= (tPHL MAX - tPLH MIN ) – (tPHL MIN- tPLH MAX )
= PDD* MAX – PDD* MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Figure 36. Waveforms for dead time.
17
Output Power Derating Curve
450
400
350
Po
300
250
200
150
100
50
0
0
20
40
60
80
100
120
140
Ta
Figure 37. Thermal derating curve, dependence of safety limiting value with
case temperature per IEC/EN/DIN EN 60747-5-2.
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, the A logo and R2Coupler™ are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved.
AV02-1275EN - March 24, 2011
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