ACPL-333J
2.5 Amp Output Current IGBT Gate Driver Optocoupler
with Integrated (VCE) Desaturation Detection, UVLO
Fault Status Feedback, Active Miller Clamp and Auto-Fault Reset
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
The ACPL-333J is an advanced 2.5 A output current, easyto-use, intelligent gate drivers which make IGBT VCE fault
protection compact, affordable, and easy-to implement.
Features such as integrated VCE detection, under voltage
lockout (UVLO), “soft” IGBT turn-off, isolated open
collector fault feedback, active Miller clamping and Autofault reset provide maximum design flexibility and circuit
protection.
• 2.5 A maximum peak output current
The ACPL-333J contains a AlGaAs LED. The LED is optically
coupled to an integrated circuit with a power output
stage. ACPL-333J are ideally suited for driving power IGBTs
and MOSFETs used in motor control inverter applications.
The voltage and current supplied by these optocouplers
make them ideally suited for directly driving IGBTs with
ratings up to 1200 V and 150 A. For IGBTs with higher
ratings, the ACPL-333J can be used to drive a discrete
power stage which drives the IGBT gate. The ACPL-333J
have an insulation voltage of VIORM = 1414 VPEAK.
• Under Voltage Lock-Out Protection (UVLO) with
Hysteresis
13
V CC2
6, 7
D
R
I
V
E
R
5, 8
LED1
11
14
V OUT
DESAT
DESAT
9, 12
SHIELD
V EE
FAULT
VS
2
10
LED2
3
16
1, 4
15
SHIELD
• Desaturation Detection
• Open Collector Isolated fault feedback
• “Soft” IGBT Turn-off
• Automatic Fault Reset after fixed mute time , typical
26ms
• Available in SO-16 package
• 100 ns maximum pulse width distortion (PWD)
• ICC(max) < 5 mA maximum supply current
• Wide operating temperature range: –40°C to 105°C
• Safety approvals:
UL approval, 5000 VRMS for 1 minute, CSA approval,
IEC/EN/DIN-EN 60747-5-5 approval VIORM = 1414 VPEAK
Applications
V CLAMP
V CC1
• 1.7A Active Miller Clamp.Clamp pin short to VEE if not
used
• Wide VCC operating range: 15 V to 30 V over
temperature range
UVLO
CATHODE
• 250 ns maximum propagation delay over temperature
range
• 50 kV/µs minimum common mode rejection (CMR) at
VCM = 1500 V
Block Diagram
ANODE
• 2.0 A minimum peak output current
V CLAMP
VE
V LED
• Isolated IGBT/Power MOSFET gate drive
• AC and brushless DC motor drives
• Industrial inverters and Uninterruptible Power Supply
(UPS)
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this
component to prevent damage and/or degradation which may be induced by ESD. The components
featured in this datasheet are not to be used in military or aerospace applications or environments.
Pin Description
1
VS
2
VCC1
3
FAULT
4
VS
5
CATHODE
6
ANODE
7
ANODE
8
CATHODE
VE
16
VLED
15
DESAT
14
VCC2
13
VEE
12
VOUT
11
VCLAMP
10
VEE
9
Pin
Symbol
Description
1
VS
Input Ground
2
VCC1
Positive input supply voltage. (3.3 V to 5.5 V)
3
FAULT
Fault output. FAULT changes from a high impedance state
to a logic low output within 5 µs of the voltage on the
DESAT pin exceeding an internal reference voltage of 6.5 V.
FAULT output is an open collector which allows the FAULT
outputs from all ACPL-333J in a circuit to be connected
together in a “wired OR” forming a single fault bus for interfacing directly to the micro-controller.
4
VS
Input Ground
5
CATHODE
Cathode
6
ANODE
Anode
7
ANODE
Anode
8
CATHODE
Cathode
9
VEE
Output supply voltage.
10
VCLAMP
Miller clamp
11
VOUT
Gate drive voltage output
12
VEE
Output supply voltage.
13
VCC2
Positive output supply voltage
14
DESAT
Desaturation voltage input. When the voltage on DESAT
exceeds an internal reference voltage of 6.5 V while
the IGBT is on, FAULT output is changed from a high
impedance state to a logic low state within 5 µs.
15
VLED
LED anode. This pin must be left unconnected for guaranteed data sheet performance. (For optical coupling testing
only)
16
VE
Common (IGBT emitter) output supply voltage.
Ordering Information
ACPL-333J is UL Recognized with 5000 Vrms for 1 minute per UL1577.
Option
Part number
RoHS Compliant
Package
Surface
Mount
ACPL-333J
-000E
SO-16
X
-500E
X
Tape& Reel
X
IEC/EN/DIN EN
60747-5-5
Quantity
X
45 per tube
X
850 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-333J-500E to order product of SO-16 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN
60747-5-5 Safety Approval in RoHS compliant.
Example 2:
ACPL-333J-000E to order product of SO-16 Surface Mount package in tube packaging with IEC/EN/DIN EN
60747-5-5 Safety Approval and RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and
RoHS compliant option will use ‘-XXXE‘.
2
Package Outline Drawings
16-Lead Surface Mount
0.457
(0.018)
LAND PATTERN RECOMMENDATION
1.270
(0.050)
16 15 14 13 12 11 10
0.64 (0.025)
9
TYPE NUMBER
DATE CODE
A XXXX
YYWW
EEE
AVAGO
LEAD-FREE
7.493 ± 0.254
(0.295 ± 0.010)
PIN 1 DOT
11.63 (0.458)
LOT ID
2.16 (0.085)
1
2
3
4
5
6
7
8
10.312 ± 0.254
(0.406 ± 0.10)
8.763 ± 0.254
(0.345 ± 0.010)
9°
0.457
(0.018)
Dimensions in Millimeters (Inches)
3.505 ± 0.127
(0.138 ± 0.005)
0-8°
0.64 (0.025) MIN.
10.363 ± 0.254
(0.408 ± 0.010)
ALL LEADS TO
BE COPLANAR
± 0.05 (0.002)
0.203 ± 0.076
(0.008 ± 0.003)
STANDOFF
Floating lead protrusion is 0.25 mm (10 mils) Max.
Note: Initial and continued variation in color of the white mold compound is normal and does not affect performance or reliability of the device
3
Recommended Pb-Free IR Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
Regulatory Information
The ACPL-333J has been approved by the following organizations:
IEC/EN/DIN EN 60747-5-5 Approval under: DIN EN 60747-5-5 (VDE 0884-5):2011-11 EN 60747-5-5:2011
Approval under UL 1577, component recognition program up to VISO = 5000 VRMS. File E55361.
UL
Approval under CSA Component Acceptance Notice #5, File CA 88324.
CSA
Table 1. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics*
Description
Symbol
Characteristic
Installation classification per DIN VDE 0110/39, Table 1
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 600 Vrms
for rated mains voltage ≤ 1000Vrms
I – IV
I – IV
I – IV
I – III
Climatic Classification
40/100/21
Pollution Degree (DIN VDE 0110/39)
Maximum Working Insulation Voltage
Unit
2
VIORM
1414
Vpeak
Input to Output Test Voltage, Method b**,
VPR
VIORM x 1.875=VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC
2652
Vpeak
Input to Output Test Voltage, Method a**,
VIORM x 1.6=VPR, Type and Sample Test, tm=10 sec, Partial discharge < 5 pC
VPR
2262
Vpeak
Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec)
VIOTM
8000
Vpeak
Case Temperature
TS
175
°C
Input Current
IS, INPUT
400
mA
Output Power
PS, OUTPUT
1200
mW
Insulation Resistance at TS, VIO = 500 V
RS
>109
W
Safety-limiting values – maximum values allowed in the event of a failure.
* Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
Surface mount classification is class A in accordance with CECCOO802.
** Refer to IEC/EN/DIN EN 60747-5-5 Optoisolator Safety Standard section of the Avago Regulatory Guide to Isolation Circuits, AV02-2041EN for a
detailed description of Method a and Method b partial discharge test profiles.
Dependence of Safety Limiting Values on Temperature. (take from DS AV01-0579EN Pg.7)
4
Table 2. Insulation and Safety Related Specifications
Parameter
Symbol
ACPL-333J
Units
Conditions
Minimum External Air
Gap (Clearance)
L(101)
8.3
mm
Measured from input terminals to output terminals, shortest
distance through air.
Minimum External
Tracking (Creepage)
L(102)
8.3
mm
Measured from input terminals to output terminals, shortest
distance path along body.
0.5
mm
Through insulation distance conductor to conductor, usually the
straight line distance thickness between the emitter and detector.
>175
V
DIN IEC 112/VDE 0303 Part 1
Minimum Internal
Plastic Gap (Internal
Clearance)
Tracking Resistance
(Comparative Tracking
Index)
CTI
Isolation Group
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
Table 3. Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
-55
125
°C
Operating Temperature
TA
-40
105
°C
2
Output IC Junction Temperature
TJ
125
°C
2
Average Input Current
IF(AVG)
25
mA
1
Peak Transient Input Current,
(VUVLO-
12
12.5
V
VO > 5 V
7, 9,
11
11.1
V
VO < 5 V
7, 9,
12
2.0
0.5
V
6
mA
IO = 0 mA, VO > 5 V
V
1.6
-1.3
5
70
1.95
V
IF = 10 mA
mV/°C
V
IR = 10 mA
pF
f = 1 MHz, VF = 0 V
3
6
7, 8, 9
23
9
Table 6. Switching Specifications (AC)
Unless otherwise noted, all typical values at TA = 25°C, VCC2 - VEE = 30 V, VE - VEE = 0 V;
all Minimum/Maximum specifications are at Recommended Operating Conditions. Only Positive Supply Voltage used.
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Fig.
Note
Propagation Delay Time
to High Output Level
tPLH
100
180
250
ns
1, 13,
14, 15,
16, 29
13, 15
Propagation Delay Time
to Low Output Level
tPHL
100
180
250
ns
Rg = 10 W,
Cg = 10 nF,
f = 10 kHz,
Duty Cycle = 50%,
IF = 10 mA,
VCC2 = 30 V
Pulse Width Distortion
PWD
-100
20
100
ns
14, 17
Propagation Delay
Difference Between Any
Two Parts or Channels
(tPHL - tPLH)
PDD
-150
150
ns
17, 16
Rise Time
tR
50
Fall Time
tF
50
DESAT Sense to
90% VO Delay
tDESAT(90%)
0.15
0.5
µs
CDESAT = 100pF, Rg = 10 W,
Cg = 10 nF, VCC2 = 30 V
17, 30
DESAT Sense to
10% VO Delay
tDESAT(10%)
2
3
µs
CDESAT = 100pF, Rg = 10 W,
Cg = 10 nF, VCC2 = 30 V
18, 19,
20, 30
DESAT Sense to Low Level
FAULT Signal Delay
tDESAT(FAULT)
0.25
0.5
µs
CDESAT = 100 pF, RF = 2.1 kΩ,
CF = Open, Rg = 10 Ω,
Cg = 10 nF, VCC2 = 30 V
30
18
30
19
ns
ns
0.8
DESAT Sense to DESAT
Low Propagation Delay
tDESAT(LOW)
DESAT Input Mute
tDESAT(MUTE)
15
26
Output High Level
Common Mode Transient
Immunity
|CMH|
15
25
50
60
15
25
50
60
Output Low Level
Common Mode Transient
Immunity
7
|CML|
1, 13,
14, 15,
16, 29
19
CDESAT = 100 pF, RF = 2.1 kΩ,
CF = 1 nF, Rg = 10 Ω,
Cg = 10 nF, VCC2 = 30 V
0.25
40
µs
CDESAT = 100pF, RF = 2.1 kW,
Rg = 10 W, Cg = 10 nF,
VCC2 = 30 V
µs
CDESAT = 100pF, RF = 2.1 kW,
Rg = 10 W, Cg = 10 nF,
VCC1 = 5.5V, VCC2 = 30 V
kV/µs
TA = 25°C, IF = 10 mA
VCM = 1500 V, VCC2 = 30 V, RF
= 2.1 kΩ, CF = 15 pF
20
31, 32,
33, 34
TA = 25°C, IF = 10 mA
VCM = 1500 V, VCC2 = 30 V, RF
= 2.1 kΩ, CF = 1 nF
kV/µs
TA = 25°C, VF = 0 V
VCM = 1500 V, VCC2 = 30 V, RF
= 2.1 kΩ, CF = 15 pF
TA = 25°C, VF = 0 V
VCM = 1500 V, VCC2 = 30 V, RF
= 2.1 kΩ, CF = 1 nF
21
21,26
31, 32,
33, 34
22
Table 7. Package Characteristics
Parameter
Symbol
Min.
Input-Output Momentary
Withstand Voltage
VISO
5000
Input-Output Resistance
RI-O
Input-Output Capacitance
Output IC-to-Pins 9 &10
Thermal Resistance
Typ.
Max.
Units
Test Conditions
Fig.
Note
Vrms
RH < 50%, t = 1 min., TA = 25°C
24, 25
> 109
W
VI-O = 500 V
25
CI-O
1.3
pF
freq=1 MHz
q09-10
30
°C/W
TA = 25°C
Notes:
1. Derate linearly above 70°C free air temperature at a rate of 0.3 mA/°C.
2. In order to achieve the absolute maximum power dissipation specified, pins 4, 9, and 10 require ground plane connections and may require
airflow. See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction temperature
and power dissipation. In most cases the absolute maximum output IC junction temperature is the limiting factor. The actual power dissipation
achievable will depend on the application environment (PCB Layout, air flow, part placement, etc.). See the Recommended PCB Layout section
in the application notes for layout considerations. Output IC power dissipation is derated linearly at 10 mW/°C above 90°C. Input IC power
dissipation does not require derating.
3. Maximum pulse width = 10 µs. This value is intended to allow for component tolerances for designs with IO peak minimum = 2.0 A. Derate
linearly from 3.0 A at +25°C to 2.5 A at +105°C. This compensates for increased IOPEAK due to changes in VOL over temperature.
4. This supply is optional. Required only when negative gate drive is implemented.
5. Maximum pulse width = 50 µs.
6. See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details.
7. 15 V is the recommended minimum operating positive supply voltage (VCC2 - VE) to ensure adequate margin in excess of the maximum VUVLO+
threshold of 12.5V. For High Level Output Voltage testing, VOH is measured with a dc load current. When driving capacitive loads, VOH will
approach VCC as IOH approaches zero units.
8. Maximum pulse width = 1.0 ms.
9. Once VO of the ACPL-333J is allowed to go high (VCC2 - VE > VUVLO+), the DESAT detection feature of the ACPL-333J will be the primary source of
IGBT protection. UVLO is needed to ensure DESAT is functional. Once VCC2 is increased from 0V to above VUVLO+, DESAT will remain functional
until VCC2 is decreased below VUVLO-. Thus, the DESAT detection and UVLO features of the ACPL-333J work in conjunction to ensure constant
IGBT protection.
10. See the DESAT fault detection blanking time section in the applications notes at the end of this data sheet for further details.
11. This is the “increasing” (i.e. turn-on or “positive going” direction) of VCC2 - VE
12. This is the “decreasing” (i.e. turn-off or “negative going” direction) of VCC2 - VE
13. This load condition approximates the gate load of a 1200 V/150A IGBT.
14. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH| for any given unit.
15. As measured from IF to VO.
16. The difference between tPHL and tPLH between any two ACPL-333J parts under the same test conditions.
17. As measured from ANODE, CATHODE of LED to VOUT
18. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low.
19. This is the amount of time the DESAT threshold must be exceeded before VOUT begins to go low, and the FAULT output to go low. This is supply
voltage dependent.
20. Fault Reset: This is the amount of time when VOUT will be asserted low after DESAT threshold is exceeded. See the Description of Operation
(Fault Reset) topic in the application information section.
21. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in the high state (i.e., VO > 15 V or FAULT > 2 V).
22. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in a low state (i.e., VO < 1.0 V or FAULT < 0.8 V).
23. To clamp the output voltage at VCC - 3 VBE, a pull-down resistor between the output and VEE is recommended to sink a static current of 650 µA
while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-down
resistor is not used.
24. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 Vrms for 1 second. This test is
performed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-5 Insulation Characteristic Table.\
25. This is a two-terminal measurement: pins 1-8 are shorted together and pins 9-16 are shorted together.
26. Split resistors network with a ratio of 1:1 is needed at input LED1. See Figure 34.
8
IF
tr
tf
90%
50%
V OUT
10%
tPLH
tPHL
Figure 1. VOUT propagation delay waveforms
5
2.5
IOL - OUTPUT LOW CURRENT
IOH - OUTPUT HIGH CURRENT - A
3.0
2.0
1.5
1.0
-40
-20
0
20
40
TA - TEMPERATURE - C
60
80
2
-----V OUT =VEE +15V
___VOUT =VEE +2.5V
1
-20
0
20
o
40
T A - TEMPERATURE -
60
80
105
80
105
oC
Figure 3. IOL vs. temperature
0
0.25
____IOUT = -650uA
VOL - OUTPUT LOW VOLTAGE - V
(VOH - VCC) - HIGH OUTPUT VOLTAGE DROP - V
3
0
-40
105
Figure 2. IOH vs. temperature
-0.5
-1
-1.5
-2
-2.5
-40
-20
0
20
40
T A - TEMPERATURE -
Figure 4. VOH vs. temperature
9
4
60
80
100
0.2
0.15
0.1
0.05
0
-40
-20
0
20
40
T A - TEMPERATURE -
oC
Figure 5. VOL vs. temperature
60
oC
8
_ _ _ _ 105 o C
______ 25 o C
--------- -40 o C
29
VOL - LOW OUTPUT VOLTAGE DROP - V
V OH - HIGH OUTPUT VOLTAGE DROP - V
30
28
27
26
25
0.0
0.2
0.4
0.6
0.8
IOH - OUTPUT HIGH CURRENT - A
6
5
4
3
2
1
0
1.0
0
0.5
2
2.5
ICC2 - OUTPUT SUPPLY CURRENT - mA
3.50
3
2
1
0
-40
-20
0
20
40
60
80
105
ICC2H
ICC2L
3.25
3.00
2.75
2.50
2.25
2.00
-40
-20
TA - TEMPERATURE - oC
ICH - BLANKING CAPACITOR
CHARGING CURRENT - mA
2.55
2.45
2.35
60
80
105
20
25
30
-0.25
-0.30
-0.35
-40
-20
0
20
40
TA - TEMPERATURE - °C
VCC2 - OUTPUR SUPPLY VOLTAGE - V
Figure 10. ICC2 vs. VCC2
40
-0.20
ICC2H
ICC2L
15
20
Figure 9. ICC2 vs. temperature
2.65
2.25
0
TA - TEMPERATURE - oC
Figure 8. ICL vs. temperature
10
1.5
Figure 7. VOL vs. IOL
4
ICC2 - OUTPUT SUPPLY CURRENT - mA
1
IOL - OUTPUT LOW CURRENT - A
Figure 6. VOH vs. IOH
ICL - CLAMP LOW LEVEN SINKING CURRENT
_ _ _ _ 100 o C
______ 25 o C
--------- -40 o C
7
Figure 11. ICHG vs. temperature
60
80
105
300
TP - PROPAGATION DELAY - ns
VDESAT - DESAT THRESHOLD - V
7.5
7.0
6.5
6.0
-40
-20
0
20
40
60
TA - TEMPERATURE - °C
80
TP - PROPAGATION DELAY - ns
TP - PROPAGATION DELAY - ns
-20
0
20
40
60
80
300
t PLH
250
200
150
105
t PLH
t PHL
250
200
150
100
100
15
20
25
30
Vcc - SUPPLY VOLTAGE - V
Figure 14. Propagation delay vs. supply voltage
t PLH
t PHL
200
100
10
20
30
LOAD CAPACITANCE - nF
Figure 16. Propagation delay vs. load capacitance
0
10
20
30
LOAD RESISTANCE - ohm
Figure 15. Propagation delay vs. load resistance
300
TP - PROPAGATION DELAY - ns
150
Figure 13. Propagation delay vs. temperature
t PHL
11
200
TA - TEMPERATURE - °C
300
0
t PHL
250
100
-40
105
Figure 12. DESAT threshold vs. temperature
0
t PLH
40
50
40
50
TDESAT - DESAT Sense to 10% Vo Delay - us
TDESAT90% - DESAT Sense to 90% Vo Delay - ns
3.0
300
250
200
150
100
-40
-20
0
20
40
60
80
VCC2 = 15V
VCC2 = 30V
2.5
2.0
1.5
1.0
-40
105
-20
0
TA - TEMPERATURE - °C
TDESAT10% - DESAT Sense to 10% Vo Delay - ms
TDESAT10% - DESAT Sense to 10% Vo Delay - us
0.012
VCC2 = 30V
3.0
2.0
1.0
0.0
20
30
LOAD RESISTANCE - ohm
40
Figure 19. DESAT sense to 10% VOUT delay vs. load resistance
12
60
80
105
Figure 18. DESAT sense to 10% VOUT delay vs. temperature
VCC2 = 15V
10
40
TA - TEMPERATURE - °C
Figure 17. DESAT sense to 90% VOUT delay vs. temperature
4.0
20
50
VCC2 = 15V
VCC2 = 30V
0.008
0.004
0.000
0
10
20
30
40
LOAD CAPACITANCE - nF
Figure 20. DESAT sense to 10% VOUT delay vs. load capacitance
50
1
VS
2
VCC1
3
FAULT
4
VS
5
CATHODE
6
VE
16
VLED
15
DESAT
14
VCC2
13
VEE
12
ANODE
VOUT
11
7
ANODE
VCLAMP
10
8
CATHODE
VEE
9
VE
16
VLED
15
DESAT
14
VCC2
13
VEE
12
10mA
0.1µF
15V Pulsed
+_
IOUT
+_
0.1µF
30V
Figure 21. IOH Pulsed test circuit
1
VS
2
VCC1
3
FAULT
4
VS
5
CATHODE
6
ANODE
VOUT
11
7
ANODE
VCLAMP
10
8
CATHODE
VEE
9
VE
16
VLED
15
DESAT
14
VCC2
13
VEE
12
0.1µF
15V Pulsed
IOUT
+_
0.1µF
+_
30V
Figure 22. IOL Pulsed test circuit
1
VS
2
VCC1
3
FAULT
4
VS
5
CATHODE
6
ANODE
VOUT
11
7
ANODE
VCLAMP
10
8
CATHODE
VEE
9
10mA
Figure 23. VOH Pulsed test circuit
13
0.1µF
VOUT
+_
0.1µF
650µA
30V
1
VS
2
VCC1
3
FAULT
4
VS
5
CATHODE
6
VE
16
VLED
15
DESAT
14
VCC2
13
VEE
12
ANODE
VOUT
11
7
ANODE
VCLAMP
10
8
CATHODE
VEE
9
VE
16
VLED
15
DESAT
14
VCC2
13
VEE
12
0.1µF
F
100mA
VOUT
0.1µF
+_
30V
Figure 24. VOL Pulsed test circuit
1
VS
2
VCC1
3
FAULT
4
VS
5
CATHODE
6
ANODE
VOUT
11
7
ANODE
VCLAMP
10
8
CATHODE
VEE
9
1
VS
VE
16
2
VCC1
VLED
15
3
FAULT
DESAT
14
4
VS
VCC2
13
5
CATHODE
VEE
12
6
ANODE
VOUT
11
7
ANODE
VCLAMP
10
8
CATHODE
VEE
9
10mA
0.1µF
ICC2
0.1µF
+_
30V
Figure 25. ICC2H test circuit
Figure 26. ICC2L test circuit
14
0.1µF
I CC2
0.1µF
+_
30V
1
VS
2
VCC1
3
FAULT
4
VS
5
CATHODE
6
VE
16
VLED
15
DESAT
14
VCC2
13
VEE
12
ANODE
VOUT
11
7
ANODE
VCLAMP
10
8
CATHODE
VEE
9
VE
16
VLED
15
DESAT
14
ICHG
10mA
0.1µF
0.1µF
+_
30V
Figure 27. ICHG Pulsed test circuit
VS
2
VCC1
3
FAULT
4
VS
5
CATHODE
6
VCC2
13
VEE
12
ANODE
VOUT
11
7
ANODE
VCLAMP
10
8
CATHODE
VEE
9
VE
16
VLED
15
DESAT
14
VCC2
13
VEE
12
VOUT
11
VCLAMP
10
VEE
9
+_
1
7V
0.1µF
IDSCHG
0.1µF
+_
30V
Figure 28. IDSCHG test circuit
10mA, 10kHz,
50% Duty Cycle
1
VS
2
VCC1
3
FAULT
4
VS
5
CATHODE
6
ANODE
7
ANODE
8
CATHODE
Figure 29. tPLH, tPHL, tf, tr, test circuit
15
0.1µF
VOUT
10Ω
10nF
0.1µF
+_
30V
1
VS
2
VCC1
3
FAULT
4
VS
5
CATHODE
6
ANODE
VE
16
VLED
15
DESAT
14
VCC2
13
VEE
12
VOUT
11
VCLAMP
10
VIN
RF=2.1kΩ
VFAULT
0.1µF
CF
5V
+_
10Ω
7
ANODE
8
CATHODE
VEE
9
1
VS
VE
16
2
VCC1
VLED
15
3
FAULT
DESAT
14
4
VS
VCC2
13
5
CATHODE
VEE
12
6
ANODE
VOUT
11
7
ANODE
VCLAMP
10
8
CATHODE
VEE
9
VE
16
VLED
15
DESAT
14
VCC2
13
VEE
12
10mA
VOUT
0.1µF
+_
30V
10nF
Figure 30. tDESAT fault test circuit
5V
RF=2.1kΩ
SCOPE
CF=15pF
or 1nF
0.1µF
30V
10
10Ω
0.1µF
360Ω
VCM
Figure 31. CMR Test circuit LED2 off
5V
1
VS
2
VCC1
3
FAULT
4
VS
5
CATHODE
6
ANODE
VOUT
11
7
ANODE
VCLAMP
10
8
CATHODE
VEE
9
RF=2.1kΩ
SCOPE
CF=15pF
or 1nF
0.1µF
10nF
30V
10Ω
0.1µF
360Ω
Figure 32. CMR Test Circuit LED2 on
16
VCM
10nF
5V
RF=2.1kΩ
CF=15pF
or 1nF
0.1µF
1
VS
2
VCC1
3
FAULT
4
VS
5
CATHODE
6
VE
16
VLED
15
DESAT
14
VCC2
13
VEE
12
ANODE
VOUT
11
7
ANODE
VCLAMP
10
8
CATHODE
VEE
9
30V
SCOPE
10Ω
10
0.1µF
360Ω
10nF
VCM
Figure 33. CMR Test circuit LED1 off
5V
1
VS
2
VCC1
3
FAULT
4
VS
5
CATHODE
6
VE
16
VLED
15
DESAT
14
VCC2
13
VEE
12
ANODE
VOUT
11
7
ANODE
VCLAMP
10
8
CATHODE
VEE
9
RF=2.1kΩ
CF=15pF
or 1nF
0.1µF
30V
SCOPE
10 Ω
0.1µF
360 Ω
10nF
5V
180Ω
5
CATHODE
6
ANODE
7
ANODE
8
CATHODE
180Ω
Split resistors network with a ratio of 1:1
Figure 34. CMR Test Circuit LED1 on
17
VCM
Application Information
Product Overview Description
The ACPL-333J are highly integrated power control
devices that incorporate all the necessary components
for a complete, isolated IGBT / MOSFET gate drive circuit
with fault protection and feedback into one SO-16
package. Active Miller clamp function eliminates the
need of negative gate drive in most application and
allows the use of simple bootstrap supply for high side
driver. An optically isolated power output stage drives
IGBTs with power ratings of up to 150 A and 1200 V. A
high speed internal optical link minimizes the propagation delays between the microcontroller and the IGBT
while allowing the two systems to operate at very large
common mode voltage differences that are common
in industrial motor drives and other power switching
applications. An output IC provides local protection
for the IGBT to prevent damage during over current,
and a second optical link provides a fully isolated fault
status feedback signal for the microcontroller. A built
in “watchdog” circuit, UVLO monitors the power stage
supply voltage to prevent IGBT caused by insufficient
gate drive voltages. This integrated IGBT gate driver is
designed to increase the performance and reliability of
a motor drive without the cost, size, and complexity of a
discrete design.
Two light emitting diodes and two integrated circuits
housed in the same SO-16 package provide the input
control circuitry, the output power stage, and two optical
channels. The output Detector IC is designed manufactured on a high voltage BiCMOS/Power DMOS process.
The forward optical signal path, as indicated by LED1,
transmits the gate control signal. The return optical
signal path, as indicated by LED2, transmits the fault
13
V CC2
UVLO
ANODE
CATHODE
6, 7
D
R
I
V
E
R
5, 8
LED1
11
14
V OUT
DESAT
DESAT
9, 12
SHIELD
V EE
V CLAMP
V CC1
FAULT
VS
2
10
LED2
3
16
1, 4
15
SHIELD
Figure 35. Block Diagram of ACPL-333J
18
V CLAMP
VE
V LED
status feedback signal.
Under normal operation, the LED1 directly controls the
IGBT gate through the isolated output detector IC, and
LED2 remains off. When an IGBT fault is detected, the
output detector IC immediately begins a “soft” shutdown
sequence, reducing the IGBT current to zero in a controlled manner to avoid potential IGBT damage from
inductive over voltages. Simultaneously, this fault status
is transmitted back to the input via LED2, where the fault
latch disables the gate control input and the active low
fault output alerts the microcontroller.
During power-up, the Under Voltage Lockout (UVLO)
feature prevents the application of insufficient gate
voltage to the IGBT, by forcing the ACPL-333J ’s output
low. Once the output is in the high state, the DESAT (VCE)
detection feature of the ACPL-333J provides IGBT protection. Thus, UVLO and DESAT work in conjunction to
provide constant IGBT protection.
Recommended Application Circuit
The ACPL-333J have an LED input gate control, and an
open collector fault output suitable for wired ‘OR’ applications. The recommended application circuit shown in
Figure 36 (page 21) illustrates a typical gate drive implementation using the ACPL-333J. The following describes
about driving IGBT. However, it is also applicable to
MOSFET. Depending upon the MOSFET or IGBT gate
threshold requirements, designers may want to adjust
the VCC supply voltage (Recommended VCC = 17.5V for
IGBT and 12.5V for MOSFET).
The two supply bypass capacitors (0.1 µF) provide the
large transient currents necessary during a switching
transition. Because of the transient nature of the
charging currents, a low current (5mA) power supply
suffices. The desaturation diode DDESAT 600V/1200V
fast recovery type, trr below 75ns (e.g. ERA34-10) and
capacitor CBLANK are necessary external components for
the fault detection circuitry. The gate resistor RG serves to
limit gate charge current and controls the IGBT collector
voltage rise and fall times. The open collector fault
output has a passive pull-up resistor RF (2.1 kW) and a
1000 pF filtering capacitor, CF. A 47 kW pull down resistor
RPULL-DOWN on VOUT provides a predictable high level
output voltage (VOH). In this application, the IGBT gate
driver will shut down when a fault is detected and fault
reset by next cycle of IGBT turn on. Application notes are
mentioned at the end of this datasheet.
+
_
1
VS
2
VCC1
3
FAULT
4
VS
5
CATHODE
6
ANODE
7
ANODE
8
CATHODE
VE 16
VLED 15
RF
0.1µF
DESAT 14
CF
0.1µF
CBLANK
100 Ω
DDESAT
RG
+
_
VCC2 13
VEE 12
VOUT
11
Q1
R
+
_
VCLAMP 10
VEE
+
VCE
-
RPULL--DOWN
9
Q2
+
VCE
-
+ HVDC
3-PHASE
AC
- HVDC
Figure 36. Recommended application circuit (Single Supply) with desaturation detection and active Miller Clamp
Description of Operation
Normal Operation
Fault Reset
During normal operation, VOUT of the ACPL-333J is controlled by input LED current IF (pins 5, 6, 7 and 8), with
the IGBT collector-to-emitter voltage being monitored
through DESAT. The FAULT output is high. See Figure 37.
Once fault is detected, the output will be soft-shut down
to low. All input LED signals will be ignored during
the fault period to allow the driver to completely soft
shut-down the IGBT. For ACPL-333J, the driver will automatically reset the FAULT pin after a fixed mute time of
25ms (typical). See Figure 37.
Fault Condition
The DESAT pin monitors the IGBT Vce voltage. When the
voltage on the DESAT pin exceeds 6.5 V while the IGBT is
on, VOUT is slowly brought low in order to “softly” turn-off
the IGBT and prevent large di/dt induced voltages. Also
activated is an internal feedback channel which brings
the FAULT output low for the purpose of notifying the
micro-controller of the fault condition.
t DESAT(LOW)
IF
6.5V
Automatic Reset
after mute time
V DESAT
t BLANK
t DESAT(10%)
90%
VOUT
10%
t DESAT(90%)
FAULT
50%
t DESAT(FAULT)
t DESAT(MUTE)
Figure 37. Fault Timing diagram (ACPL-333J)
19
50%
Output Control
Slow IGBT Gate Discharge during Fault Condition
The outputs (VOUT and FAULT) of the ACPL-333J are controlled by the combination of IF, UVLO and a detected
IGBT Desat condition. Once UVLO is not active (VCC2 VE > VUVLO), VOUT is allowed to go high, and the DESAT
(pin 14) detection feature of the ACPL-333J will be the
primary source of IGBT protection. Once VCC2 is increased
from 0V to above VUVLO+, DESAT will remain functional
until VCC2 is decreased below VUVLO-. Thus, the DESAT
detection and UVLO features of the ACPL-333J work in
conjunction to ensure constant IGBT protection.
When a desaturation fault is detected, a weak pull-down
device in the ACPL-333J output drive stage will turn on
to ‘softly’ turn off the IGBT. This device slowly discharges
the IGBT gate to prevent fast changes in drain current
that could cause damaging voltage spikes due to lead
and wire inductance. During the slow turn off, the large
output pull-down device remains off until the output
voltage falls below VEE + 2 Volts, at which time the large
pull down device clamps the IGBT gate to VEE.
Desaturation Detection and High Current Protection
The ACPL-333J satisfies these criteria by combining a
high speed, high output current driver, high voltage
optical isolation between the input and output, local
IGBT desaturation detection and shut down, and an
optically isolated fault status feedback signal into a single
16-pin surface mount package.
The fault detection method, which is adopted in the
ACPL-333J, is to monitor the saturation (collector)
voltage of the IGBT and to trigger a local fault shutdown
sequence if the collector voltage exceeds a predetermined threshold. A small gate discharge device slowly
reduces the high short circuit IGBT current to prevent
damaging voltage spikes. Before the dissipated energy
can reach destructive levels, the IGBT is shut off. During
the off state of the IGBT, the fault detect circuitry is simply
disabled to prevent false ‘fault’ signals.
The alternative protection scheme of measuring IGBT
current to prevent desaturation is effective if the short
circuit capability of the power device is known, but
this method will fail if the gate drive voltage decreases
enough to only partially turn on the IGBT. By directly
measuring the collector voltage, the ACPL-333J limits the
power dissipation in the IGBT even with insufficient gate
drive voltage. Another more subtle advantage of the desaturation detection method is that power dissipation in
the IGBT is monitored, while the current sense method
relies on a preset current threshold to predict the safe
limit of operation. Therefore, an overly conservative over
current threshold is not needed to protect the IGBT.
DESAT Fault Detection Blanking Time
The DESAT fault detection circuitry must remain disabled
for a short time period following the turn-on of the IGBT
to allow the collector voltage to fall below the DESAT
threshold. This time period, called the DESAT blanking
time is controlled by the internal DESAT charge current,
the DESAT voltage threshold, and the external DESAT
capacitor.
The nominal blanking time is calculated in terms of
external capacitance (CBLANK), FAULT threshold voltage
(VDESAT ), and DESAT charge current (ICHG) as tBLANK =
CBLANK x VDESAT / ICHG. The nominal blanking time with
the recommended 100pF capacitor is 100pF * 6.5 V / 240
µA = 2.7 µsec.
The capacitance value can be scaled slightly to adjust the
blanking time, though a value smaller than 100 pF is not
recommended. This nominal blanking time represents
the longest time it will take for the ACPL-333J to respond
to a DESAT fault condition. If the IGBT is turned on while
the collector and emitter are shorted to the supply rails
(switching into a short), the soft shut-down sequence
will begin after approximately 3 µsec. If the IGBT collector
and emitter are shorted to the supply rails after the IGBT
is already on, the response time will be much quicker due
to the parasitic parallel capacitance of the DESAT diode.
The recommended 100pF capacitor should provide
adequate blanking as well as fault response times for
most applications.
IF
UVLO(VCC2-VE)
DESAT Function
Pin 3 (FAULT) Output
VOUT
ON
Active
Not Active
High
Low
ON
Not Active
Active (with DESAT fault)
Low (FAULT)
Low
ON
Not Active
Active (no DESAT fault)
High (or no fault)
High
OFF
Active
Not Active
High
Low
OFF
Not Active
Not Active
High
Low
20
Under Voltage Lockout
The ACPL-333J Under Voltage Lockout (UVLO) feature is
designed to prevent the application of insufficient gate
voltage to the IGBT by forcing the ACPL-333J output
low during power-up. IGBTs typically require gate
voltages of 15 V to achieve their rated VCE(ON) voltage.
At gate voltages below 13 V typically, the VCE(ON) voltage
increases dramatically, especially at higher currents.
At very low gate voltages (below 10 V), the IGBT may
operate in the linear region and quickly overheat.
The UVLO function causes the output to be clamped
whenever insufficient operating supply (VCC2) is applied.
Once VCC2 exceeds VUVLO+ (the positive-going UVLO
threshold), the UVLO clamp is released to allow the
device output to turn on in response to input signals. As
VCC2 is increased from 0 V (at some level below VUVLO+),
first the DESAT protection circuitry becomes active. As
VCC2 is further increased (above VUVLO+), the UVLO clamp
is released. Before the time the UVLO clamp is released,
the DESAT protection is already active. Therefore, the
UVLO and DESAT Fault detection feature work together
to provide seamless protection regardless of supply
voltage (VCC2).
Active Miller Clamp
A Miller clamp allows the control of the Miller current
during a high dV/dt situation and can eliminate the use
of a negative supply voltage in most of the applications.
During turn-off, the gate voltage is monitored and the
clamp output is activated when gate voltage goes below
2V (relative to VEE). The clamp voltage is VOL+2.5V typ
for a Miller current up to 1100mA. The clamp is disabled
when the LED input is triggered again.
1
VS
2
VCC1
3
FAULT
4
VS
5
CATHODE
6
VE
16
VLED
15
DESAT
14
VCC2
13
VEE
12
ANODE
VOUT
11
7
ANODE
VCLAMP
10
8
CATHODE
VEE
9
The freewheeling of flyback diodes connected across
the IGBTs can have large instantaneous forward voltage
transients which greatly exceed the nominal forward
voltage of the diode. This may result in a large negative
voltage spike on the DESAT pin which will draw substantial current out of the driver if protection is not used. To
limit this current to levels that will not damage the driver
IC, a 100 ohm resistor should be inserted in series with
the DESAT diode. The added resistance will not alter the
DESAT threshold or the DESAT blanking time.
Other Recommended Components
2
VCC1
The application circuit in Figure 36 includes an output
pull-down resistor, a DESAT pin protection resistor, a
FAULT pin capacitor, and a FAULT pin pullup resistor and
Active Miller Clamp connection.
3
FAULT
4
VS
5
CATHODE
6
21
RPULL-DOWN
DESAT Pin Protection Resistor
VS
During the output high transition, the output voltage
rapidly rises to within 3 diode drops of VCC2. If the output
current then drops to zero due to a capacitive load, the
output voltage will slowly rise from roughly VCC2-3(VBE)
to VCC2 within a period of several microseconds. To limit
the output voltage to VCC2-3(VBE), a pull-down resistor,
RPULL-DOWN between the output and VEE is recommended to sink a static current of several 650 µA while the
output is high. Pull-down resistor values are dependent
on the amount of positive supply and can be adjusted
according to the formula, Rpull-down = [VCC2-3 * (VBE)] /
650 µA.
RG
Figure 38. Output pull-down resistor.
1
Output Pull-Down Resistor
VCC
VE
16
VLED
15
DESAT
14
VCC2
13
VEE
12
ANODE
VOUT
11
7
ANODE
VCLAMP
10
8
CATHODE
VEE
9
Figure 39. DESAT pin protection.
100pF
100 Ω
VCC
RG
DDESAT
Capacitor on FAULT Pin for High CMR
Pull-up Resistor on FAULT Pin
Rapid common mode transients can affect the fault pin
voltage while the fault output is in the high state. A 1000
pF capacitor should be connected between the fault pin
and ground to achieve adequate CMOS noise margins at
the specified CMR value of 50 kV/µs.
The FAULT pin is an open collector output and therefore
requires a pull-up resistor to provide a high-level signal.
Also the FAULT output can be wire ‘OR’ed together with
other types of protection (e.g. over-temperature, overvoltage, over-current ) to alert the microcontroller.
Other Possible Application Circuit (Output Stage)
1
VS
2
VCC1
3
FAULT
4
VS
5
CATHODE
VE
16
VLED
15
DESAT
14
VCC2
13
VEE
12
01F 01F
01F
O
6
ANODE
VOUT
11
7
ANODE
VCLAMP
10
8
CATHODE
VEE
9
R
O
R
2
RG
1
+_
Q1
RPULL-DOWN
_+
Q2
+
VCE
+
VCE
-
+ HVDC
3-PHASE
AC
- HVDC
Figure 40. IGBT drive with negative gate drive, external booster and desaturation detection (VCLAMP should be connected to VEE when it is not used)
VCLAMP is used as secondary gate discharge path. * indicates component required for negative gate drive topology
1
VS
2
VCC1
3
FAULT
4
VS
5
CATHODE
VE
16
VLED
15
DESAT
14
VCC2
13
VEE
12
01F 01F
01F
O
6
ANODE
VOUT
11
7
ANODE
VCLAMP
10
8
CATHODE
VEE
9
R
O
R
2
RG
1
+_
Q1
RPULL-DOWN
+_
Q2
+
VCE
+
VCE
-
R3
Figure 41. Large IGBT drive with negative gate drive, external booster. VCLAMP control secondary discharge path for higher power application.
22
+ HVDC
3-PHASE
AC
- HVDC
Thermal Model
The ACPL-333J is designed to dissipate the majority of
the heat through pins 1, 4, 5 & 8 for the input IC and pins
9 & 12 for the output IC. (There are two VEE pins on the
output side, pins 9 and 12, for this purpose.) Heat flow
through other pins or through the package directly into
ambient are considered negligible and not modeled
here.
In order to achieve the power dissipation specified in
the absolute maximum specification, it is imperative
that pins 5, 9, and 12 have ground planes connected to
them. As long as the maximum power specification is
not exceeded, the only other limitation to the amount
of power one can dissipate is the absolute maximum
junction temperature specification of 125°C. The junction
temperatures can be calculated with the following
equations:
Tji = Pi (θi5 + θ5A) + TA
Tjo = Po (θo9,12 + θ9,12A) + TA
Tjo
Tji
θl9, 12 = 30°C/W
θI1 = 60°C/W
TP9, 12
TP1
θ1A = 50°C/W*
θ9, 12A = 50°C/W*
TA
where Pi = power into input IC and Po = power into
output IC. Since θ5A and θ9,12A are dependent on PCB
layout and airflow, their exact number may not be
available. Therefore, a more accurate method of calculating the junction temperature is with the following
equations:
Tji = Pi θi5 + TP5
Tjo = Po θo9,12 + TP9,12
These equations, however, require that the pin 5 and pins
9, 12 temperatures be measured with a thermal couple
on the pin at the ACPL-333J package edge.
If the calculated junction temperatures for the thermal
model in Figure 42 is higher than 125°C, the pin temperature for pins 9 and 12 should be measured (at the
package edge) under worst case operating environment
for a more accurate estimate of the junction temperatures.
Tji = junction temperature of input side IC
Tjo = junction temperature of output side IC
TP5 = pin 5 temperature at package edge
TP9,12 = pin 9 and 12 temperature at package edge
θI5 = input side IC to pin 5 thermal resistance
θo9,12 = output side IC to pin 9 and 12 thermal resistance
θ5A = pin 5 to ambient thermal resistance
θ9,12A = pin 9 and 12 to ambient thermal resistance
*The θ5A and θ9,12A values shown here are for PCB layouts with reasonable air flow.
This value may increase or decrease by a factor of 2 depending on PCB layout and/or airflow.
Figure 42. ACPL-333J Thermal Model
Related Application Notes
AN5314 – Active Miller Clamp
AN5315 – “Soft” Turn-off Feature
AN1043 – Common-Mode Noise : Sources and Solutions
AV02-0310EN - Plastic Optocouplers Product ESD and Moisture Sensitivity
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2015 Avago Technologies. All rights reserved. Obsoletes AV02-0726EN
AV02-1087EN - March 6, 2015
工商网监
湘ICP备2023018690号
