ACPL-339J-000E

ACPL-339J Dual-Output Gate Drive Optocoupler Interface with Integrated (VCE) DESAT Detection, FAULT and UVLO Status Feedback Data Sheet Description Features The ACPL-339J is an advanced 1.0 A dual-output, easy-touse, intelligent IGBT and Power MOSFET gate drive optocoupler interface. Uniquely designed to support MOSFET buffer of various current ratings, the ACPL-339J makes it easier for system engineers to support different system power ratings using one hardware platform by interchanging the MOSFET buffers and power IGBT/MOSFET switches. These changes can be made without redesigning the critical circuit isolation and short-circuit protection. This concept maximizes gate drive design scalability for motor control and power conversion applications ranging from low to high power ratings. • Dual output drive for external NMOS and PMOS buffer The ACPL-339J contains a AlGaAs LED. The LED is optically coupled to an integrated circuit with two power output stages with active timing control to prevent cross conduction at external MOSFET buffer. It is also integrated with features such as VCE detection, under voltage lockout (UVLO), “soft” IGBT turn-off, and isolated open collector fault feedback to provide maximum design flexibility and circuit protection. The ACPL-339J has an insulation voltage of VIORM = 1414 Vpeak in IEC/EN/DIN EN 60747-5-5. Functional Diagram 13 VCC2 UVLO_P ANODE CATHODE 3 D R I V E R 2, 4 LED1 SHIELD Drive Logic & Overlap Protection 12 16 FAULT 6 9 LED2 7 15 DESAT VGND1 5, 8 • Active timing control to prevent cross conduction in MOSFET buffer • IGBT desaturation detection • Isolated DESAT and UVLO fault feedback • Configurable “Soft” shutdown during fault • Under Voltage Lock-Out Protection (UVLO) with Hysteresis for positive and negative power supply • 300 ns maximum propagation delay over temperature range. • 6.0 mA to 10.0 mA Low LED input current • 25 kV/µs Minimum Common Mode Rejection (CMR) at VCM = 1500 V • Wide Operating VCC Range: 15 V to 30 V • Industrial temperature range: -40° C to 105° C • SO-16 package • Safety Approval Pending – UL Recognized 5000 VRMS for 1 min. – CSA – IEC/EN/DIN EN 60747-5-5 VIORM = 1414 Vpeak Applications • IGBT/Power MOSFET gate drive Interface • AC and brushless DC motor drives VE • Renewable energy inverters • Industrial Inverters UVLO_N 11 VCC1 VOUTP • 1.0 A minimum peak output current 14 VOUTN • Switching power supplies VEE DESAT VGMOS SHIELD CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Pin Description VE 16 1 NC 2 CATHODE DESAT 15 3 ANODE VGMOS 14 4 CATHODE VCC2 13 5 VGND1 VOUTP 12 6 VCC1 VOUTN 11 7 FAULT NC 10 8 VGND1 VEE Pin Symbol Description 1 NC No connection 2 CATHODE Cathode 3 ANODE Anode 4 CATHODE Cathode 5 VGND1 Input ground 6 VCC1 Positive input supply voltage (3.3 V ± 5%, 5 V ± 5%) 7 FAULT Fault output. FAULT changes from logic low to high output: a) after TBLANK (set by CBLANK and the internal current source of 250 μA), once the voltage on the DESAT pin exceeding an internal reference voltage of 8 V (reference to VE) b) UVLO condition 8 VGND1 Input ground 9 VEE Output supply voltage 9 10 NC No connection 11 VOUTN 12 VOUTP Low side voltage output 13 VCC2 Positive output supply voltage 14 VGMOS 15 DESAT VGMOS will switch from VEE to VE after DESAT is activated 16 VE Common (IGBT emitter) output supply voltage High side voltage output Desaturation voltage input. When the voltage on DESAT exceeds an internal reference voltage of 8 V while the IGBT is on, FAULT and VGMOS outputs are changed from logic low to high state. Ordering Information ACPL-339J is UL Recognized with 5000 Vrms for 1 minute per UL1577. Option Part number RoHS Compliant Package Surface Mount ACPL-339J -000E SO-16 X -500E X Tape & Reel X IEC/EN/DIN EN 60747-5-5 Quantity X 45 per tube X 850 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: ACPL-339J-500E to order product of SO-16 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval in RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. 2 Package Outline Drawings ACPL-339J 16-Lead Surface Mount Package 0.018 (0.457) 16 15 14 13 12 11 10 9 LAND PATTERN RECOMMENDATION 0.025 (0.64 ) 0.050 (1.270) TYPE NUMBER DATE CODE A 339J YYWW 0.295 ± 0.010 (7.493 ± 0.254) 0.458 (11.63) 0.085 (2.16) 9° 1 2 3 4 5 6 7 8 0.406 ± 0.10 (10.312 ± 0.254) 0.018 (0.457) ALL LEADS TO BE COPLANAR ± 0.002 0.345 ± 0.010 (8.986 ± 0.254) 0.138 ± 0.005 (3.505 ± 0.127) 0-8° 0.025 MIN. 0.408 ± 0.010 (10.160 ± 0.254) 0.008 ± 0.003 (0.203 ± 0.076) STANDOFF Dimensions in inches (millimeters) Notes: Initial and continued variation in the color of the ACPL-339J’s white mold compound is normal and does note affect device performance or reliability. Floating Lead Protrusion is 0.25 mm (10 mils) max. Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non- Halide Flux should be used. Regulatory Information The ACPL-339J is pending approval by the following organizations: IEC/EN/DIN EN 60747-5-5 Maximum working insulation voltage VIORM = 1414 VPEAK UL Approval under UL 1577, component recognition program up to VISO = 5000 VRMS. File E55361. CSA Approval under CSA Component Acceptance Notice #5, File CA 88324. 3 Table 1. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* Description Symbol Characteristic Installation classification per DIN VDE 0110/39, Table 1 for rated mains voltage ≤ 150 Vrms for rated mains voltage ≤ 300 Vrms for rated mains voltage ≤ 600 Vrms for rated mains voltage ≤ 1000 Vrms I – IV I – IV I – IV I – III Climatic Classification 40/105/21 Pollution Degree (DIN VDE 0110/39) 2 Unit Maximum Working Insulation Voltage VIORM 1414 Vpeak Input to Output Test Voltage, Method b** VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial discharge < 5 pC VPR 2652 Vpeak Input to Output Test Voltage, Method a** VIORM x 1.6 = VPR, Type and Sample Test, tm = 10 sec, Partial discharge < 5 pC VPR 2262 Vpeak Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) VIOTM 8000 Vpeak Case Temperature TS 175 °C Input Current IS, INPUT 400 mA Output Power PS, OUTPUT 1200 mW Insulation Resistance at TS, VIO = 500 V RS >109 W Safety-limiting values – maximum values allowed in the event of a failure. * Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. Surface mount classification is class A in accordance with CECCOO802. ** Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section IEC/EN/ DIN EN 60747-5-5, for a detailed description of Method a and Method b partial discharge test profiles. Table 2. Insulation and Safety Related Specifications Parameter Symbol ACPL-339J Units Conditions Minimum External Air Gap (Clearance) L(101) 8.3 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (Creepage) L(102) 8.3 mm Measured from input terminals to output terminals, shortest distance path along body. 0.5 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. >175 V DIN IEC 112/VDE 0303 Part 1 Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group 4 CTI IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Table 3. Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature TS -55 125 °C Operating Temperature TA -40 105 °C Output IC Junction Temperature TJ 125 °C Average Input Current IF(AVG) 25 mA Peak Transient Input Current (< 1 µs pulse width, 300 pps) IF(TRAN) 1.0 A Reverse Input Voltage VR 5 V “High” Peak Output Current IOH(PEAK) 5.5 A 2 “Low” Peak Output Current IOL(PEAK) 5.5 A 2 Positive Input Supply Voltage VCC1 7 V FAULT Output Current IFAULT 8 mA FAULT Pin Voltage VFAULT -0.5 VCC1 V Total Output Supply Voltage (VCC2 – VEE) 0 35 V Negative Output Supply Voltage (VE – VEE) 0 17 V Positive Output Supply Voltage (VCC2 – VE) 0 35 – (VE – VEE) V Input Current (Rise/Fall Time) tr(IN)/tf(IN) 500 ns High Side Output Voltage VOUTP(PEAK) VE – 0.5 VCC2 + 0.5 V Low Side Output Voltage VOUTN(PEAK) VEE – 0.5 VE + 0.5 V DESAT Voltage VDESAT VE – 0.5 VCC2 + 0.5 V VGMOS Voltage VGMOS VEE – 0.5 VE + 0.5 V Output IC Power Dissipation PO 600 mW 3 Input LED Power Dissipation PI 150 mW 4 0 Note 1 Notes: 1. Derate linearly above 70° C free-air temperature at a rate of 0.3 mA/°C. 2. Maximum pulse width = 10 µs 3. Derate linearly above 95° C free-air temperature at a rate of 20 mW/°C. 4. Derate linearly above 95° C free-air temperature at a rate of 4 mW/°C. The maximum LED junction temperature should not exceed 125° C. Table 4. Recommended Operating Conditions Parameter Symbol Min. Max. Units Operating Temperature TA -40 105 °C Positive Input Supply Voltage VCC1 3 5.5 V Total Output Supply Voltage (VCC2 – VEE) 21 30 V Negative Output Supply Voltage (VE – VEE) 6 15 V Positive Output Supply Voltage (VCC2 – VE) 15 30 – (VE – VEE) V Input Current (ON) IF(ON) 6 10 mA Input Voltage (OFF) VF(OFF) -3.6 0.8 V 5 Note Table 5. Electrical Specifications (DC) Unless otherwise noted, all typical values at TA = 25° C, VCC1 = 3.3 V or 5 V, VCC2 – VE = 15 V, VE – VEE = 8 V; all Minimum/ Maximum specifications are at Recommended Operating Conditions. Parameter Symbol Min. VOUTP High Level Output Current IOUTPH VOUTP Low Level Output Current Units Test Conditions Fig. Note -1 A VCC2 – VOUTP ≤ 15 V 3 1 IOUTPL 1 A VOUTP – VE ≤ 15 V 4 1 VOUTN High Level Output Current IOUTNH -1 A VE – VOUTN ≤ 8 V 3 1 VOUTN Low Level Output Current IOUTNL 1 A VOUTN - VEE ≤ 8 V 4 1 VOUTP High Level Output RDSON ROUTPH 3.5 7 Ω IOUTP = -1 A, VF = 0 V 3, 5 1 VOUTP Low Level Output RDSON ROUTPL 1.5 4 Ω IOUTP = 1 A, IF = 8 mA 4, 6 1 VOUTN High Level Output RDSON ROUTNH 3.5 7 Ω IOUTN = -1 A, VF = 0 V 3, 5 1 VOUTN Low Level Output RDSON ROUTNL 1.5 4 Ω IOUTN = 1 A, IF = 8 mA 4, 6 1 VOUTP High Level Output Voltage VOUTPH V IOUTP = -100 mA, VF = 0 V 1 2, 4, 5 VOUTP Low Level Output Voltage VOUTPL V IOUTP = 100 mA, IF = 8 mA 2 VOUTN High Level Output Voltage VOUTNH V IOUTN = -100 mA, VF = 0 V 1 VOUTN Low Level Output Voltage VOUTNL V IOUTN = 100 mA, IF = 8 mA 2 VGMOS High Level Output Current IOUTGH -80 mA VE – VGMOS ≤ 8 V, IF = 8 mA, DESAT = Open VGMOS Low Level Output Current IOUTGL 80 mA VGMOS – VEE ≤ 8 V, VF = 0 V, DESAT = Open VGMOS High Level Output RDSON ROUTGH 22 30 Ω IOUTG = -80 mA, IF = 8 mA 7 VGMOS Low Level Output RDSON ROUTGL 6 10 Ω IOUTN = 80 mA, VF = 0 V, DESAT = Open 8 VGMOS High Level Output Voltage VOUTGH VE V IOUTG = 0 mA, IF = 8 mA, DESAT = Open VGMOS Low Level Output Voltage VOUTGL VEE V IOUTN = 0 mA, VF = 0 V, DESAT = Open High Level Output Supply Current (VCC2) ICC2H 8.5 12 mA VF = 0 V, No Load 9, 10 Low Level Output Supply Current (VCC2) ICC2L 8.5 12 mA IF = 8 mA, No Load, 9, 10 High Level Output Supply Current (VEE) IEEH 8 11 mA VF = 0 V, No Load 11, 12 Low Level Output Supply Current (VEE) IEEL 8 11 mA IF = 8 mA, No Load 11, 12 Threshold Input Current Low to High IFLH 1.3 5 mA No Load, VOUTP – VE < 5 V, VOUTN – VEE < 1 V 13, 14 Threshold Input Voltage High to Low VFHL V No Load, VOUTP – VE > 5 V, VOUTN – VEE > 1 V 6 Typ. Max. VCC2 – 0.60 VCC2 – 0.30 VE + 0.14 VE – 0.60 VE – 0.30 VEE + 0.12 0.8 VE + 0.50 VEE + 0.60 3, 4, 5 Table 5. Electrical Specifications (DC) (continued) Unless otherwise noted, all typical values at TA = 25° C, VCC1 = 3.3 V or 5 V, VCC2 – VE = 15 V, VE – VEE = 8 V; all Minimum/ Maximum specifications are at Recommended Operating Conditions. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Input Forward Voltage VF 1.2 1.55 1.95 V IF = 8 mA Temperature Coefficient of Input Forward Voltage ΔVF/ΔTA mV/°C IF = 8 mA Input Reverse Breakdown Voltage BVR V IR = 100 mA Input Capacitance CIN pF f = 1 MHz, VF = 0 V UVLO_P Threshold, VCC2-VE VUVLOP+ 12 13 14 V IF = 8 mA, VOUTP – VE < 5 V 31 2, 5, 6 VUVLOP- 11 12 13 V IF = 8 mA, VOUTP – VE > 5 V 31 3, 5, 7 UVLO_P Hysteresis, VCC2-VE VUVLOP+ - VUVLOP- UVLO_N Threshold, VE-VEE VUVLON+ 4.8 5.4 6 V IF = 8 mA, VOUTN – VEE < 1 V 31 2, 5, 8 VUVLON- 4.7 5 5.7 V IF = 8 mA, VOUTN – VEE > 1 V 31 3, 5, 9 UVLO_N Hysteresis, VE-VEE VUVLON+ - VUVLON- DESAT Threshold VDESAT 7.5 8 9 V VCC2 – VE > VUVLOPand VE – VEE > VUVLON- 15 5 Blanking Capacitor Charging Current ICHG 0.15 0.25 0.36 mA VDESAT = 2 V 16 5, 10 DESAT Low Voltage when Blanking Capacitor Discharge VDSCHG 1.1 3 V IDSCHG = 10 mA FAULT Logic Low Output Voltage VFAULTL 0.10 0.25 V VDESAT = 0 V, RF = 10 kΩ, CF = 1 nF, VCC1 = 5 V or 3.3 V FAULT Logic High Output Voltage VFAULTH VCC1 V DESAT = Open, RF = 10 kΩ, CF = 1 nF, VCC1 = 5 V or 3.3 V FAULT Logic Low Output Current IFAULTL 0.25 mA VFAULT = 0.15 V, VCC1 = 5 V or 3.3 V FAULT Logic High Output Current IFAULTH 0.2 µA VFAULT = VCC1 = 5 V or 3.3 V -1.7 5 70 1 V 0.3 V 1 5, 10 Notes: 1. Output is sourced at -1.0 A / 1.0 A with a maximum pulse width = 10 μs. 2. 15 V is the recommended minimum operating positive supply voltage (VCC2 – VE) to ensure adequate margin in excess of the maximum VUVLOP+ threshold of 13.5 V. For High Level Output Voltage testing, VOUTP is measured with a 50 ms pulse load current. When driving capacitive loads, VOUTP will approach VCC as IOUTPH approaches zero units. 3. 6.6 V is the recommended minimum operating positive supply voltage (VE – VEE) to ensure adequate margin in excess of the maximum VUVLON+ threshold of 5.6 V. For High Level Output Voltage testing, VOUTN is measured with a 50 ms pulse load current. When driving capacitive loads, VOUTN will approach VE as IOUTNH approaches zero units. 4. Maximum pulse width = 1.0 ms. 5. Once VOUTP is allowed to go low (VCC2 – VE > VUVLOP+) and VOUTN is allowed to go high (VE – VEE > VUVLON+), the DESAT detection feature of the ACPL-339J will be the primary source of IGBT protection. UVLO is needed to ensure DESAT is functional. Once VCC2 – VE > VUVLOP+ and VE – VEE > VUVLON+, DESAT will remain functional until VCC2 – VE < VUVLOP- or VE – VEE < VUVLON-,. Thus, the DESAT detection and UVLO features of the ACPL-339J work in conjunction to ensure constant IGBT protection. 6. This is the “increasing” (i.e. turn-on or “positive going” direction) of VCC2 – VE. 7. This is the “decreasing” (i.e. turn-off or “negative going” direction) of VCC2 – VE. 8. This is the “increasing” (i.e. turn-on or “positive going” direction) of VEE – VE. 9. This is the “decreasing” (i.e. turn-ff or “negative going” direction) of VEE – VE. 10. See the DESAT fault detection blanking time section in the applications notes at the end of this data sheet for further details. 7 Table 6. Switching Specifications (AC) Unless otherwise noted, all typical values at TA = 25° C, VCC1 = 3.3 V or 5 V, and VCC2 – VE = 15 V, VE – VEE = 8 V; all Minimum/ Maximum specifications are at Recommended Operating Conditions. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Propagation Delay Time to High Output Level tPLH 100 180 300 ns 17, 18, 30 1 Propagation Delay Time to Low Output Level tPHL 100 150 300 ns CP = CN = 4 nF, f = 20 kHz, Duty Cycle = 50%, IF = 6 mA to 10 mA 17, 18, 30 1 Pulse Width Distortion PWD 150 25 150 ns Propagation Delay Difference Between Any Two Parts PDD (tPLH – tPHL) -200 200 ns Propagation Delay Skew tPSK 170 ns LED OFF to 90% of VOUTP tDP 50 150 250 ns 17,18, 30 LED ON to 10% of VOUTN tDN 50 125 250 ns 17,18, 30 Non-overlap Time Low to High tNLH 30 ns 25, 30 Non-overlap Time High to Low tNHL 20 ns 25, 30 10% to 90% Rise Time on VOUTP tPR 40 ns 90% to 10% Fall Time on VOUTP tPF 40 ns 10% to 90% Rise Time on VOUTN tNR 40 ns 90% to 10% Fall Time on VOUTN tNF 30 ns Delay time from DESAT threshold to 50% of High VGMOS t1 250 500 ns Delay time from DESAT threshold to 50% of High VOUTP t2 250 500 ns Delay time from DESAT threshold to 50% of High FAULT t3 8.5 11 μs RF = 10 kΩ, CF = 1 nF, 20, 28, 29 VCC1 = 3.3 V or 5 V, f = 250 Hz, Duty Cycle = 50%, IF = 8 mA Delay from 50% of VGMOS to 50% of VOUTN t4 11 ns CP = CN = 4 nF, CG = 1 nF, f = 250 Hz, Duty Cycle = 50%, IF = 8 mA Mute time tMUTE 0.75 1 ms f = 700 Hz, Duty Cycle 24, 28, 29 = 50%, IF = 8 mA 4 Output High Level Common Mode Transient Immunity |CMH| 25 35 kV/μs TA = 25° C, VCM = 1500 V, VCC1 = 5 V, CF = 1 nF, RF = 10 kΩ, IF = 8 mA with split resistors 5 Output Low Level Common Mode Transient Immunity |CML| 25 35 kV/μs TA = 25° C, VCM = 1500 V, VCC1 = 5 V, CF = 1 nF, RF = 10 kΩ, VF = 0 V 6 1.5 2 36, 37 3 7 CP = CN = 4 nF, f = 20 kHz, Duty Cycle = 50%, IF = 8 mA 30 30 30 30 CP = CN = 4 nF, CG = 1 nF, f = 250 Hz, Duty Cycle = 50%, IF = 8 mA 19, 22, 28, 29 19, 28, 29 21, 23, 28, 29 Notes: 1. This load condition approximates the gate load of a 60V/5A MOSFET 2. Pulse Width Distortion (PWD) is defined as |tPHL – tPLH| for any given unit. 3. The difference between tPHL and tPLH between any two ACPL-339J parts under the same test conditions. 4. Auto Reset: This is the minimum amount of time when VOUTP will be asserted high, VOUTN asserted low, VGMOS asserted high and FAULT asserted high, after DESAT threshold is exceeded. See the Description of Operation (Auto Reset) topic in the application information section. 5. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in the high state (i.e., VOUTP – VE > 12 V, VOUTN – VEE > 5 V or FAULT > 2 V). A 1 nF and a 10 kΩ pull-up resistor is needed in fault detection mode. 6. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e., VOUTP – VE < 1.0 V, VOUTN – VEE < 1.0 V or FAULT < 0.8 V). 7. tPSK is equal to the worst-case difference in tPHL or tPLH that will be seen between units under the same test condition. 8 Table 7. Package Characteristics Parameter Symbol Min. Input-Output Momentary Withstand Voltage VISO 5000 Input-Output Resistance RI-O Input-Output Capacitance CI-O Typ. Max. Units Test Conditions Fig. Note Vrms RH < 50%, t = 1 min., TA = 25° C 1, 2 > 109 W VI-O = 500 V 2 1.3 pF freq =1 MHz Notes 1. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 Vrms for 1 second. This test is performed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-5 Insulation Characteristic Table, if applicable. 2. Device considered a two-terminal device: pins 1 to 8 are shorted together and pins 9 to 16 are shorted together. 0.35 LOW OUTPUT VOLTAGE DROP - V HIGH OUTPUT VOLTAGE DROP - V 0.4 0.3 0.25 0.2 0.15 0.1 0 VOUTPH-VCC2 VOUTNH-VE VF = 0 V IOUT = -100 mA 0.05 -40 -20 0 25 50 TA - TEMPERATURE - °C 85 105 Figure 1. VOUTPH/VOUTNH vs. temperature -0.5 85 105 2.5 OUTPUT LOW CURRENT - A OUTPUT HIGH CURRENT - A 0 25 50 TA - TEMPERATURE - °C 3 IOUTPH IOUTNH -1 -1.5 -2 VF = 0 V TA = 25° C 0 -2 -4 -6 -8 -10 VOUTPH-VCC2/VOUTNH-VE - V Figure 3. IOUTPH/IOUTNH vs.VOUTPH/VOUTNH 9 VOUTPL-VE VOUTNL-VEE Figure 2. VOUTPL/VOUTNL vs. temperature 0 -2.5 0.2 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 IF = 8 mA 0.02 IOUT = 100 mA 0 -40 -20 -12 -14 -15 2 1.5 1 0.5 0 IOUTPL IOUTNL IF = 8 mA TA = 25° C 0 2 4 6 8 10 VOUTPL-VE/VOUTNL-VEEE - V Figure 4. IOUTPL/IOUTNL vs.VOUTPL/VOUTNL 12 14 15 2.5 2 LOW OUTPUT RDSON - Ω HIGH OUTPUT RDSON - Ω 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 ROUTPH ROUTNH VF = 0 V IOUT = -1 A -40 -20 0 25 50 TA - TEMPERATURE - °C 85 20 15 10 IF = 8 mA IOUTG = -80 mA -20 0 25 50 TA - TEMPERATURE - °C 85 105 -40 -20 0 25 50 TA - TEMPERATURE - °C 85 105 85 105 VF = 0 V IOUTG = -80 mA DESAT = OPEN -40 -20 0 25 50 TA - TEMPERATURE - °C Figure 8. ROUTGL vs. temperature 8.6 8.55 ICC2H ICC2L VF = 0 V (ICC2H) IF = 8 mA (ICC2L) -40 -20 Figure 9. ICC2 vs. temperature 10 10 9 8 7 6 5 4 3 2 1 0 VCC2 SUPPLY CURRENT - mA VCC2 SUPPLY CURRENT - mA Figure 7. ROUTGH vs. temperature 8.8 8.75 8.7 8.65 8.6 8.55 8.5 8.45 8.4 8.35 8.3 0 ROUTPL ROUTNL IF = 8 mA IOUT = 1 A VGMOS LOW OUTPUT RDSON - Ω VGMOS HIGH OUTPUT RDSON - Ω 25 -40 0.5 Figure 6. ROUTPL/ROUTNL vs. temperature 30 0 1 105 Figure 5. ROUTPH/ROUTNH vs. temperature 5 1.5 0 25 50 TA - TEMPERATURE - °C 85 8.5 8.45 8.4 8.35 8.3 IF = 8 mA (ICC2L) VF = 0 V (ICC2H) TA = 25° C VE-VEE = 6 V 8.25 8.2 105 8.15 15 16 Figure 10. ICC2 vs. VCC2 17 ICC2L ICC2H 18 19 20 VCC2-VE - V 21 22 23 24 8.3 8.5 8.25 8.45 8.2 VEE SUPPLY CURRENT - mA VEE SUPPLY CURRENT - mA 8.55 8.4 8.35 8.3 8.25 8.15 IEEH IEEL VF = 0 V (IEEH) IF = 8 mA (IEEL) 8.2 -40 -20 0 25 50 TA - TEMPERATURE - °C 85 8.05 8 7.9 105 10 LOW TO HIGH CURRENT THRESHOLD - mA 15 7 8 9 10 11 VE-VEE - V 12 13 14 15 TA = 25° C 5 0 -5 0 0.5 1 1.5 2 2.5 LOW TO HIGH INPUT CURRENT THRESHOLD - mA 2 1.5 1 0.5 3 -40 -20 0 25 50 TA - TEMPERATURE - °C 85 105 85 105 ICHGB LANKING CAPACITOR CHARGING CURRENT - µA 235 8.16 8.14 8.12 8.1 8.08 8.06 8.04 0 IFLH ON IFLH OFF Figure 14. IFLH vs. temperature 8.18 VDESAT DESAT THRESHOLD - V 6 IEEL IEEH 2.5 VOUTP VOUTN Figure 13. VOUTPH/VOUTNH vs. IFLH -40 -20 0 25 50 TA - TEMPERATURE - °C Figure 15. VDESAT vs. temperature 11 IF = 8 mA (IEEL) VF = 0 V (IEEH) TA = 25° C VCC2-VE = 15 V Figure 12. IEE vs. VEE 20 VOUTP/VOUTN OUT VOLTAGE - V 8.1 7.95 Figure 11. IEE vs. temperature -10 8.15 85 105 230 225 220 215 210 -40 -20 Figure 16. ICHG vs. temperature 0 25 50 TA - TEMPERATURE - °C 250 tP/tD PROPAGATION DELAY - ns tP/tD PROPAGATION DELAY - ns 250 200 150 100 50 0 tPHL tPLH tDP tDN CP/CN = 4 nF f = 20 kHz DC = 50% -40 -20 0 25 50 TA - TEMPERATURE - °C 85 250 t3 DELAY TIME - ns t1/t2 DELAY TIME - ns 9.5 200 150 100 CP/CN = 4 nF f = 250 Hz DC = 50% -20 85 8 400 12 350 t1 DELAY TIME - ns 14 10 8 6 -20 Figure 21. t4 vs. temperature CF = 1 nF RF = 10 kΩ f = 250 Hz DC = 50% -20 0 25 50 TA - TEMPERATURE - °C 105 250 200 150 CP/CN = 4 nF IF = 8 mA TA = 25° C f = 250 Hz DC = 50% 50 0 25 50 TA - TEMPERATURE - °C 85 300 100 CG = 1 nF f = 250 Hz DC = 50% -40 12 Figure 20. t3 vs. temperature 450 0 10 8.5 16 2 4 6 8 CP/CN - LOAD CAPACITANCE - nF 9 7 -40 105 Figure 19. t1 /t2 vs. temperature 4 2 7.5 t1 t2 0 25 50 TA - TEMPERATURE - °C 0 Figure 18. tP /tD vs. CP/CN 300 -40 tPHL tPLH tDP tDN IF = 8 mA TA = 25° C f = 20 kHz DC = 50% 50 10 0 t4 DELAY TIME - ns 100 350 50 12 150 0 105 Figure 17. tP /tD vs. temperature 200 85 105 0 1 2 Figure 22. t1 vs. CG 3 4 5 6 7 8 CG - LOAD CAPACITANCE - nF 9 10 40 tMUTE MUTE TIME - ms t4 DELAY TIME - ns 35 30 25 20 15 IF = 8 mA TA = 25° C f = 250 Hz DC = 50% 10 5 0 1 2 3 4 5 6 7 8 CN/CG - LOAD CAPACITANCE - nF 9 10 Figure 23. t4 vs. CN /CG tNLH/tNHL NON-OVERLAP TIME - ns 35 30 25 20 15 10 CP/CN = 4 nF f = 20 kHz DC = 50% 5 0 0 25 50 TA - TEMPERATURE - °C Figure 25. tNLH/tNHL vs. temperature 13 -40 -20 tNLH tNHL 85 105 1.08 1.06 1.04 1.02 1 0.98 0.96 0.94 0.92 0.9 0.88 0.86 -40 f = 700 Hz DC = 50% -20 0 25 50 TA - TEMPERATURE - °C Figure 24. tMUTE vs. temperature 85 105 Applications Information Product Overview Description 13 VCC2 UVLO_P ANODE CATHODE 3 D R I V E R 2, 4 LED1 Drive Logic & Overlap Protection 12 16 UVLO_N SHIELD 11 VCC1 FAULT 6 9 15 DESAT VGND1 5, 8 VE VOUTN VEE LED2 7 VOUTP 14 DESAT VGMOS SHIELD Figure 26. Block Diagram of ACPL-339J Recommended Application Circuit 1 NC VE 16 CBLANK 100 Ω 1 µF 2 CATHODE DESAT 15 3 ANODE VGMOS 14 4 CATHODE 1 µF R + _ + _ 0.3 µF R VCC2 13 5 VGND1 VOUTP 12 6 VCC1 VOUTN 11 RF = 10 kΩ 7 FAULT NC 10 8 VGND1 VEE CF = 1 nF ^RP DDESAT 330 Ω *MP1 + _ RS = 330 Ω RGP Q1 MN2 ^RN RGN *MN1 10 µF + _ 9 MP1 = Si7415DN/Si7465DP MN1 = Si7414DN/Si7848DP MN2 = Si2318 * MP1 and MN1 equivalent CLOAD to be < 15 nF ^ RP and RN are not required unless capacitive loading of MP1 or MN1 draws > 4 A of peak current. Figure 27. Typical de-saturation protected gate drive circuit, non-inverting 14 Q2 + VCE _ Output Control The outputs (VOUTP, VOUTN, VGMOS and FAULT) of the ACPL-339J are controlled by the combination of IF, UVLO and DESAT conditions. Once UVLO_P and UVLO_N is not active (VCC2 - VE > VUVLOP+, VE - VEE > VUVLON+), VOUTP is allowed to go low and VOUTN is allowed to go high. Thereafter, the DESAT (pin 15) detection feature of the ACPL-339J will be the primary source of IGBT/MOSFET protection. DESAT will remain functional until VCC2 - VE is decreased below VUVLOP- or VE - VEE is decreased below VUVLON-. Thus, the DESAT detection and UVLO features of the ACPL-339J work alternatively to ensure constant IGBT/MOSFET protection. IF UVLO_P and UVLO_N DESAT Function Pin 7 (FAULT) Output VOUTP VOUTN VGMOS X Active Not Active VCC1 VCC2 VE VE ON Not Active Active (with DESAT fault) VCC1 VCC2 VEE VE ON Not Active Active (no DESAT fault) VGND1 VE VEE VEE OFF Not Active Not Active VGND1 VCC2 VE VEE Description of Operation during DESAT Fault Condition The DESAT pin monitors the IGBT Vce voltage. The DESAT fault detection circuitry must remain disabled for a short time period following the turn-on of the IGBT to allow the collector voltage to fall below the DESAT threshold. This time period, called the DESAT blanking time, is controlled by the internal DESAT charge current, the DESAT voltage threshold, and the external DESAT capacitor. The nominal blanking time is calculated in terms of external capacitance (CBLANK), FAULT threshold voltage (VDESAT ), and DESAT charge current (ICHG) as TBLANK = CBLANK x VDESAT/ ICHG. The nominal blanking time with the recommended 100 pF capacitor is 100 pF * 8 V/250 µA = 3.2 µsec. The capacitance value can be scaled slightly to adjust the blanking time, though a value smaller than 100 pF is not recommended. This nominal blanking time also represents the longest time it will take for the ACPL-339J to respond to a DESAT fault condition. Once DESAT fault is detected and after TBLANK time, both VOUTP and VOUTN will turn off the respective external MP1 and MN1 and VGMOS switches from low to high, turning on an external MN2 pull down device, in order to ‘softly’ turn-off the IGBT. Also activated is an internal feedback channel which brings the FAULT output from low to high for the purpose of notifying the micro-controller of the fault condition. 15 Once fault is detected, the output will be muted for TMUTE time. All input LED signals will be ignored during the mute period to allow the driver to completely soft shut down the IGBT. The fault is auto-reset upon the 1ms (typical) mute time (TMUTE) timeout or upon LED INPUT high to low transition, whichever is later. In this way, there is a minimum timeout but also the flexibility of lengthening the timeout freely. See Figure 28 and 29. Soft IGBT Shut Down during Fault Condition When a DESAT fault is detected, VGMOS switches from low to high, turning on an external MN2 pull down device. MN2 slowly discharges the IGBT gate at a decay rate corresponding to the RC constant of RS and CIN (IGBT input capacitance). Based on a RS of 330 Ω and CIN of 10 nF, the entire soft shut down will decay in 4.8 * 330 Ω * 10 nF = 15.8 µs. Soft shut down prevents fast changes in the collector current that can cause damaging voltage spikes due to lead and wire inductance. IF LED ON LED OFF 8V VDESAT VGMOS t1 Soft Shut Down VG(IGBT) VOUTN Ext NMOS(MN1) OFF Ext NMOS ON Ext NMOS OFF t4 VOUTP FAULT Ext PMOS ON Ext PMOS(MP1) OFF t2 t3 Internal DESAT TMUTE Timer tMUTE Figure 28. DESAT Fault State Timing Diagram with LED turn OFF before the TMUTE timeout IF LED ON LED OFF 8V VDESAT VGMOS t1 Soft Shut Down VG(IGBT) VOUTN Ext NMOS(MN1) OFF Ext NMOS ON t4 VOUTP FAULT Internal DESAT TMUTE Timer Ext PMOS(MP1) OFF t2 t3 tMUTE Figure 29. Desat Fault State Timing Diagram with LED OFF after the TMUTE timeout 16 Timing Diagram & Cross-Conduction Scheme IF tDP tPHL VOUTP tPR tPF VCC2 – VTH(PMOS) Ext PMOS(MP1) OFF tNLH tNR tNHL tNF Ext NMOS (MN1) ON VOUTN tPLH VG(IGBT) VEE + VTH(NMOS) tDN IGBT OFF IGBT ON IGBT OFF Figure 30. Timing diagram and Cross Conduction Scheme The MOS Driver monitors VOUTP & VOUTN to detect for VCC2VOUTP or VOUTN-VEE equals V TH(MOS) during the respective external MOSFET’s turn-off transition. Upon detection, the complimentary VOUT is turned on after some inherent delay tNLH/tNHL. supply is lower than under voltage lockout (UVLO) threshold gate driver output will shut off to protect IGBT from low voltage bias. ACPL-339J has two UVLO logic blocks, UVLO_P and UVLO_N to control the VOUTP and VOUTN respectively. The UVLO control logic takes precedence over input IF and DESAT. In another words, IF and DESAT are ignored when VCC2 and VEE supplies are not sufficient causing UVLO clamp to be active. Both VUVLOP+ and VUVLON+ will need to be crossed before the clamp can be released. Thereafter, VOUTP and VOUTN will respond to IF and DESAT accordingly. Description of Under Voltage Lock Out Insufficient gate voltage to IGBT can increase turn on resistance of IGBT, resulting in large power loss and IGBT damage due to high heat dissipation. ACPL-339J monitors the output power supply constantly. When output power LED1 ON LED1 ON VCC2 VCC2 15 V 15 V VUVLOP+ VUVLOP+ VE time VUVLON+ 8V VE VUVLON+ 8V VEE VEE VOUTP VOUTP 15 V 15 V VE time VE 8V 8V VOUTN VOUTN FAULT FAULT VCC1 VCC1 VGND1 Figure 31. UVLO, VOUT and FAULT logic diagram 17 time time VGND1 time time Drive and Shutdown MOSFET Selection The MOSFETs, MP1 and MN1 driving strength can be estimated by the gate charge and desired charge time needed. The equation below shows an example of this: Qg = ICHARGE x TCHARGE Qg is the total gate charge that can be picked readily from the IGBT data sheets. For a 1200/50 A IGBT, the typical Qg is approximately 300 nC and for desired charging time of 200 ns, the ICHARGE will be, ICHARGE = 300 nC / 200 ns = 1.5 A The charging current calculated is an average current. The peak gate current of the MOSFET driver can be estimated using the rule of thumb of doubling the ICHARGE. So for this example, a 3 A peak current MOSFET driver rating will be appropriate. The following table lists some recommended MOSFET ratings and part numbers suitable for their respective IGBT class. Applications IGBT Class Qg Estimated Peak Charging Current MN1 MP1 MN2 Low Power 1200 V / 50 A 300 nC 3A Sanyo ECH8619 Sanyo ECH8619 Vishay SI2308 Mid Power 1200 V / 300 A 2000 nC 8A Vishay SI7414 Vishay SI7415 Vishay SI2308 High Power 1200 V / 600 A 4000 nC 16A Vishay SIS434 Vishay SI7611 Fairchild FDC5612 Selecting the Gate Resistor (RG) The IGBT switching time is determined by the charging and discharging of the gate of the IGBT. Higher gate peak current will decrease the turn-on and turn-off time and hence reduce the the switching losses. The charging and discharging currents are controlled by the gate resistors RGP and RGN respectively. The RG must be able to limit the peak current below the maximum allowed for the PMOS(MP1) and NMOS(MN1). The internal RDSON of MP1 and MN1 must be taken into account when calculating the peak current. RGP ≥ VCC – VEE – RDSONP IOP(MAX) RGN ≥ VCC – VEE – RDSONN ION(MAX) Other Recommended Components The application circuit in Figure 27 includes a DESAT pin protection resistor, FAULT pin capacitor and pull-up resistor, and false FAULT prevention diodes. 18 Split Resistors Input LED Drive Circuit Figure 32 shows the recommended drive circuit that gives optimum common-mode rejection. The two current setting resistors balance the common mode impedances at the LED’s anode and cathode. This helps to equalize the common mode voltage change at the anode and cathode. VDD = 5.0 V: R1 = 287 Ω ±1% R2 = 143 Ω ±1% R1/R2 ≈ 2 R1 µC In the recommended appli­cation circuit shown in Figure 27, the voltage on pin 15 (DESAT) is VDESAT = VF + VCE, (where VF is the forward ON voltage of DDESAT and VCE is the IGBT collector-to-emit­ter voltage). The value of VCE which triggers DESAT to signal a FAULT condition, is nominally 8 V – VF. If desired, this DESAT threshold voltage can be decreased by using multiple DESAT diodes or low voltage zener diode in series. If n is the number of DE­SAT diodes, the nominal threshold value becomes VCE,FAULT(TH) = 8 V – n x VF. If a Zener diode is used, the nominal threshold value becomes VCE,FAULT(TH) = 8 V – VF – Vz. In the case of using two diodes instead of one, diodes with half of the total required maximum reverse-voltage rating may be chosen. 1 NC +5 V R2 This results in ICHARGE = CD-DESAT x dVCE/dt charging current which will charge the blanking capacitor, CBLANK. In order to minimize this charging current and avoid false DESAT triggering, it is best to use fast response diodes. Listed in the below table are fast-recovery diodes that are suitable for use as a DESAT diode (DDESAT). 2 CATHODE 3 ANODE 4 CATHODE 5 VGND1 Figure 32. Split Resistors Input LED Drive Circuit DESAT Diode and DESAT Threshold The DESAT diode’s function is to conduct forward cur­rent, allowing sensing of the IGBT’s saturated collector-toemitter voltage, VCESAT, (when the IGBT is “on”) and to block high voltages (when the IGBT is “off”). During IGBT switching off and towards the end of the forward conduction of the DESAT diode, a reverse current flow for short time. This reverse recovery effect causes the diode not able to achieve its blocking capability until the mobile charge in the junction is depleted. During this time, there is commonly a very high dVCE/dt voltage ramp rate across the IGBT’s collector-to-emitter. VE 16 CBLANK 100 Ω DZENER DDESAT DESAT 15 VGMOS 14 Q1 Figure 33. DESAT Diode and DESAT threshold Part Number Manufacturer trr(ns) Max. Reverse Voltage Rating, VRRM (V) VF @ 0.25 mA (V) Package Type MUR1100E On-Semi 75 1000 < 0.5 59-10 (axial leaded) MURA160T3G On-Semi 75 600 < 0.7 Case 403A (SMD) USIM-E3/5AT Vishay 75 1000 < 0.6 DO-214AC (SMD) SF1600-TR-E3 VIshay 75 1600 < 0.6 SOD-57 (axial leaded) SF38 Multicomp 35 600 < 0.5 DO-201AD (axial leaded) 19 + VCE – DESAT Pin Protection Resistor FAULT Pin Capacitor and Pull-up Resistor The freewheeling of flyback diodes connected across the IGBTs can have large instantaneous forward voltage transients which greatly exceed the nominal forward voltage of the diode. This may result in a large negative voltage spike on the DESAT pin which will draw substantial current out of the driver if protection is not used. To limit this current to levels that will not damage the driver IC, a 100 ohm resistor should be inserted in series with the DESAT diode. The added resistance will not alter the DESAT threshold or the DESAT blanking time. UVLO fault is feedback to the FAULT pin through LED2. If LED2 is normally-off during normal operation, a VCC2 or VEE power supplies fault might result in insufficient drive current to turn on LED2 to report the UVLO fault. To avoid such a condition, LED2 need to be normally-on during normal operations. To reduce power consumption, LED2 operates at 50% duty cycle at a frequency of 5 MHz provided by an internal oscillator. A RC network at the FAULT pin is required to filter this oscillation to read a stable “low” for no fault condition. False Fault Prevention Diodes The RC network consists of a FAULT pin capacitor, CF and a pull-up resistor RF. To achieve effective filtering and high CMR, a 1 nF capacitor should be connected between the FAULT pin and ground, and a 10 KΩ pull-up resistor between FAULT pin and VCC1. One of the situations that may cause the driver to generate a false fault signal is if the substrate diode of the driver becomes forward biased. This can happen if the reverse recovery spikes coming from the IGBT freewheeling diodes bring the DESAT pin below ground. Hence the DESAT pin voltage will be ‘brought’ above the threshold voltage. This negative going voltage spikes is typically generated by inductive loads or reverse recovery spikes of the IGBT/MOSFETs free-wheeling diodes. In order to prevent a false fault signal, it is highly recommended to connect a zener diode and schottky diode across the DESAT pin and VE pin This circuit solution is shown in Figure 34. The schottky diode will prevent the substrate diode of the gate driver optocoupler from being forward biased while the zener diode (value around 7.5 to 8 V) is used to prevent any positive high transient voltage to affect the DESAT pin. VE 16 DESAT 15 VGMOS 14 CBLANK 100 Ω 47 kΩ + VCE – 5V + _ IC1 0.3 µF RF = 10 kΩ 6 VCC1 7 FAULT CF = 1 nF 8 VGND1 FAULT 47 kΩ Q1 20 4.7 kΩ 4.7 kΩ DDESAT 10 V Zener Schottky 1N5925A Diode MBR0540 Figure 34. False fault prevention diodes Due to the active “high” FAULT logic, the FAULT pins of more than one ACPL-339J cannot be tied together to achieve a common FAULT signal for the controller. An ‘OR’ing circuit shown in Figure 35 can be used to overcome the problem. 5 V 0.3 µF + _ RF = 10 kΩ ACPL-339J IC2 6 VCC1 7 FAULT CF = 1 nF Figure 35. ‘OR’ing the FAULT outputs 8 VGND1 ACPL-339J Dead Time and Propagation Delay Specifications The ACPL-339J includes a Propagation Delay Difference (PDD) specification intended to help designers minimize “dead time” in their power inverter designs. Dead time is the time period during which both the high and low side power transistors (Q1 and Q2 in Figure 37) are off. Any overlap in Q1 and Q2 conduction will result in large currents flowing through the power devices between the high and low voltage motor rails. To minimize dead time in a given design, the turn on of LED2 should be delayed (relative to the turn off of LED1) so that under worst-case conditions, transistor Q1 has just turned off when transistor Q2 turns on, as shown in Figure 36. The amount of delay necessary to achieve this condition is equal to the maximum value of the propagation delay difference specification, PDDMAX, which is specified to be 200 ns over the operating temperature range of -40° C to 105° C. LED1 IF 1 tPHL MIN VOUTP 1 VOUTN 1 tPLH MAX tPLH MAX VG(IGBT) Q1 Q1 IGBT OFF Q1 IGBT ON VG(IGBT) Q2 Q2 IGBT ON Q2 IGBT OFF tPHL MIN tPHL MIN VOUTP 2 VOUTN 2 tPLH MAX LED2 IF 2 PDD = tPLH MAX - tPHL MIN PDD = tPLH MAX - tPHL MIN Figure 36. Minimum LED skew for zero dead time 21 Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time is equivalent to the difference between the maximum and minimum propagation delay difference specifications as shown in Figure 37. The maximum dead time for the ACPL-339J is 400 ns (= 200 ns – (-200 ns)) over an operating temperature range of -40° C to 105° C. Note that the propagation delays used to calculate PDD and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical IGBTs. LED1 IF 1 tPHL MIN VOUTP 1 VOUTN 1 tPLH MIN tPLH MIN Q1 IGBT OFF VG(IGBT) Q1 Max. Dead Time = PDDMAX – PDDMIN Q2 IGBT ON VG(IGBT) Q2 tPHL MAX VOUTN 2 tPLH MIN Figure 37. Waveforms for dead time 22 Max. Dead Time = PDDMAX – PDDMIN Q2 IGBT OFF tPHL MAX VOUTP 2 LED2 IF 2 Q1 IGBT ON Thermal Model Definitions Symbol °C/W Junction to Ambient Thermal Resistance of LED1 due to heating of LED1 R11 103 Junction to Ambient Thermal Resistance of LED1 due to heating of Feedback Detector R12 24 Junction to Ambient Thermal Resistance of LED1 due to heating of LED2 R13 22 Junction to Ambient Thermal Resistance of LED1 due to heating of Output IC R14 18 Junction to Ambient Thermal Resistance of Feedback Detector due to heating of LED1 R21 22 Junction to Ambient Thermal Resistance of Feedback Detector due to heating of Feedback Detector R22 80 Junction to Ambient Thermal Resistance of Feedback Detector due to heating of LED2 R23 29 Junction to Ambient Thermal Resistance of Feedback Detector due to heating of Output IC R24 17 Junction to Ambient Thermal Resistance of LED2 due to heating of LED1 R31 21 Junction to Ambient Thermal Resistance of LED2 due to heating of Feedback Detector R32 28 Junction to Ambient Thermal Resistance of LED2 due to heating of LED2 R33 104 Junction to Ambient Thermal Resistance of LED2 due to heating of Output IC R34 24 Junction to Ambient Thermal Resistance of Output IC due to heating of LED1 R41 25 Junction to Ambient Thermal Resistance of Output IC due to heating of Feedback Detector R42 23 Junction to Ambient Thermal Resistance of Output IC due to heating of LED2 R43 33 Junction to Ambient Thermal Resistance of Output IC due to heating of Output IC R44 33 P1 : Power dissipation of LED1 (W) P2 : Power dissipation of Feedback Detector (W) P3 : Power dissipation of LED2 (W) P4 : Power dissipation of Output IC (W) T1 : Junction temperature of LED1 (°C) T2 : Junction temperature of Feedback Detector (°C) T3 : Junction temperature of LED2 (°C) T4 : Junction temperature of Output IC (°C) TA : Ambient temperature. Ambient temperatures were measured approximately 1.25 cm above optocoupler at ~25° C in still air. This thermal model assumes the device is mounted on a high conductivity test board as per JEDEC 51-7. The junction temperatures at the LED1, Feedback Detector, LED2 and Output IC junctions of the optocoupler can be calculated using the equations below. T1 = (R11 * P1 + R12 * P2 + R13 * P3 + R14 * P4) + TA T2 = (R21 * P1 + R22 * P2 + R23 * P3 + R24 * P4) + TA T3 = (R31 * P1 + R32 * P2 + R33 * P3 + R34 * P4) + TA T4 = (R41 * P1 + R42 * P2 + R43 * P3 + R44 * P4) + TA -- (1) -- (2) -- (3) -- (4) All junction temperatures should be within the absolute maximum rating of 125° C. For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2015 Avago Technologies. All rights reserved. AV02-3784EN - April 27, 2015