ACPL-796H
Optically Isolated Sigma-Delta Modulator
Data Sheet
Description
Features
The ACPL-796H is a 1-bit, second-order sigma-delta ()
modulator converts an analog input signal into a highspeed data stream with galvanic isolation based on optical
coupling technology. The ACPL-796H operates from a 5 V
power supply with dynamic range of 80 dB with an appropriate digital filter. The differential inputs of ±200 mV (full
scale ±320 mV) are ideal for direct connection to shunt
resistors or other low-level signal sources in applications
such as motor phase current measurement.
The analog input is continuously sampled by means of
sigma-delta over-sampling using external clock, coupled
across the isolation barrier, which allows synchronous
operation with any digital controller. The signal information is contained in the modulator data, as a density
of ones with data rate up to 20 MHz, and the data are
encoded and transmitted across the isolation boundary
where they are recovered and decoded into high-speed
data stream of digital ones and zeros. The original signal
information can be reconstructed with a digital filter. The
serial interface has a wide supply range of 3 V to 5.5 V.
5 MHz to 20 MHz external clock input range
1-bit, second-order sigma-delta modulator
16 bits resolution no missing codes (12 bits ENOB)
74 dB minimum SNR
3.5 V/°C maximum offset drift
±1% maximum gain error
Internal reference voltage
±200 mV linear range with single 5 V supply
3 V to 5.5 V wide supply range for digital interface
–40°C to +105°C operating temperature range
SO-16 package
25 kV/s common-mode transient immunity
Safety and regulatory approval (pending):
IEC/EN/DIN EN 60747-5-5: 1230 Vpeak working
insulation voltage
UL 1577: 5000 Vrms/1min double protection rating
CSA: Component Acceptance Notice #5
Combined with superior optical coupling technology,
the modulator delivers high noise margins and excellent
immunity against isolation-mode transients. With 0.5 mm
minimum distance through insulation (DTI), the ACPL-796H
provides reliable double protection and high working
insulation voltage, which is suitable for fail-safe designs.
This outstanding isolation performance is superior to
alternatives including devices based on capacitive- or
magnetic-coupling with DTI in micro-meter range. Offered
in an SO-16 package, the isolated ADC delivers the reliability, small size, superior isolation and over-temperature
performance motor drive designers need to accurately
measure current at much lower price compared to traditional current transducers.
Applications
The internal clock version modulators, HCPL-7860 (DIP-8/
gull wing surface mount package) and HCPL-786J (SO-16
package), are also available.
VIN −
Motor phase and rail current sensing
Power inverter current and voltage sensing
Industrial process control
Data acquisition systems
General purpose current and voltage sensing
Traditional current transducer replacements
Functional Block Diagram
VDD1
Σ−Δ
MODULATOR/
ENCODER
GND1
LED
DRIVER
DECODER
MDAT
SHIELD
BUF
VIN +
VDD2
VREF
LED
DRIVER
CLOCK
DETECTOR
SHIELD
ACPL-796H
Figure 1.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
MCLKIN
GND2
Pin Configuration and Descriptions
VDD1
16 GND2
1
VIN+ 2
15 NC
VIN– 3
14 VDD2
13 MCLKIN
GND1
4
NC
5
NC
6
11 MDAT
VDD1
7
10 NC
GND1
8
9
ACPL-796H
12 NC
GND2
Figure 2. Pin configuration.
Table 1. Pin descriptions.
Pin No.
Symbol
Description
1, 7
VDD1
Supply voltage for signal input side (analog side), relative to GND1
2
VIN+
Positive analog input, recommended input range ±200 mV
3
VIN–
Negative analog input, recommended input range ±200 mV (normally connected to GND1)
4, 8
GND1
Supply ground for signal input side
5, 6, 10, 12, 15
NC
No connection. Leave floating
9, 16
GND2
Supply ground for data output side (digital side)
11
MDAT
Modulator data output
13
MCLKIN
Modulator clock input, 5 MHz to 20 MHz
14
VDD2
Supply voltage for data output side, relative to GND2
Table 2. Ordering Information
ACPL-796H is UL recognized with 5000 Vrms/1 minute rating per UL 1577 (pending).
Part number
Option
(RoHS Compliant)
Package
-000E
ACPL-796H
-060E
Surface Mount
Tape& Reel
IEC/EN/DIN EN
60747-5-5
X
SO-16
Quantity
45 per tube
X
X
-500E
X
X
-560E
X
X
45 per tube
850 per reel
X
850 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example:
ACPL-796H-560E to order product of Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5
Safety Approval and RoHS compliance.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
2
Package Outline Drawings
16-Lead Surface Mount (SO-16)
0.457
(0.018)
LAND PATTERN RECOMMENDATION
0.64 (0.025)
1.270
(0.050)
16 15 14 13 12 11 10 9
TYPE NUMBER
DATE CODE
A 796H
YYWW
7.493 ± 0.254
(0.295 ± 0.010)
11.63 (0.458)
2.16 (0.085)
1 2 3 4 5 6 7 8
10.312 ± 0.254
(0.406 ± 0.10)
0.457
(0.018)
ALL LEADS
TO BE
COPLANAR
± 0.002
8.986 ± 0.254
(0.345 ± 0.010)
9°
3.505 ± 0.127
(0.138 ± 0.005)
0-8°
0.025 MIN.
10.160 ± 0.254
(0.408 ± 0.010)
0.203 ± 0.076
(0.008 ± 0.003)
STANDOFF
Dimensions in millimeters and (inches).
Note: Floating lead protrusion is 0.15 mm (6 mils) max.
Note: Initial and continued variation in color of the white mold compound
is normal and does not affect performance or reliability of the device.
Figure 3. 16-Lead Surface Mount.
Recommended Pb-Free IR Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
Regulatory Information
The ACPL-796H is pending for approvals by the following organizations:
IEC/EN/DIN EN 60747-5-5
CSA
Approved with Maximum Working Insulation Voltage
VIORM = 1230 Vpeak.
Approval under CSA Component Acceptance Notice #5,
File CA 88324.
UL
Approval under UL 1577, component recognition program
up to VISO = 5000 Vrms/1min. File E55361.
3
Table 3. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics[1]
Description
Symbol
Value
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 450 V rms
for rated mains voltage ≤ 600 Vrms
for rated mains voltage ≤ 1000 Vrms
Units
I-IV
I-IV
I-IV
I-IV
I-III
Climatic Classification
55/105/21
Pollution Degree (DIN VDE 0110/1.89)
2
VIORM
1230
Vpeak
Input to Output Test Voltage, Method b
VIORM × 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial Discharge < 5 pC
VPR
2306
Vpeak
Input to Output Test Voltage, Method a
VIORM × 1.6 = VPR, Type and Sample Test, tm = 10 sec,
Partial Discharge < 5 pC
VPR
1968
Vpeak
Highest Allowable Overvoltage (Transient Overvoltage, tini = 60 sec)
VIOTM
8000
Vpeak
Safety-limiting values (Maximum values allowed in the event of a failure)
Case Temperature
Input Current[2]
Output Power[2]
TS
IS,INPUT
PS,OUTPUT
175
400
600
°C
mA
mW
Insulation Resistance at TS, VIO = 500 V
RS
≥ 109
Notes:
1. Insulation characteristics are guaranteed only within the safety
maximum ratings, which must be ensured by protective circuits
within the application.
2. Safety-limiting parameters are dependent on ambient temperature.
Refer to the following figure for dependence of PS and IS on ambient
temperature.
OUTPUT POWER - PS, INPUT CURRENT - IS
Maximum Working Insulation Voltage
800
PS (mW)
IS (mA)
700
600
500
400
300
200
100
0
0 25 50 75 100 125 150 175 200
TS - CASE TEMPERATURE - oC
Figure 4.
4
Table 4. Insulation and Safety Related Specifications
Parameter
Symbol
Value
Units
Conditions
Minimum External Air Gap
(External Clearance)
L(101)
8.3
mm
Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking
(External Creepage)
L(102)
8.3
mm
Measured from input terminals to output terminals,
shortest distance path along body
0.5
mm
Through insulation distance, conductor to conductor,
usually the direct distance between the photoemitter
and photodetector inside the optocoupler cavity
>175
V
DIN IEC 112/VDE 0303 Part 1
Minimum Internal Plastic Gap
(Internal Clearance)
Tracking Resistance
(Comparative Tracking Index)
CTI
Isolation Group
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
Table 5. Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
–55
+125
°C
Ambient Operating Temperature
TA
–40
+105
°C
Supply voltage
VDD1, VDD2
–0.5
6.0
V
Steady-State Input Voltage[1,3]
VIN+, VIN–
–2
VDD1 + 0.5
V
Two-Second Transient Input Voltage[2]
VIN+, VIN–
–6
VDD1 + 0.5
V
Digital Input/Output Voltages
MCLKIN, MDAT
–0.5
VDD2 + 0.5
V
Lead Solder Temperature
260°C for 10 sec., 1.6 mm below seating plane
Notes:
1. DC voltage of up to –2 V on the inputs does not cause latch-up or damage to the device; tested at typical operating conditions.
2. Transient voltage of 2 seconds up to –6 V on the inputs does not cause latch-up or damage to the device; tested at typical operating conditions.
3. Absolute maximum DC current on the inputs = 100 mA, no latch-up or device damage occurs.
Table 6. Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Ambient Operating Temperature
TA
–40
+105
°C
VDD1 Supply Voltage
VDD1
4.5
5.5
V
VDD2 Supply Voltage
VDD2
3
5.5
V
Analog Input Voltage[1]
VIN+, VIN–
–200
+200
mV
Notes:
1. Full scale signal input range ±320 mV.
5
Table 7. Electrical Specifications
Unless otherwise noted, TA = –40°C to +105°C, VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, VIN+ = –200 mV to +200 mV, and
VIN– = 0 V (single-ended connection); tested with Sinc3 filter, 256 decimation ratio, fMCLKIN = 10 MHz.
Parameter
Symbol
Min.
Typ.[1]
Max.
Units
Test Conditions/Notes
STATIC CHARACTERISTICS
Resolution
Integral Nonlinearity
INL
16
–15
–25
3
3
15
25
Bits
LSB
LSB
Decimation filter output set to 16 bits
TA = –40°C to +85°C; see Definitions section
TA = 85°C to 105°C
–25
25
0.9
LSB
No missing codes, guaranteed by design;
see Definitions section
4.5
3.5
mV
TA = –40°C to +105°C; see Definitions section
V/°C
–2
2
V/V
%
–1
1
%
Differential Nonlinearity
DNL
–0.9
–1
Offset Error
VOS
Offset Drift vs.
Temperature
Offset Drift vs. VDD1
TCVOS
Gain Error
GE
Gain Error Drift vs.
Temperature
120
TCGE
VIN+ = –250 mV to +250mV
TA = –40°C to +105°C, VIN+ = –250 to +250 mV;
see Definitions section
TA = 25°C, VIN+ = –250 to +250 mV
60
ppm/°C
110
V/V
FSR
±320
mV
VIN = VIN+ – VIN–; Note 2
Gain Error Drift vs. VDD1
ANALOG INPUTS
Full-Scale Differential
Voltage Input Range
Average Input Bias Current
3
IINA
–0.5
A
VDD1 = 5V, VDD2 = 5V, VIN+ = 0 V; Note 3
Average Input Resistance
RIN
33
Across VIN+ or VIN– to GND1; Note 3
Input Capacitance
DYNAMIC CHARACTERISTICS
Signal-to-Noise Ratio
Signal-to(Noise + Distortion)
Ratio
CINA
8
k
pF
74
65
80
75
68
75
SNR
SNDR
12
25
Common-Mode Rejection
Ratio
DIGITAL INPUTS AND OUTPUTS
Input High Voltage
CMRR
74
Input Low Voltage
VIL
VIH
dB
dB
7, 8
dB
TA = –40°C to +85°C
7, 8
TA = –40°C to +105°C, VIN+ = –250 mV to +250 mV
7
Bits
kV/V
dB
0.8 ×
VDD2
0.2 ×
VDD2
see Definitions section
VCM = 1 kV; See Definitions section
V
Note 5
V
Note 5
Input Current
IIND
±0.5
A
Input Capacitance
CIND
Output High Voltage
VOH
VDD2
– 0.2
6
VDD2
– 0.1
pF
V
VDD2 = 5 V supply, IOUT = –200 A
VDD2
– 0.15
VDD2
– 0.1
V
VDD2 = 3.3 V supply, IOUT = –200 A
0.4
V
IOUT = +200 A
14
6
19
8
mA
mA
VDD2 = 5 V supply
5
7
mA
VDD2 = 3.3 V supply
Output Low Voltage
VOL
POWER SUPPLY
VDD1 Supply Current
VDD2 Supply Current
IDD1
IDD2
Notes:
1. All Typical values are at TA = 25°C, VDD1 = 5 V, VDD2 = 5 V.
2. Beyond the full-scale input range the data output is either all zeroes or all ones.
3. Because of the switched-capacitor nature of the isolated modulator, time averaged values are shown.
4. Signal frequency of 543 Hz is used as a reference frequency for coherent sampling.
5. Ensured by design.
6
6
Across VIN+ or VIN– to GND1
VIN+ = –200 mV to +200 mV, 543 Hz, sine wave; Note 4
TA = –40°C to +105°C; see Definitions section
TA = –40°C to +105°C; see Definitions section
65
Effective Number of Bits
ENOB
Isolation Transient Immunity CMR
Fig.
9, 10
11, 12
Table 8. Timing Specifications
Unless otherwise noted, TA = –40°C to +105°C, VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V.
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions/Notes
Modulator Clock Input Frequency
fMCLKIN
5
10
20
MHz
Clock duty cycle 40% to 60%
Data Delay After Rising Edge of
MCLKIN[1]
tD
3
15
ns
CL = 15 pF
Fig.
5
Notes:
1. Data changes at the clock rising edge so it can be safely read at the falling edge, although it can be read at the rising edge if preferred.
MCLKIN
tD
MDAT
Figure 5. Data timing.
Table 9. Package Characteristics
Parameter
Symbol
Min.
Input-Output Momentary
Withstand Voltage
VISO
5000
Input-Output Resistance
RI-O
1012
Typ.
1013
1011
Max.
Units
Test Conditions
Note
Vrms
RH ≤ 50%, t = 1 min;
TA = 25°C
1, 2
VI-O = 500 Vdc
2
TA = 100°C
2
Input-Output Capacitance
CI-O
1.4
pF
f = 1 MHz
2
Input IC Junction-to-Ambient
Thermal Resistance
JAI
83
°C/W
1 oz. trace, 2-layer PCB,
still air, TA = 25°C
3
Output IC Junction-to- Ambient
Thermal Resistance
JAO
85
°C/W
1 oz. trace, 2-layer PCB,
still air, TA = 25°C
3
Notes:
1. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 Vrms for 1 second. This test is performed
before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-5 Insulation Characteristic Table.
2. This is a two-terminal measurement: pins 1-8 are shorted together and pins 9-16 are shorted together.
3. Maximum power dissipation in analog side and digital side IC’s needs to be limited to ensure that their respective junction temperature is less than
125°C. The maximum permissible power dissipation is dependent on the thermal impedance and the ambient temperature.
7
Typical Performance Plots
50
40
MCLKIN = 20 MHz
30
MCLKIN = 10 MHz
20
10
0
MCLKIN = 5 MHz
-10
-20
-30
-40
-50
-400 -320 -240 -160 -80 0
80 160 240 320 400
VIN+ (mV)
80
79
78
77
76
75
74
73
72
71
70
MCLKIN = 10 MHz
MCLKIN = 20 MHz
MCLKIN = 5 MHz
50
75
100 125 150 175 200 225 250 275 300
VIN+ (mV)
20
18
TA = +105°C
16 TA = +85°C
MCLKIN = 10 MHz
MCLKIN = 5 MHz
MCLKIN = 20 MHz
14
TA = +25°C
12
TA = –40°C
10
8
-40
-20
0
20
40
60
TEMPERATURE (°C)
80
100
120
18
16
MCLKIN = 20 MHz
MCLKIN = 10 MHz
14
12
MCLKIN = 5 MHz
10
8
6
-320
-240
-160
-80
6
-320
-240
-160
-80
0
80
VIN+ (mV)
160
Figure 9. IDD1 vs. VIN DC input at various temperatures.
20
IDD1 (mA)
fIN = 543 Hz
fIN = 543 Hz
Figure 8. SNDR vs. temperature.
0
80
VIN+ (mV)
160
Figure 10. IDD1 vs. VIN DC input for various frequencies.
8
80
78
76
74
72
70
68
66
64
62
60
Figure 7. SNDR vs. input voltage VIN.
IDD1 (mA)
SNDR (dB)
Figure 6. Input current vs. input voltage.
SNDR (dB)
IIN+ (A)
Unless otherwise noted, TA = 25°C, VDD1 = 5 V, VDD2 = 5 V, VIN+ = –200 mV to +200 mV, and VIN– = 0 V, fMCLKIN = 10 MHz,
with Sinc3 filter, 256 decimation ratio.
240
320
240
320
8
8
7
7
TA = +105°C
6
TA = +85°C
TA = +25°C
5
IDD2 (mA)
IDD2 (mA)
6
TA = –40°C
4
MCLKIN = 10 MHz
5
MCLKIN = 5 MHz
4
3
3
2
-320
MCLKIN = 20 MHz
-240
-160
-80
0
80
VIN+ (mV)
160
240
320
Figure 11. IDD2 vs. VIN DC input at various temperatures.
2
-320
-240
-160
-80
0
80
VIN+ (mV)
160
240
320
Figure 12. IDD2 vs. VIN DC input for various frequencies.
Definitions
Integral Nonlinearity (INL)
corrected by software or hardware.
INL is the maximum deviation of a transfer curve from a
straight line passing through the endpoints of the ADC
transfer function, with offset and gain errors adjusted out.
Signal-to-Noise Ratio (SNR)
Differential Nonlinearity (DNL)
DNL is the deviation of an actual code width from the
ideal value of 1 LSB between any two adjacent codes in
the ADC transfer curve. DNL is a critical specification in
closed-loop applications. A DNL error of less than ±1 LSB
guarantees no missing codes and a monotonic transfer
function.
Offset Error
Offset error is the deviation of the actual input voltage
corresponding to the mid-scale code (32,768 for a 16-bit
system with an unsigned decimation filter) from 0 V. Offset
error can be corrected by software or hardware.
Gain Error
Gain error is the the difference between the ideal gain
slope and the actual gain slope, with offset error adjusted
out. Gain error includes reference error. Gain error can be
9
The SNR is the measured ratio of AC signal power to noise
power below half of the sampling frequency. The noise
power excludes harmonic signals and DC.
Signal-to-(Noise + Distortion) Ratio (SNDR)
The SNDR is the measured ratio of AC signal power to
noise plus distortion power at the output of the ADC. The
signal power is the rms amplitude of the fundamental
input signal. Noise plus distortion power is the rms sum
of all non-fundamental signals up to half the sampling
frequency (excluding DC).
Effective Number of Bits (ENOB)
The ENOB determines the effective resolution of an ADC,
expressed in bits, defined by ENOB = (SNDR − 1.76)/6.02
Isolation Transient Immunity (CMR)
The isolation transient immunity (also known as CommonMode Rejection or CMR) specifies the minimum rate-ofrise/fall of a common-mode signal applied across the
isolation boundary beyond which the modulator clock or
data is corrupted.
Product Overview
Description
The ACPL-796H isolated sigma-delta () modulator
converts an analog input signal into a high-speed (up
to 20 MHz) single-bit data stream by means of a sigmadelta over-sampling modulator. The time average of the
modulator data is directly proportional to the input signal
voltage. The modulator uses external clock ranges from 5
MHz to 20 MHz that is coupled across the isolation barrier.
This arrangement allows synchronous operation of data
acquisition to any digital controller, and adjustable clock
for speed requirements of the application. The modulator
data are encoded and transmitted across the isolation
boundary where they are recovered and decoded into
high-speed data stream of digital ones and zeros. The
original signal information is represented by the density
of ones in the data output.
The other main function of the modulator (optocoupler)
is to provide galvanic isolation between the analog signal
input and the digital data output. It provides high noise
margins and excellent immunity against isolation-mode
transients that allows direct measurement of low-level
signals in highly noisy environments, for example measurement of moor phase currents in power inverters.
With 0.5 mm minimum DTI, the ACPL-796H provides
reliable double protection and high working insulation
voltage, which is suitable for fail-safe designs. This outstanding isolation performance is superior to alternatives
including devices based on capacitive- or magnetic-coupling with DTI in micro-meter range. Offered in an SO-16
package, the isolated ADC delivers the reliability, small
size, superior isolation and over-temperature performance motor drive designers need to accurately measure
current at much lower price compared to traditional
current transducers.
Analog Input
200(TYP)
VIN+
fSWITCH
= MCLKIN
3 pF (TYP)
1.5 pF
ANALOG
GROUND
COMMON MODE
VOLTAGE
1.5 pF
fSWITCH
= MCLKIN
3 pF (TYP)
200(TYP)
VIN–
Figure 13. Analog input equivalent circuit.
In the typical application circuit (Figure 18), the ACPL-796H
is connected in a single-ended input mode. Given the
fully differential input structure, a differential input connection method (balanced input mode as shown in Figure
14) is recommended to achieve better performance. The
input currents created by the switching actions on both of
the pins are balanced on the filter resistors and cancelled
out each other. Any noise induced on one pin will be
coupled to the other pin by the capacitor C and creates
only common mode noise which is rejected by the device.
Typical value for Ra and Rb is 22 and 10 nF for C.
5V
VDD1
Ra
VIN+
+Analog Input
Rb
–
–Analog
Input
C
ACPL-796H
VIN–
GND1
The differential analog inputs of the ACPL-796H are implemented with a fully-differential, switched-capacitor
circuit. The ACPL-796H accepts signal of ±200 mV (full
scale ±320 mV), which is ideal for direct connection to
shunt based current sensing or other low-level signal
sources applications such as motor phase current measurement. An internal voltage reference determines the
full-scale analog input range of the modulator (±320 mV);
an input range of ±200 mV is recommended to achieve
optimal performance. Users are able to use higher input
range, for example ±250 mV, as long as within full-scale
range, for purpose of over-current or overload detection.
Figure 13 shows the simplified equivalent circuit of the
analog input.
10
Figure 14. Simplified differential input connection diagram.
Latch-up Consideration
Modulator Data Output
Latch-up risk of CMOS devices needs careful consideration, especially in applications with direct connection to
signal source that is subject to frequent transient noise.
The analog input structure of the ACPL-796H is designed
to be resilient to transients and surges, which are often
encountered in highly noisy application environments
such as motor drive and other power inverter systems.
Other situations could cause transient voltages to the
inputs include short circuit and overload conditions. The
ACPL-796H is tested with DC voltage of up to –2 V and
2-second transient voltage of up to –6 V to the analog
inputs and there is no latch-up or damage to the device.
Input signal information is contained in the modulator
output data stream, represented by the density of ones
and zeros. The density of ones is proportional to the input
signal voltage, as shown in Figure 15. A differential input
signal of 0 V ideally produces a data stream of ones 50%
of the time and zeros 50% of the time. A differential input
of –200 mV corresponds to 18.75% density of ones, and
a differential input of +200 mV is represented by 81.25%
density of ones in the data stream. A differential input of
+320 mV or higher results in ideally all ones in the data
stream, while input of –320 mV or lower will result in all
zeros ideally. Table 10 shows this relationship.
MODULATOR OUTPUT
+FS (ANALOG INPUT)
0 V (ANALOG INPUT)
–FS (ANALOG INPUT)
ANALOG INPUT
TIME
Figure 15. Moudlator output vs. analog input.
Table 10. Input voltage with ideal corresponding density of 1s at modulator data output, and ADC code.
Analog Input
Voltage Input
Density of 1s
ADC Code (16-bit unsigned decimation)
Full-Scale Range
640 mV
+Full-Scale
+320 mV
100%
65,535
+Recommended Input Range
+200 mV
81.25%
53,248
Zero
0 mV
50%
32,768
–Recommended Input Range
–200 mV
18.75%
12,288
–Full-Scale
–320 mV
0%
0
Notes:
1. With bipolar offset binary coding scheme, the digital code begins with digital 0 at –FS input and increases proportionally to the analog input until
the full-scale code is reached at the +FS input. The zero crossing occurs at the mid-scale input.
2. Ideal density of 1s at modulator data output can be calculated with VIN/640 mV + 50%; similarly, the ADC code can be calculated with (VIN/640 mV)
× 65,536 + 32,768, assuming a 16-bit unsigned decimation filter.
11
Digital Filter
A digital filter converts the single-bit data stream from
the modulator into a multi-bit output word similar to
the digital output of a conventional A/D converter. With
this conversion, the data rate of the word output is also
reduced (decimation). A Sinc3 filter is recommended to
work together with the ACPL-796H. With a 10 MHz external
ISOLATED
5V
INPUT
CURRENT
RSHUNT
0.1
PF
ISOLATION
BARRIER
VDD1
VDD2
VIN+
MCLKIN
VIN–
MDAT
GND1
GND2
clock frequency, 256 decimation ratio and 16-bit word
settings, the output data rate is 39 kHz (= 10 MHz/256).
This filter can be implemented in an ASIC, an FPGA or a
DSP. Some of the ADC codes with corresponding input
voltages are shown in Table 10.
NONISOLATED
5 V/3.3 V
VDD
0.1
PF
CLOCK
DATA
SCLK
SDAT
CS
3-WIRE
SERIAL
INTERFACE
GND
SINC3 FILTER
ACPL-796H
Note: In applications, a 0.1 F bypass capacitor must be connected between pins VDD1 and
GND1, and between pins VDD2 and GND2 of the ACPL-796H.
Figure 16. Typical application circuit with a Sinc3 filter.
Digital Interface IC
The HCPL-0872 Digital Interface IC (SO-16 package) is a
digital filter that converts the single-bit data stream from
the modulator into 15-bit output words and provides a
serial output interface that is compatible with SPI®, QSPI®,
and Microwire® protocols, allowing direct connection to a
ISOLATED
5V
INPUT
CURRENT
RSHUNT
0.1
PF
ISOLATION
BARRIER
VDD1
VDD2
VIN+
MCLKIN
VIN–
MDAT
GND1
GND2
NONISOLATED
5V
microcontroller. Instead of a digital filter implemented in
software, the HCPL-0872 can be used together with the
ACPL-796H to form an isolated programmable two-chip
A/D converter (see Figure 17).
CLOCK
VDD
0.1
PF
ACPL-796J
MCLK1
MDAT1
SCLK
SDAT
CS
3-WIRE
SERIAL
INTERFACE
GND
ACPL-796H
Figure 17. Typical application circuit with the HCPL-0872.
Available in an SO-16 surface-mount package, the Digital
Interface IC has features include five different conversion modes (combinations of speed and resolution),
three different pre-trigger modes (allows conversion time
