ACPL-C78A, ACPL-C780, ACPL-C784
Miniature Isolation Amplifiers
Data Sheet
Description
Features
The ACPL-C78A/C780/C784 family of isolation amplifiers is designed for current sensing in electronic motor
drives. In a typical implementation, motor currents flow
through an external resistor and the resulting analog
voltage drop is sensed by the ACPL-C78A/C780/C784. A
differential output voltage is created on the other side of
the ACPL-C78A/C780/C784 optical isolation barrier. This
differential output voltage is proportional to the motor
current and can be converted to a single-ended signal
by using an op-amp as shown in the recommended application circuit. Since common-mode voltage swings
of several hundred volts in tens of nanoseconds are
common in modern switching inverter motor drives, the
ACPL-C78A/C780/C784 is designed to ignore very high
common-mode transient slew rates (of at least 10 kV/µs).
• 15 kV/µs Common-Mode Rejection at VCM = 1000 V
The high CMR capability of the ACPL-C78A/C780/C784
isolation amplifier provides the precision and stability
needed to accurately monitor motor current in high noise
motor control environments, providing for smoother
control (less “torque ripple”) in various types of motor
control applications.
The product can also be used for general analog signal
isolation applications requiring high accuracy, stability,
and linearity under similarly severe noise conditions. For
general applications, we recommend the ACPL-C780 (gain
tolerance of ±3%) and the ACPL-C784 (gain tolerance of
±5%). For precision applications Avago Technologies offers
the ACPL-C78A with part-to-part gain tolerance of ±1%.
The ACPL-C78A/C780/C784 utilizes sigma-delta (∑-∆) analog-to-digital converter technology, chopper stabilized
amplifiers, and a fully differential circuit topology.
Together, these features deliver unequaled isolationmode noise rejection, as well as excellent offset and gain
accuracy and stability over time and temperature. This
performance is delivered in a compact, auto-insertable,
Stretched SO-8 (SSO-8) package that meets worldwide
regulatory safety standards.
• Compact, Auto-Insertable Stretched SO-8 Package
• 0.00025 V/V/°C Gain Drift vs. Temperature
• 0.3 mV Input Offset Voltage
• 100 kHz Bandwidth
• 0.004% Nonlinearity
• Worldwide Safety Approval: UL 1577 (5000 Vrms/1 min.),
CSA and IEC/EN/DIN EN 60747-5-5
• Advanced Sigma-Delta (∑-∆) A/D Converter Technology
• Fully Differential Amplifier
Applications
• Motor Phase and Rail Current Sensing
• Inverter Current Sensing
• DC bus voltage sensing
• General Purpose Current Sensing and Monitoring
• General Purpose Analog Signal Isolation
Functional Diagram
VDD1 1
IDD1
IDD2
8 VDD2
VIN+ 2
+
+
7 VOUT+
VIN- 3
-
-
6 VOUT-
GND1 4
SHIELD
5 GND2
NOTE: A 0.1 μF bypass capacitor must be connected between pins 1 and
4 and between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Pin Description
Pin No.
Symbol
Description
1
VDD1
Supply voltage for input side (4.5 V to 5.5 V), relative to GND1
2
VIN+
Positive input (± 200 mV recommended)
3
VIN–
Negative input (normally connected to GND1)
4
GND1
Input side ground
5
GND2
Output side ground
6
VOUT–
Negative output
7
VOUT+
Positive output
8
VDD2
Supply voltage for output side (4.5 V to 5.5 V), relative to GND2
Ordering Information
ACPL-C78A/C780/C784 is UL recognized with 5000 Vrms/1 minute rating per UL 1577.
Part number
Option
(RoHS Compliant)
Package
-000E
ACPL-C78A
ACPL-C780
ACPL-C784
-060E
-500E
-560E
Surface Mount
Tape& Reel
IEC/EN/DIN EN
60747-5-5
X
Stretched
SO-8
Quantity
80 per tube
X
X
X
X
X
X
80 per tube
1000 per reel
X
1000 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example:
ACPL-C78A-560E to order product of Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5
Safety Approval and RoHS compliance.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
2
Package Outline Drawings
Stretched SO-8 Package (SSO-8)
RECOMMENDED LAND PATTERN
5.850 ± 0.50
(0.230 ± 0.010)
PART NUMBER
8
7
6
5
C78A
V
YYWW
V = OPTION CODE[1]
RoHS-COMPLIANCE
INDICATOR
DATE CODE
12.650 (0.5)
6.807 ± 0.127
(0.268 ± 0.005)
1.905 (0.1)
1
2
3
4
7°
3.180 ± 0.127
(0.125 ± 0.005)
0.381 ± 0.130
(0.015 ± 0.005)
45°
0.450
(0.018)
0.750 ± 0.250
(0.0295 ± 0.010)
1.590 ± 0.127
(0.063 ± 0.005)
0.200 ± 0.100
(0.008 ± 0.004)
11.50 ± 0.250
(0.453 ± 0.010)
1.270
(0.050) BSG
Dimensions in millimeters and (inches).
Lead coplanarity = 0.1 mm (0.004 inches).
Note 1: “V” = Is 060 or 560; other options are not marked.
Recommended Pb-Free IR Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
Regulatory Information
The ACPL-C78A/C780/C784 is approved by the following organizations:
IEC/EN/DIN EN 60747-5-5
UL
Approval with Maximum Working Insulation Voltage
VIORM = 1414 Vpeak.
Approval under UL 1577, component recognition program
up to VISO = 5000 Vrms. File E55361.
CSA
Approval under CSA Component Acceptance Notice #5,
File CA 88324.
3
Insulation and Safety Related Specifications
Parameter
Symbol
Value
Units
Conditions
Minimum External Air Gap
(External Clearance)
L(101)
8.0
mm
Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking
(External Creepage)
L(102)
8.0
mm
Measured from input terminals to output terminals,
shortest distance path along body
0.5
mm
Through insulation distance, conductor to conductor,
usually the direct distance between the photoemitter and
photodetector inside the optocoupler cavity
>175
V
DIN IEC 112/VDE 0303 Part 1
Minimum Internal Plastic Gap
(Internal Clearance)
Tracking Resistance
(Comparative Tracking Index)
CTI
Isolation Group
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
IEC/EN/DIN EN 60747-5-5 Insulation Characteristics (Option 060)[1]
Description
Symbol
Value
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 450 V rms
for rated mains voltage ≤ 600 Vrms
for rated mains voltage ≤ 1000 Vrms
I-IV
I-IV
I-IV
I-IV
I-III
Climatic Classification
55/100/21
Pollution Degree (DIN VDE 0110/1.89)
2
Units
Maximum Working Insulation Voltage
VIORM
1414
Vpeak
Input to Output Test Voltage, Method b
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial Discharge < 5 pC
VPR
2652
Vpeak
Input to Output Test Voltage, Method a
VIORM x 1.5 = VPR, Type and Sample Test, tm = 10 sec,
Partial Discharge < 5 pC
VPR
2262
Vpeak
Highest Allowable Overvoltage (Transient Overvoltage, tini = 60 sec)
VIOTM
8000
Vpeak
Safety-limiting values
(Maximum values allowed in the event of a failure)
Case Temperature
Input Current[2]
Output Power[2]
TS
IS,INPUT
PS,OUTPUT
175
230
600
°C
mA
mW
Insulation Resistance at TS, VIO = 500 V
RS
≥ 109
Ω
Notes:
1. Insulation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits within the
application.
2. Safety-limiting parameters are dependent on ambient temperature. The Input Current, IS,INPUT, derates linearly above 25 °C free-air temperature at
a rate of 2.53 mA/°C; the Output Power, PS,OUTPUT, derates linearly above 25 °C free-air temperature at a rate of 4 mW/°C.
4
Absolute Maximum Rating
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
–55
+125
°C
Ambient Operating Temperature
TA
–40
+100
°C
Supply Voltages
VDD1, VDD2
0
5.5
V
Steady-State Input Voltage
VIN+, VIN–
–2
VDD1 + 0.5
V
Two Second Transient Input Voltage
VIN+, VIN–
–6
Output Voltages
VOUT+, VOUT–
–0.5
Lead Solder Temperature
260°C for 10 sec., 1.6 mm below seating plane
Note
V
VDD2 + 0.5
V
1
Notes:
1. Non-Halide Flux should be used.
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Ambient Operating Temperature
TA
–40
+85
°C
Supply Voltages
VDD1, VDD2
4.5
5.5
V
Input Voltage (linear and accurate)
VIN+, VIN–
–200
+200
mV
Input Voltage (functional)
VIN+, VIN–
–2
2
V
5
Note
1
DC Electrical Specifications
Unless otherwise noted, all typicals and figures are at the nominal operating conditions of VIN+ = 0, VIN– = 0 V,
VDD1 = VDD2 = 5 V and TA = 25°C; all Minimum and Maximum specifications are within the Recommended Operating
Conditions.
Parameter
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Fig.
Input Offset Voltage
VOS
–2
0.3
2
mV
TA = 25°C
1,2,3
Input Offset Voltage
VOS
–3
TA = –40°C to +85°C
1,2,3
Magnitude of Input Offset
Change vs. Temperature
|dVOS/dTA|
Gain (ACPL-C78A, ±1%)
G1
Gain (ACPL-C780, ±3%)
3
Note
3
10
µV/°C
7.92
8
8.08
V/V
G3
7.76
8
8.24
Gain (ACPL-C784, ±5%)
G5
7.6
8
8.4
Magnitude of VOUT Gain
Change vs.Temperature
|dG/dTA|
0.00025
VOUT Nonlinearity over
±200 mV Input Voltage
NL200
0.0037
Magnitude of NL200
Change vs. Temperature
|dNL200/dTA|
0.0002
VOUT Nonlinearity over
±100 mV Input Voltage
NL100
0.0027
Maximum Input Voltage
before VOUT Clipping
|VIN+|MAX
308
Input Side Supply Current
IDD1
11
16
mA
VIN+ = +400 mV
10
7
Output Side Supply
Current
IDD2
13
16
mA
VIN+ = –400 mV
10
8
Input Current
IIN+
–0.5
µA
VIN+ = 0, VIN– = 0 V
11
9
Magnitude of Input Bias
Current vs.Temperature
|dIIN/dTA|
0.45
nA/°C
Output Low Voltage
VOL
1.29
V
9
10
Output High Voltage
VOH
3.8
V
9
10
VOUT Output CommonMode Voltage
VOCM
VOUT Output Short-Circuit
Current
|IOSC|
18.6
mA
Equivalent Input Impedance
RIN
500
kΩ
VOUT Output Resistance
ROUT
15
Ω
Input DC Common-Mode
Rejection Ratio
CMRRIN
76
dB
6
–5
2.2
2.545
2
2
VIN+ = –200 mV to +200 mV,
TA = 25°C
4,5,6
3
V/V
VIN+ = –200 mV to +200 mV,
TA = 25°C
4,5,6
3
V/V
VIN+ = –200 mV to +200 mV,
TA = 25°C
4,5,6
3
4,5,6
4
7,8
5
7,8
5
7,8
6
V/V/°C
0.35
%
VIN+ = –200 mV to +200 mV
%/°C
0.2
%
VIN+ = –100 mV to +100 mV
mV
2.8
9
V
VOUT = 0 V or VDD2
11
9
12
AC Electrical Specifications
Unless otherwise noted, all typicals and figures are at the nominal operating conditions of VIN+ = 0, VIN– = 0 V,
VDD1 = VDD2 = 5 V and TA = 25°C; all Minimum and Maximum specifications are within the Recommended Operating
Conditions.
Parameter
Symbol
Min.
Typ.
Small-Signal Bandwidth
(-3 dB)
f–3 dB
50
RMS VOUT Noise
Unit
Test Conditions
Fig.
100
kHz
VIN+ = 200 mVpk-pk sine wave
12,13
VN
31.5
mVrms
VIN+ = 0 V
VIN to VOUT Signal Delay
(50 – 10%)
tPD10
2.03
3.3
µs
VIN+ = 0 to 150 mV step, measured
at VOUT node in Figure 15
14,15
VIN to VOUT Signal Delay
(50 – 50%)
tPD50
3.47
5.6
µs
VIN+ = 0 to 150 mV step, measured
at VOUT node in Figure 15
14,15
VIN to VOUT Signal Delay
(50 – 90%)
tPD90
4.99
9.9
µs
VIN+ = 0 to 150 mV step, measured
at VOUT node in Figure 15
14,15
VOUT Rise/ Fall Time
(10 – 90%)
tR/F
2.96
6.6
µs
VIN+ = 0 to 150 mV step, measured
at VOUT node in Figure 15
14,15
15
kV/µs
VCM = 1 kV, TA = 25°C
16
170
mVrms
Common Mode Transient CMTI
Immunity
Power Supply Rejection
PSR
10
Max.
Note
13
14
15
Package Characteristics
Parameter
Symbol
Min.
Input-Output Momentary Withstand
Voltage
VISO
5000
Resistance (Input-Output)
RI-O
Capacitance (Input-Output)
CI-O
7
Typ.
Max.
Unit
Test Condition
Fig.
Note
Vrms
RH < 50%,
t = 1 min., TA = 25°C
16,17
>1012
Ω
VI-O = 500 VDC
18
0.5
pF
f = 1 MHz
18
Notes:
General Note: Typical values represent the mean value of all char
acterization units at the nominal operating conditions. Typical drift
specifications are determined by calculating the rate of change of the
specified parameter versus the drift parameter (at nominal operating
conditions) for each characterization unit, and then averaging the indi
vidual unit rates. The corresponding drift figures are normalized to the
nominal operating conditions and show how much drift occurs as the
particular drift parameter is varied from its nominal value, with all other
parameters held at their nominal operating values. Note that the typical
drift specifications in the tables may differ from the slopes of the mean
curves shown in the corresponding figures.
1. It is recommended to operate with VIN– = 0 V (tied to GND1). Limiting
VIN+ to 100 mV will improve DC nonlinearity and nonlinearity drift.
If VIN– is brought above VDD1 – 2 V, an internal test mode may be
activated. This test mode is for LED coupling test and is not intended
for customer use.
2. This is the Absolute Value of Input Offset Change vs. Temperature.
3. Gain is defined as the slope of the best-fit line of differential output
voltage (VOUT+–VOUT–) vs. differential input voltage (VIN+–VIN–) over
the specified input range.
4. This is the Absolute Value of Gain Change vs. Temperature.
5. Nonlinearity is defined as half of the peak-to-peak output deviation
from the best-fit gain line, expressed as a percentage of the full-scale
differential output voltage.
6. NL100 is the nonlinearity specified over an input voltage range of
±100 mV.
7. The input supply current decreases as the differential input voltage
(VIN+–VIN–) decreases.
8. The maximum specified output supply current occurs when the
differential input voltage (VIN+–VIN–) = –200 mV, the maximum
recommended operating input voltage. However, the output supply
current will continue to rise for differential input voltages up to
approximately –300 mV, beyond which the output supply current
remains constant.
9. Because of the switched-capacitor nature of the input sigma-delta
converter, time-averaged values are shown.
10. When the differential input signal exceeds approximately 308 mV,
the outputs will limit at the typical values shown.
11. Short circuit current is the amount of output current generated when
either output is shorted to VDD2 or GND2.
VDD1
VDD2
12. CMRR is defined as the ratio of the differential signal gain (signal
applied differentially between pins 2 and 3) to the common-mode
gain (input pins tied together and the signal applied to both inputs
at the same time), expressed in dB.
13. Output noise comes from two primary sources: chopper noise and
sigma-delta quantization noise. Chopper noise results from chopper
stabilization of the output op-amps. It occurs at a specific frequency
(typically 400 kHz at room temperature), and is not attenuated by
the internal output filter. A filter circuit can be easily added to the
external post-amplifier to reduce the total RMS output noise. The
internal output filter does eliminate most, but not all, of the sigmadelta quantization noise. The magnitude of the output quantization
noise is very small at lower frequencies (below 10 kHz) and increases
with increasing frequency.
14. CMTI (Common Mode Transient Immunity or CMR, Common Mode
Rejection) is tested by applying an exponentially rising/falling voltage
step on pin 4 (GND1) with respect to pin 5 (GND2). The rise time of
the test waveform is set to approximately 50 ns. The amplitude of the
step is adjusted until the differential output (VOUT+–VOUT–) exhibits
more than a 200 mV deviation from the average output voltage for
more than 1μs. The ACPL-C78A/C780/C784 will continue to function
if more than 10 kV/μs common mode slopes are applied, as long as
the breakdown voltage limitations are observed.
15. Data sheet value is the differential amplitude of the transient at the
output of the ACPL-C78A/C780/C784 when a 1 Vpk-pk, 1 MHz square
wave with 40 ns rise and fall times is applied to both VDD1 and VDD2.
16. In accordance with UL 1577, each optocoupler is proof tested by
applying an insulation test voltage ≥6000 Vrms for 1 second (leakage
detection current limit, II-O ≤ 5 μA). This test is performed before the
100% production test for partial discharge (method b) shown in IEC/
EN/DIN EN 60747-5-5 Insulation Characteristic Table.
17. The Input-Output Momentary Withstand Voltage is a dielectric
voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating, refer
to the IEC/EN/DIN EN 60747-5-5 insulation characteristics table and
your equipment level safety specification.
18. This is a two-terminal measurement: pins 1–4 are shorted together
and pins 5–8 are shorted together.
+15 V
0.1 µF
1
8
2
0.1 µF
3
ACPL-C78A
ACPL-C780
ACPL-C784
4
0.1 µF
7
10 K
6
10 K
5
+
0.47
µF
VOUT
–
AD624CD
GAIN = 100
0.1 µF
0.47
µF
-15 V
Figure 1. Input Offset Voltage Test Circuit.
8
0.39
VOS - INPUT OFFSET VOLTAGE - mV
VOS - INPUT OFFSET VOLTAGE - mV
0.8
0.7
0.6
0.5
0.4
0.3
0.2
-55
-25
5
35
TA - TEMPERATURE - °C
65
0.37
0.36
0.35
0.34
0.33
4.5
95
Figure 2. Input Offset Voltage vs. Temperature.
vs. VDD1
vs. VDD2
0.38
4.75
5.0
5.25
VDD - SUPPLY VOLTAGE - V
5.5
Figure 3. Input Offset vs. Supply.
8.035
G - GAIN - V/V
8.03
8.025
8.02
8.015
8.01
-55
-15
-35
5
25
45
TA - TEMPERATURE - °C
65
85
Figure 4. Gain vs. Temperature.
VDD1
VDD2
+15 V
+15 V
0.1 µF
0.1 µF
VIN
404
1
8
0.1µF
2
13.2
3
ACPL-C78A
ACPL-C780
ACPL-C784
7
10 K
6
10 K
+
+
–
–
VOUT
0.01 µF
4
5
0.47
µF
AD624CD
GAIN = 4
0.1 µF
-15 V
10 K
0.47
µF
Figure 5. Gain and Nonlinearity Test Circuit.
AD624CD
GAIN = 10
0.1 µF
0.47
µF
-15 V
9
0.1 µF
8.032
0.03
0.025
NL - NONLINEARITY - %
G - GAIN - V/V
8.03
8.028
8.026
8.024
vs. VDD1
vs. VDD2
4.5
4.75
5.0
5.25
VDD - SUPPLY VOLTAGE - V
0
VO - OUTPUT VOLTAGE - V
NL - NONLINEARITY - %
-25
5
35
65
TA - TEMPERATURE - °C
95
4.2
0.004
0.003
4.5
4.75
5.0
5.25
VDD - SUPPLY VOLTAGE - V
3.4
2.6
1.8
1.0
-0.5
5.5
Figure 8. Nonlinearity vs. Supply.
VOUT+
VOUT–
-0.3
-0.1
0.1
VIN - INPUT VOLTAGE - V
0.3
0.5
Figure 9. Output Voltage vs. Input Voltage.
13
0
IIN - INPUT CURRENT - µA
IDD - SUPPLY CURRENT - mA
-55
Figure 7. Nonlinearity vs. Temperature.
vs. VDD1
vs. VDD2
10
7
IDD1, VIN+ = +400 mV
IDD2, VIN+ = –400 mV
-0.3
-0.1
0.1
VIN - INPUT VOLTAGE - V
Figure 10. Supply Current vs. Input Voltage.
10
0.01
5.5
0.005
4
-0.5
0.015
0.005
Figure 6. Gain vs. Supply.
0.002
0.02
0.3
0.5
-1
-2
-3
-4
-5
-0.6
-0.4
0
-0.2
0.2
VIN - INPUT VOLTAGE - V
Figure 11. Input Current vs. Input Voltage.
0.4
0.6
50
1
0
PHASE - DEGREES
GAIN - dB
0
-1
-2
-3
-4
-50
-100
-150
-200
-250
10
1000
10000
FREQUENCY (Hz)
100
-300
100000
Figure 12. Gain vs. Frequency.
10
100
1000
10000
FREQUENCY (Hz)
Figure 13. Phase vs. Frequency.
PD - PROPAGATION DELAY - µS
5.5
4.7
Tpd 10
Tpd 50
Tpd 90
Trise
3.9
3.1
2.3
1.5
-55
35
5
TA - TEMPERATURE - °C
-25
65
95
Figure 14. Propagation Delay vs. Temperature.
10 K
VDD1
VDD2
+15 V
0.1 µF
0.1 µF
VIN
0.01 µF
1
8
2
7
2K
6
2K
3
ACPL-C78A
ACPL-C780
ACPL-C784
4
5
0.1 µF
–
VOUT
+
MC34081
0.1 µF
10 K
-15 V
VIN IMPEDANCE LESS THAN 10 Ω.
Figure 15. Propagation Delay Test Circuits.
11
100000
10 K
0.1
µF
0.1
µF
9V
150 pF
VDD2
78L05
IN OUT
+15 V
0.1 µF
1
8
2
7
2K
6
2K
ACPL-C78A
ACPL-C780
ACPL-C784
3
4
0.1 µF
–
5
MC34081
0.1 µF
10 K
150
pF
PULSE GEN.
VOUT
+
-15 V
–
+
VCM
Figure 16. CMTI Test Circuits.
Application Information
Power Supplies and Bypassing
The recommended supply connections are shown in
Figure 17. A floating power supply (which in many applications could be the same supply that is used to drive
the high-side power transistor) is regulated to 5 V using
a simple zener diode (D1); the value of resistor R4 should
be chosen to supply sufficient current from the existing
floating supply. The voltage from the current sensing
resistor (Rsense) is applied to the input of the ACPL-C78A/
C780/C784 through an RC anti-aliasing filter (R2 and C2).
Although the application circuit is relatively simple, a few
recommendations should be followed to ensure optimal
performance.
ACPL-C78A/C780/C784. The bypass capacitors are
required because of the high-speed digital nature of
the signals inside the ACPL-C78A/C780/C784. A 0.01 µF
bypass capacitor (C2) is also recommended at the input
due to the switched-capacitor nature of the input circuit.
The input bypass capacitor also forms part of the antialiasing filter, which is recommended to prevent highfrequency noise from aliasing down to lower frequencies
and interfering with the input signal. The input filter also
performs an important reliability function – it reduces
transient spikes from ESD events flowing through the
current sensing resistor.
The power supply for the ACPL-C78A/C780/C784 is most
often obtained from the same supply used to power the
power transistor gate drive circuit. If a dedicated supply is
required, in many cases it is possible to add an additional
winding on an existing transformer. Otherwise, some sort of
simple isolated supply can be used, such as a line powered
transformer or a high-frequency DC-DC converter.
PC Board Layout
An inexpensive 78L05 three-terminal regulator can also be
used to reduce the floating supply voltage to 5 V. To help
attenuate high-frequency power supply noise or ripple, a
resistor or inductor can be used in series with the input of
the regulator to form a low-pass filter with the regulator’s
input bypass capacitor.
As shown in Figure 18, 0.1 µF bypass capacitors (C1, C2)
should be located as close as possible to the pins of the
12
The design of the printed circuit board (PCB) should follow
good layout practices, such as keeping bypass capacitors
close to the supply pins, keeping output signals away from
input signals, the use of ground and power planes, etc. In
addition, the layout of the PCB can also affect the isolation
transient immunity (CMTI) of the ACPL-C78A/C780/C784,
due primarily to stray capacitive coupling between the
input and the output circuits. To obtain optimal CMTI
performance, the layout of the PC board should minimize
any stray coupling by maintaining the maximum possible
distance between the input and output sides of the circuit
and ensuring that any ground or power plane on the PC
board does not pass directly below or extend much wider
than the body of the ACPL-C78A/C780/C784.
+
FLOATING
POWER
SUPPLY
–
HV+
GATE DRIVE
CIRCUIT
***
D1
5.1 V
C1
0.1 µF
R2
39 Ω
MOTOR
***
ACPL-C78A
ACPL-C780
ACPL-C784
C2
0.01 µF
+ R1 –
RSENSE
***
HV-
Figure 17. Recommended Supply and Sense Resistor Connections.
POSITIVE
FLOATING
SUPPLY
HV+
C5
150 pF
GATE DRIVE
CIRCUIT
U1
78L05
IN OUT
C1
0.1
µF
R5
10.0 K
***
+ –
RSENSE
VDD2 (+5 V)
VDD1
C2
0.1
µF
8
2
7
R1
6
2.00 K
R2
U2
5
ACPL-C78A
ACPL-C780
ACPL-C784
***
HVFigure 18. Recommended Application Circuit.
TO GND1 TO VDD1
TO VDD2 TO GND2
C4
C2
U2
TO RSENSE+
R5
VOUT+
VOUT–
C3
TO RSENSE–
Note: Drawing not to scale
ACPL - C78A/C780/C784
Figure 19. Example Printed Circuit Board Layout.
13
C4
0.1 µF
2.00 K
4
GND1
+15 V
1
C3
0.01 3
µF
68
MOTOR
R3
***
C6
150 pF
GND2
C8
0.1 µF
GND2
–
U3
+ TL032A
C7
R4
0.1 µF
10.0 K
-15 V
GND2
GND2
VOUT
Current Sensing Resistors
The current sensing resistor should have low resistance (to
minimize power dissipation), low inductance (to minimize
di/dt induced voltage spikes which could adversely
affect operation), and reasonable tolerance (to maintain
overall circuit accuracy). Choosing a particular value for
the resistor is usually a compromise between minimizing power dissipation and maximizing accuracy. Smaller
sense resistance decreases power dissipation, while larger
sense resistance can improve circuit accuracy by utilizing
the full input range of the ACPL-C78A/C780/C784.
The first step in selecting a sense resistor is determining
how much current the resistor will be sensing. The graph in
Figure 20 shows the RMS current in each phase of a threephase induction motor as a function of average motor
output power (in horsepower, hp) and motor drive supply
voltage. The maximum value of the sense resistor is determined by the current being measured and the maximum
recommended input voltage of the isolation amplifier. The
maximum sense resistance can be calculated by taking
the maximum recommended input voltage and dividing
by the peak current that the sense resistor should see
during normal operation. For example, if a motor will have
a maximum RMS current of 10 A and can experience up
to 50% overloads during normal operation, then the peak
current is 21.1 A (=10 x 1.414 x 1.5). Assuming a maximum
input voltage of 200 mV, the maximum value of sense resistance in this case would be about 10 mΩ.
The maximum average power dissipation in the sense
resistor can also be easily calculated by multiplying the
sense resistance times the square of the maximum RMS
current, which is about 1 W in the previous example. If the
power dissipation in the sense resistor is too high, the resistance can be decreased below the maximum value to
decrease power dissipation. The minimum value of the
sense resistor is limited by precision and accuracy requirements of the design. As the resistance value is reduced,
MOTOR OUTPUT POWER - HORSEPOWER
40
440 V
380 V
220 V
120 V
35
30
25
20
15
10
5
0
0
5
15
10
20
25
MOTOR PHASE CURRENT - A (rms)
30
35
Figure 20. Motor Output Horsepower vs. Motor Phase Current and Supply
Voltage.
14
the output voltage across the resistor is also reduced,
which means that the offset and noise, which are fixed,
become a larger percentage of the signal amplitude. The
selected value of the sense resistor will fall somewhere
between the minimum and maximum values, depending
on the particular requirements of a specific design.
When sensing currents large enough to cause significant
heating of the sense resistor, the temperature coefficient
(tempco) of the resistor can introduce nonlinearity due to
the signal dependent temperature rise of the resistor. The
effect increases as the resistor-to-ambient thermal resistance increases. This effect can be minimized by reducing
the thermal resistance of the current sensing resistor or
by using a resistor with a lower tempco. Lowering the
thermal resistance can be accomplished by repositioning the current sensing resistor on the PC board, by using
larger PC board traces to carry away more heat, or by
using a heat sink.
For a two-terminal current sensing resistor, as the value
of resistance decreases, the resistance of the leads become
a significant percentage of the total resistance. This has
two primary effects on resistor accuracy. First, the effective
resistance of the sense resistor can become dependent
on factors such as how long the leads are, how they are
bent, how far they are inserted into the board, and how far
solder wicks up the leads during assembly (these issues
will be discussed in more detail shortly). Second, the leads
are typically made from a material, such as copper, which
has a much higher tempco than the material from which
the resistive element itself is made, resulting in a higher
tempco overall.
Both of these effects are eliminated when a four-terminal
current sensing resistor is used. A four-terminal resistor has
two additional terminals that are Kelvin connected directly
across the resistive element itself; these two terminals are
used to monitor the voltage across the resistive element
while the other two terminals are used to carry the load
current. Because of the Kelvin connection, any voltage
drops across the leads carrying the load current should
have no impact on the measured voltage.
When laying out a PC board for the current sensing
resistors, a couple of points should be kept in mind. The
Kelvin connections to the resistor should be brought
together under the body of the resistor and then run very
close to each other to the input of the ACPL-C78A/C780/
C784; this minimizes the loop area of the connection and
reduces the possibility of stray magnetic fields from interfering with the measured signal. If the sense resistor is not
located on the same PC board as the ACPL-C78A/C780/
C784 circuit, a tightly twisted pair of wires can accomplish
the same thing.
Also, multiple layers of the PC board can be used to
increase current carrying capacity. Numerous platedthrough vias should surround each non-Kelvin terminal of
the sense resistor to help distribute the current between
the layers of the PC board. The PC board should use 2 or
4 oz. copper for the layers, resulting in a current carrying
capacity in excess of 20 A. Making the current carrying
traces on the PC board fairly large can also improve the
sense resistor’s power dissipation capability by acting as a
heat sink. Liberal use of vias where the load current enters
and exits the PC board is also recommended.
In addition, the op-amp should also have enough bandwidth and slew rate so that it does not adversely affect the
response speed of the overall circuit. The post-amplifier
circuit includes a pair of capacitors (C5 and C6) that form
a single-pole low-pass filter; these capacitors allow the
bandwidth of the post-amp to be adjusted independently
of the gain and are useful for reducing the output noise
from the isola-tion amplifier. Many different op-amps
could be used in the circuit, including: TL032A, TL052A,
and TLC277 (Texas Instruments), LF412A (National Semiconductor).
Note: Please refer to Avago Technologies Application Note 1078 for
additional information on using Isolation Amplifiers.
The gain-setting resistors in the post-amp should have a
tolerance of 1% or better to ensure adequate CMRR and
adequate gain tolerance for the overall circuit. Resistor
networks can be used that have much better ratio tolerances than can be achieved using discrete resistors. A
resistor network also reduces the total number of components for the circuit as well as the required board space.
Sense Resistor Connections
The recommended method for connecting the
ACPL-C78A/C780/C784 to the current sensing resistor is
shown in Figure 18. VIN+ (pin 2 of the ACPL-C78A/C780/
C784) is connected to the positive terminal of the sense
resistor, while VIN- (pin 3) is shorted to GND1 (pin 4), with
the power-supply return path functioning as the sense
line to the negative terminal of the current sense resistor.
This allows a single pair of wires or PC board traces to
connect the ACPL-C78A/C780/C784 circuit to the sense
resistor. By referencing the input circuit to the negative
side of the sense resistor, any load current induced noise
transients on the resistor are seen as a common-mode
signal and will not interfere with the current-sense signal.
This is important because the large load currents flowing
through the motor drive, along with the parasitic inductances inherent in the wiring of the circuit, can generate
both noise spikes and offsets that are relatively large
compared to the small voltages that are being measured
across the current sensing resistor.
If the same power supply is used both for the gate drive
circuit and for the current sensing circuit, it is very important
that the connection from GND1 of the ACPL-C78A/C780/
C784 to the sense resistor be the only return path for
supply current to the gate drive power supply in order to
eliminate potential ground loop problems. The only direct
connection between the ACPL-C78A/C780/C784 circuit
and the gate drive circuit should be the positive power
supply line.
Output Side
The op-amp used in the external post-amplifier circuit
should be of sufficiently high precision so that it does not
contribute a significant amount of offset or offset drift
relative to the contribution from the isolation amplifier.
Generally, op-amps with bipolar input stages exhibit
better offset performance than op-amps with JFET or
MOSFET input stages.
15
Frequently asked questions about the
ACPL-C78A/C780/C784
1. The basics
1.1. Why should I use the ACPL-C78A/C780/C784 for sensing current
when Hall-effect sensors are available which don’t need an
isolated supply voltage?
Available in an auto-insertable, Stretched SO-8
package, the ACPL-C78A/C780/C784 is smaller than
and has better linearity, offset vs. temperature and
Common Mode Rejection (CMR) performance than
most Hall-effect sensors. Additionally, often the
required input-side power supply can be derived
from the same supply that powers the gate-drive
optocoupler.
2. Sense resistor and input filter
2.1. Where do I get 10 mΩ resistors? I have never seen one that low.
Although less common than values above 10 Ω, there
are quite a few manufacturers of resistors suitable
for measuring currents up to 50 A when combined
with the ACPL-C78A/C780/C784. Example product
information may be found at Vishay's web site
(http://www.vishay.com) and Isotek’s web site
(http://www.isotekcorp.com).
2.2. Should I connect both inputs across the sense resistor instead of
grounding VIN- directly to pin 4?
This is not necessary, but it will work. If you do, be
sure to use an RC filter on both pin 2 (VIN+) and pin 3
(VIN-) to limit the input voltage at both pads.
2.3. Do I really need an RC filter on the input? What is it for? Are other
values of R and C okay?
The input anti-aliasing filter (R=39 Ω, C=0.01 µF)
shown in the typical application circuit is recommended for filtering fast switching voltage transients
from the input signal. (This helps to attenuate higher
signal frequencies which could otherwise alias with
the input sampling rate and cause higher input offset
voltage.)
3. Isolation and insulation
Some issues to keep in mind using different filter
resistors or capacitors are:
4.1. Can the signal to noise ratio be improved?
1. Filter resistor: Input bias current for pins 2 and 3:
This is on the order of 500 nA. If you are using a
single filter resistor in series with pin 2 but not pin
3 the IxR drop across this resistor will add to the
offset error of the device. As long as this IR drop
is small compared to the input offset voltage
there should not be a problem. If larger-valued
resistors are used in series, it is better to put half
of the resistance in series with pin 2 and half the
resistance in series with pin 3. In this case, the
offset voltage is due mainly to resistor mismatch
(typically less than 1% of the resistance design
value) multiplied by the input bias.
2. Filter resistor: The equivalent input resistance
for ACPL-C78A/C780/C784 is around 500 kΩ.
It is therefore best to ensure that the filter
resistance is not a significant percentage of
this value; otherwise the offset voltage will be
increased through the resistor divider effect.
[As an example, if Rfilt = 5.5 kΩ, then VOS = (Vin *
1%) = 2 mV for a maximum 200 mV input and VOS
will vary with respect to Vin.]
3. The input bandwidth is changed as a result of this
different R-C filter configuration. In fact this is one
of the main reasons for changing the input-filter
R-C time constant.
4. Filter capacitance: The input capacitance of the
ACPL-C78A/C780/C784 is approximately 1.5 pF.
For proper operation the switching input-side
sampling capacitors must be charged from a
relatively fixed (low impedance) voltage source.
Therefore, if a filter capacitor is used it is best for
this capacitor to be a few orders of magnitude
greater than the CINPUT (A value of at least 100 pF
works well.)
2.4. How do I ensure that the ACPL-C78A/C780/C784 is not destroyed
as a result of short circuit conditions which cause voltage drops
across the sense resistor that exceed the ratings of the ACPLC78A/C780/C784’s inputs?
Select the sense resistor so that it will have less than 5 V
drop when short circuits occur. The only other requirement is to shut down the drive before the sense resistor
is damaged or its solder joints melt. This ensures that
16
the input of the ACPL-C78A/C780/C784 can not be
damaged by sense resistors going open-circuit.
3.1. How many volts will the ACPL-C78A/C780/C784 withstand?
The momentary (1 minute) withstand voltage is 5000
V rms per UL 1577 and CSA Component Acceptance
Notice #5.
4. Accuracy
Yes. Some noise energy exists beyond the 100 kHz
bandwidth of the ACPL-C78A/C780/C784. Additional
filtering using different filter R,C values in the post-amplifier application circuit can be used to improve the
signal to noise ratio. For example, by using values of R3
= R4 = 10 kΩ, C5 = C6 = 470 pF in the application circuit
the rms output noise will be cut roughly by a factor of
2. In applications needing only a few kHz bandwidth
even better noise performance can be obtained. The
noise spectral density is roughly 500 nV/sqrt(Hz) below
20 kHz (input referred).
4.2. Does the gain change if the internal LED light output degrades
with time?
No. The LED is used only to transmit a digital pattern.
Avago Technologies has accounted for LED degradation in the design of the product to ensure long life.
5. Power supplies and start-up
5.1. What are the output voltages before the input side power supply
is turned on?
VOUT+ is close to 1.29 V and VOUT– is close to 3.80 V. This
is equivalent to the output response at the condition
that LED is completely off.
5.2. How long does the ACPL-C78A/C780/C784 take to begin working
properly after power-up?
Within 1 ms after VDD1 and VDD2 powered the device
starts to work. But it takes longer time for output to
settle down completely. In case of the offset measurement while both inputs are tied to ground there
is initially VOS adjustment (about 60 ms). The output
completely settles down in 100 ms after device
powering up.
6. Miscellaneous
6.1. How does the ACPL-C78A/C780/C784 measure negative signals
with only a +5 V supply?
The inputs have a series resistor for protection
against large negative inputs. Normal signals are no
more than 200 mV in amplitude. Such signals do not
forward bias any junctions sufficiently to interfere
with accurate operation of the switched capacitor
input circuit.
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved.
AV02-1436EN - March 26, 2013
