ACPL-C797-500E

ACPL-C797 Optically Isolated Sigma-Delta Modulator Data Sheet Description Features The ACPL-C797 is a 1-bit, second-order sigma-delta (-) modulator converts an analog input signal into a high-speed data stream with galvanic isolation based on optical coupling technology. The ACPL-C797 operates from a 5-V power supply with dynamic range of 80 dB with an appropriate digital filter. The differential inputs of ±200 mV (full scale ±320 mV) are ideal for direct connection to shunt resistors or other low-level signal sources in applications, such as motor phase current measurement.  The analog input is continuously sampled by a means of sigma-delta over-sampling using an on-board clock. The signal information is contained in the modulator data, as a density of ones with data rate of 10 MHz, and the data are encoded and transmitted across the isolation boundary where they are recovered and decoded into high-speed data stream of digital ones and zeros. The original signal information can be reconstructed with a digital filter. The serial interface for data and clock has a wide supply range of 3V to 5. V.  Combined with superior optical-coupling technology, the modulator delivers high noise margins and excellent immunity against isolation-mode transients. With 0.5-mm minimum distance through insulation (DTI), the ACPL-C797 provides reliable reinforced insulation and high working insulation voltage, which is suitable for fail-safe designs. This outstanding isolation performance is superior to alternatives, including devices based on capacitive- or magnetic-coupling with DTI in micro-meter range. Offered in a Stretched SO-8 (SSO-8) package, the isolated ADC delivers the reliability, small size, superior isolation, and over-temperature performance that motor drive designers need to accurately measure current at much lower price compared to traditional current transducers.             Superior optical isolation and insulation 10-MHz internal clock 1-bit, second-order sigma-delta modulator 16 bits resolution no missing codes (12 bits ENOB) 78 dB SNR 3.5 μV/°C maximum offset drift ±1% gain error Internal reference voltage ±200-mV linear range with single 5-V supply (±320 mV full scale) 3-V to 5.5-V wide supply range for digital interface –40°C to +105°C operating temperature range SSO-8 package 25-kV/μs common-mode transient immunity Safety and regulatory approval: — IEC/EN/DIN EN 60747-5-5: 1414 Vpeak working insulation voltage — UL 1577: 5000 Vrms/1 min isolation voltage — CSA: Component Acceptance Notice #5 Applications       Motor phase and rail current sensing Power inverter current and voltage sensing Industrial process control Data acquisition systems General purpose current and voltage sensing Traditional current transducer replacements CAUTION The external clock version modulator ACPL-796J (SO-16 package) is also available. Broadcom -1- It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation that may be induced by ESD. The components featured in this data sheet are not to be used in military or aerospace applications or environments. ACPL-C797 Data Sheet Functional Block Diagram Figure 1 Functional Block Diagram VDD1 VDD2 6-' MODULATOR/ ENCODER VIN+ VIN– MCLK LED DRIVER DECODER SHIELD BUF CLK VREF GND1 MDAT GND2 Pin Configurations and Descriptions Figure 2 Pin Configuration VDD1 1 VIN+ 2 VIN– 3 GND1 4 ACPL-C797 8 VDD2 7 MCLK 6 MDAT 5 GND2 Table 1 Pin Descriptions Pin No. Symbol Description 1 VDD1 Supply voltage for signal input side (analog side), relative to GND1 2 VIN+ Positive analog input, recommended input range ±200 mV 3 VIN- Negative analog input, recommended input range ±200 mV (normally connected to GND1) 4 GND1 Supply ground for signal input side 5 GND2 Supply ground for data/clock output side (digital side) 6 MDAT Modulator data output 7 MCLK Modulator clock output 8 VDD2 Supply voltage for data output side, relative to GND2 Broadcom -2- ACPL-C797 Data Sheet Ordering Information ACPL-C797 is UL recognized with 5000 Vrms/1 minute rating per UL 1577. Table 2 Ordering Information Part Number ACPL-C797 Option (RoHS Compliant) -000E Package Surface Mount Stretched SO-8 Tape and Reel X -500E X X IEC/EN/DIN EN 60747-5-5 Quantity X 80 per tube X 1000 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example: ACPL-C797-500E to order product of Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval and RoHS compliance. Option data sheets are available. Contact your Broadcom sales representative or authorized distributor for information. Broadcom -3- ACPL-C797 Data Sheet Package Outline Drawings Stretched SO-8 Package (SSO-8) Figure 3 Package Dimensions RECOMMENDED LAND PATTERN * 5.850 ± 0.254 (0.230 ± 0.010) PART NUMBER 8 7 6 5 C797 YYWW EEE RoHS-COMPLIANCE INDICATOR DATE CODE 12.650 (0.498) 6.807 ± 0.127 (0.268 ± 0.005) 1.905 (0.075) 1 2 3 4 0.64 (0.025) LOT ID 7° 1.590 ± 0.127 (0.063 ± 0.005) 45° 0.450 (0.018) 3.180 ± 0.127 (0.125 ± 0.005) 0.750 ± 0.250 (0.0295 ± 0.010) 11.50 ± 0.250 (0.453 ± 0.010) 0.200 ± 0.100 (0.008 ± 0.004) 0.381 ± 0.127 (0.015 ± 0.005) 1.270 (0.050) BSG 0.254 ± 0.100 (0.010 ± 0.004) * Total package width (inclusive of mold flash) 6.100 mm ± 0.250 mm Dimensions in millimeters and (inches). Note: Lead coplanarity = 0.1 mm (0.004 inches). Floating lead protrusion = 0.25 mm (10 mils) max. Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Use non-halide flux. Regulatory Information The ACPL-C797 is approved by the following organizations: Table 3 Regulatory Information IEC/EN/DIN EN 60747-5-5 Maximum working insulation voltage VIORM = 1414VPEAK UL Approval under UL 1577, component recognition program up to VISO = 5000 VRMS. File E55361. CSA Approval under CSA Component Acceptance Notice #5, File CA 88324. Broadcom -4- ACPL-C797 Data Sheet IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table 4 IEC/EN/DIN EN 60747-5-5 Insulation Characteristicsa Description Symbol Value Units Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤ 150 Vrms I-IV for rated mains voltage ≤ 300 Vrms I-IV for rated mains voltage ≤ 450 Vrms I-IV for rated mains voltage ≤ 600 Vrms I-IV for rated mains voltage ≤ 1000 Vrms I-III Climatic Classification 55/105/21 Pollution Degree (DIN VDE 0110/1.89) 2 VIORM 1414 Vpeak Input to Output Test Voltage, Method b VIORM × 1.875 = VPR, 100% Production Test with tm = 1s, Partial Discharge < 5 pC VPR 2652 Vpeak Input to Output Test Voltage, Method a VIORM × 1.6 = VPR, Type and Sample Test, tm = 10s, Partial Discharge < 5 pC VPR 2262 Vpeak VIOTM 8000 Vpeak TS 175 °C Input Currentb IS,INPUT 230 mA Output Powerb PS,OUTPUT 600 mW RS ≥ 109  Maximum Working Insulation Voltage Highest Allowable Overvoltage (Transient Overvoltage, tini = 60 sec) Safety-limiting values (Maximum values allowed in the event of a failure) Case Temperature Insulation Resistance at TS, VIO = 500 V a. Insulation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits within the application. b. Safety-limiting parameters are dependent on ambient temperature. The Input Current, IS,INPUT, derates linearly above 25°C free-air temperature at a rate of 2.53 mA/°C; the Output Power, PS,OUTPUT, derates linearly above 25°C free-air temperature at a rate of 4 mW/°C. Insulation and Safety Related Specifications Table 5 Insulation and Safety Related Specifications Parameter Symbol Value Units Conditions Minimum External Air Gap (External Clearance) L(101) 8.0 mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (External Creepage) L(102) 8.0 mm Measured from input terminals to output terminals, shortest distance path along body 0.5 mm Through insulation distance, conductor to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity >175 V DIN IEC 112/VDE 0303 Part 1 Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Broadcom -5- ACPL-C797 Data Sheet Absolute Maximum Ratings Table 6 Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature TS –55 +125 °C Ambient Operating Temperature TA –40 +105 °C VDD1, VDD2 –0.5 6.0 V Steady-State Input Voltagea, b VIN+, VIN- –2 VDD1 + 0.5 V Two-Second Transient Input Voltagec VIN+, VIN- –6 VDD1 + 0.5 V MCLK, MDAT –0.5 VDD2 + 0.5 V Supply Voltage Digital Output Voltages Lead Solder Temperature 260°C for 10s., 1.6 mm below seating plane a. DC voltage of up to –2V on the inputs does not cause latch-up or damage to the device; tested at typical operating conditions. b. Absolute maximum DC current on the inputs = 100 mA, no latch-up or device damage occurs. c. .Transient voltage of 2 seconds up to –6V on the inputs does not cause latch-up or damage to the device; tested at typical operating conditions. Recommended Operating Conditions Table 7 Recommended Operating Conditions Parameter Symbol Min. Max. Units TA –40 +105 °C VDD1 Supply Voltage VDD1 4.5 5.5 V VDD2 Supply Voltage VDD2 3 5.5 V Analog Input Voltagea VIN+, VIN- –200 +200 mV Ambient Operating Temperature a. Full scale signal input range ±320 mV. Electrical Specifications VDD1 Unless otherwise noted, TA = –40°C to +105°C, VDD1 = 4.5V to 5.5V, VDD2 = 3V to 5.5V, VIN+ = –200 mV to +200 mV, and VIN- = 0V (single-ended connection); tested with Sinc3 filter, 256 decimation ratio. Table 8 Electrical Specifications Parameter Symbol Min. Typ.a Max. Units Test Conditions 16 — — Bits Decimation filter output set to 16 bits –5 3 15 LSB TA = –40°C to +85°C; see Definitions –25 3 25 LSB TA = 85°C to +105°C Figure Static Characteristics Resolution Integral Nonlinearity INL Differential Nonlinearity DNL –0.9 — 0.9 LSB No missing codes, guaranteed by design; see Definitions Offset Error VOS –1 0.3 2 mV TA = –40°C to 105°C; see Definitions TCVOS — 1.0 3.5 μV/°C Offset Drift vs. Temperature Broadcom -6- VDD1 = 5V 5 Notes ACPL-C797 Data Sheet Table 8 Electrical Specifications (Continued) Parameter Symbol Offset Drift vs. VDD1 Internal Reference Voltage Reference Voltage Tolerance VREF Drift vs. Temperature Min. Typ.a Max. Units — 200 — μV/V 320 — mV –1 — 1 % TA = 25°C, VIN+ = –320 mV to +320 mV; see Definitions –2 — 2 % TA = –40°C to +105°C, VIN+ = –320 mV to +320mV — 60 — ppm/°C — –1.3 — mV/V VREF GE TCGE VREF Drift vs. VDD1 Test Conditions Figure Notes 6 b Analog Inputs Full-Scale Differential Voltage Input Range FSR — ± 320 — mV VIN = VIN+ – VIN- Input Bias Current IINA — –0.3 — μA VDD1 = 5V, VDD2 = 5V, VIN+ = 0V Input Resistance RIN — 24 — k Across VIN+ or VIN- to GND1 Input Capacitance CINA — 8 — pF Across VIN+ or VIN- to GND1 7 SNR 68 78 — dB TA = –40°C to +105°C; see Definitions 8 Signal-to-(Noise + Distortion) Ratio SNDR 65 75 — dB TA = –40°C to +105°C; see Definitions 9 Effective Number of Bits ENOB — 12 — Bits See Definitions Isolation Transient Immunity CMR — 25 — kV/μs Common-Mode Rejection Ratio CMRR — 74 — dB Output High Voltage VOH VDD2 – 0.2 VDD2 – 0.1 — V IOUT = –200 μA Output Low Voltage VOL — 0.6 V IOUT = +1.6 mA VDD1 Supply Current IDD1 — 9 14 mA VIN+ = –320 mV to +320 mV 10 VDD2 Supply Current IDD2 — 5.2 8 mA VDD1 = 5-V supply 11 — 4.6 7 mA VDD1 = 3.3-V supply 12 VCM = 1 kV; see Definitions Digital Outputs Power Supply a. All Typical values are at TA = 25°C, VDD1 = 5V, VDD2 = 5 . b. VREF Drift vs. VDD1 can be expressed as -0.4%/V with reference to VREF. c. Beyond the full-scale input range the data output is either all zeroes or all ones. d. Because of the switched-capacitor nature of the isolated modulator, time averaged values are shown. Broadcom -7- d d VIN+ = 400 mVpp, 1-kHz sine wave Dynamic Characteristics Signal-to-Noise Ratio c ACPL-C797 Data Sheet Timing Specifications Unless otherwise noted, TA = –40°C to +105°C, VDD1 = 4.5V to 5.5V, VDD2 = 3V to 5.5V. Table 9 Timing Specifications Parameter Symbol Min. Typ. Max. Units fMCLK 9 10 11 MHz Data Access Time After MCLK Rising Edge tA — — 40 Data Hold Time After MCLK Rising Edge tH 10 — Symbol Min. Input-Output Momentary Withstand Voltage VISO Input-Output Resistance Input-Output Capacitance Modulator Clock Output Frequency Test Conditions/Notes Figure CL = 15 pF, Clock duty cycle 40% to 60% 13 ns CL = 15 pF 4 — ns CL = 15 pF 4 Typ.[1] Max. Units 5000 — — Vrms RI-O — >1012 —  VI-O = 500 Vdc c CI-O — 0.5 — pF f = 1 MHz c Figure 4 Data Timing MCLK tA tH MDAT Package Characteristics Table 10 Package Characteristics Parameter Test Conditions/Notes RH ≤ 50%, t = 1 min; TA = 25°C Note a, b a. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 Vrms for 1 second (leakage detection current limit, II-O ≤ 5 μA). This test is performed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-5 Insulation Characteristic Table. b. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating, refer to the IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table and your equipment level safety specification. c. This is a two-terminal measurement: pins 1–4 are shorted together and pins 5–8 are shorted together. Broadcom -8- ACPL-C797 Data Sheet Typical Performance Plots Unless otherwise noted, TA = 25°C, VDD1 = 5V, VDD2 = 5V, VIN+ = –200 mV to +200 mV, and VIN- = 0V, with Sinc3 filter, 256 decimation ratio. Figure 5 Offset Change vs. Temperature Figure 6 VREF Change vs. Temperature 2.0 335 1.5 330 325 0.5 VREF (mV) VOS (mV) 1.0 0.0 -0.5 320 315 -1.0 310 -1.5 -2.0 -55 -35 -15 5 25 45 65 Temperature (°C) 85 105 305 125 Figure 7 Input Current vs. Input Voltage 20 SNR (dB) IIN+ (PA) 10 0 -10 -20 160 240 320 400 -15 5 25 45 65 Temperature (°C) 85 105 125 85 105 125 86 84 82 80 78 76 74 72 70 68 66 -55 -35 -15 5 25 45 65 Temperature (°C) Figure 10 IDD1 vs. VIN DC Input at Various Temperatures 12.0 11.0 10.0 IDD1 (mA) SNDR (dB) Figure 9 SNDR vs. Temperature 86 84 82 80 78 76 74 72 70 68 66 -35 Figure 8 SNR vs. Temperature 30 -30 -400 -320 -240 -160 -80 0 80 VIN+ (mV) -55 9.0 8.0 7.0 25° C -40° C 105° C 6.0 -55 -35 -15 5 25 45 65 Temperature (°C) 85 105 5.0 -400 125 Broadcom -9- -300 -200 -100 0 100 VIN (mV) 200 300 400 ACPL-C797 Data Sheet Figure 11 IDD2 (VDD2 = 5V) vs. VIN DC Input at Various Temperatures Figure 12 IDD2 (VDD2 = 3.3V) vs. VIN DC Input at Various Tempeatures 8.0 8.0 VDD2 = 3.3 V 25° C -40° C 105° C 7.0 6.0 IDD2 (mA) IDD2 (mA) 6.0 5.0 4.0 3.0 3.0 2.0 -400 -300 -200 -100 0 100 VIN (mV) 200 300 2.0 -400 400 Figure 13 Clock Frequency vs. Temperature for Various VDD1 Clock Frequency (MHz) 5.0 4.0 10.5 10.4 10.3 10.2 10.1 10.0 9.9 9.8 9.7 9.6 9.5 25° C -40° C 105° C 7.0 4.5V 5V 5.5V -55 -35 -15 5 25 45 65 Temperature (°C) 85 105 125 Broadcom - 10 - -300 -200 -100 0 100 VIN (mV) 200 300 400 ACPL-C797 Data Sheet Definitions Effective Number of Bits (ENOB) Integral Nonlinearity (INL) The ENOB determines the effective resolution of an ADC, expressed in bits, defined by ENOB = (SNDR –1.76) / 6.02. INL is the maximum deviation of a transfer curve from a straight line passing through the endpoints of the ADC transfer function, with offset and gain errors adjusted out. Isolation Transient Immunity (CMR) Differential Nonlinearity (DNL) DNL is the deviation of an actual code width from the ideal value of 1 LSB between any two adjacent codes in the ADC transfer curve. DNL is a critical specification in closed-loop applications. A DNL error of less than ±1 LSB guarantees no missing codes and a monotonic transfer function. The isolation transient immunity (also known as Common-Mode Rejection or CMR) specifies the minimum rate-of-rise/fall of a common-mode signal applied across the isolation boundary beyond which the modulator clock or data is corrupted. Product Overview Description Offset Error Offset error is the deviation of the actual input voltage corresponding to the mid-scale code (32,768 for a 16-bit system with an unsigned decimation filter) from 0V. Offset error can be corrected by software or hardware. Gain Error (Full-Scale Error) Gain error includes positive full-scale gain error and negative full-scale gain error. Positive full-scale gain error is the deviation of the actual input voltage corresponding to positive full-scale code (65,535 for a 16-bit system) from the ideal differential input voltage (VIN+ – VIN- = +320 mV), with offset error adjusted out. Negative full-scale gain error is the deviation of the actual input voltage corresponding to negative full-scale code (0 for a 16-bit system) from the ideal differential input voltage (VIN+ – VIN- = –320 mV), with offset error adjusted out. Gain error includes reference error. Gain error can be corrected by software or hardware. Signal-to-Noise Ratio (SNR) The SNR is the measured ratio of AC signal power to noise power below half of the sampling frequency. The noise power excludes harmonic signals and DC. Signal-to-(Noise + Distortion) Ratio (SNDR) The ACPL-C797 isolated sigma-delta (-) modulator converts an analog input signal into a high-speed (10 MHz typical) single-bit data stream by means of a sigma-delta over-sampling modulator. The time average of the modulator data is directly proportional to the input signal voltage. The modulator uses internal clock of 10 MHz. The modulator data is encoded and transmitted across the isolation boundary where it is recovered and decoded into high-speed data stream of digital ones and zeros. The original signal information is represented by the density of ones in the data output. The other main function of the modulator (optocoupler) is to provide galvanic isolation between the analog signal input and the digital data output. It provides high noise margins and excellent immunity against isolation-mode transients that allows direct measurement of low-level signals in highly noisy environments; for example, measurement of motor phase currents in power inverters. With 0.5-mm minimum DTI, the ACPL-C797 provides reliable double protection and high working insulation voltage, which is suitable for fail-safe designs. This outstanding isolation performance is superior to alternatives including devices based on capacitive- or magnetic-coupling with DTI in micro-meter range. Offered in an SSO-8 package, the isolated ADC delivers the reliability, small size, superior isolation and over-temperature performance, motor drive designers must accurately measure current at much lower price compared to traditional current transducers. The SNDR is the measured ratio of AC signal power to noise plus distortion power at the output of the ADC. The signal power is the rms amplitude of the fundamental input signal. Noise plus distortion power is the rms sum of all non-fundamental signals up to half the sampling frequency (excluding DC). Broadcom - 11 - ACPL-C797 Data Sheet Analog Input Latch-up Consideration The differential analog inputs of the ACPL-C797 are implemented with a fully-differential, switched-capacitor circuit. The ACPL-C797 accepts a signal of ±200 mV (full scale ±320 mV), which is ideal for direct connection to shunt-based current sensing or other low-level signal sources applications, such as motor phase current measurement. An internal voltage reference determines the full-scale analog input range of the modulator (±320 mV); an input range of ±200 mV is recommended to achieve optimal performance. Users are able to use higher input ranges, for example ±250 mV, as long as within full-scale range, for purpose of over-current or overload detection. Figure 14 shows the simplified equivalent circuit of the analog input. Latch-up risk of CMOS devices needs careful consideration, especially in applications with direct connection to signal source that is subject to frequent transient noise. The analog input structure of the ACPL-C797 is designed to be resilient to transients and surges, which are often encountered in highly noisy application environments, such as motor drive and other power inverter systems. Other situations could cause transient voltages to the inputs include short circuit and overload conditions. The ACPL-C797 is tested with DC voltage of up to –2V and 2-second transient voltage of up to –6V to the analog inputs with no latch-up or damage to the device. In the typical application circuit (Figure 17), the ACPL-C797 is connected in a single-ended input mode. Given the fully differential input structure, a differential input connection method (balanced input mode as shown in Figure 15) is recommended to achieve better performance. The input currents created by the switching actions on both of the pins are balanced on the filter resistors and cancelled out each other. Any noise induced on one pin will be coupled to the other pin by the capacitor C and creates only common mode noise which is rejected by the device. Typical values for Ra (= Rb) and C are 22  and 10 nF, respectively. Figure 14 Analog Input Equivalent Circuit Modulator Data Output Input signal information is contained in the modulator output data stream, represented by the density of ones and zeros. The density of ones is proportional to the input signal voltage, as shown in Figure 16. A differential input signal of 0V ideally produces a data stream of ones and zeros in equal densities. A differential input of –200 mV corresponds to 18.75-percent density of ones, and a differential input of +200 mV is represented by 81.25-percent density of ones in the data stream. A differential input of +320 mV or higher results in ideally all ones in the data stream, while input of –320 mV or lower will result in all zeros ideally. Table 11 shows this relationship. 200 : (TYP) VIN+ fSWITCH = MCLK 3 pF (TYP) 1.5 pF ANALOG GROUND 1.5 pF fSWITCH = MCLK COMMON MODE VOLTAGE 3 pF (TYP) 200 : (TYP) VIN– Figure 15 Simplified Differential Input Connection Diagram 5V VDD1 Ra +Analog Input VIN+ Rb –Analog Input C ACPL-C797 VIN– GND1 Broadcom - 12 - ACPL-C797 Data Sheet Figure 16 Modulator Output vs. Analog Input MODULATOR OUTPUT +FS (ANALOG INPUT) 0 V (ANALOG INPUT) –FS (ANALOG INPUT) ANALOG INPUT TIME Table 11 Input Voltage with Ideal Corresponding Density of 1s at Modulator Data Output, and ADC Code Analog Input Voltage Input Density of 1s Density of 0s ADC Code (16-bit Unsigned Decimation) +Full-Scale +320 mV 100% 0% 65,535 +Recommended Input Range +200 mV 81.25% 18.75% 53,248 Zero 0 mV 50% 50% 32,768 –Recommended Input Range –200 mV 18.75% 81.25% 12,288 –Full-Scale –320 mV 0% 100% 0 NOTE 1. 2. With bipolar offset binary coding scheme, the digital code begins with digital 0 at –FS input and increases proportionally to the analog input until the full-scale code is reached at the +FS input. The zero crossing occurs at the mid-scale input. Ideal density of 1s at modulator data output can be calculated with VIN/640 mV + 50%; similarly, the ADC code can be calculated with (VIN/640 mV) × 65,536 + 32,768, assuming a 16-bit unsigned decimation filter. Digital Filter A digital filter converts the single-bit data stream from the modulator into a multi-bit output word similar to the digital output of a conventional A/D converter. With this conversion, the data rate of the word output is also reduced (decimation). A Sinc3 filter is recommended to work together with the ACPL-C797. With 256 decimation ratio and 16-bit word settings, the output data rate is 39 kHz (= 10 MHz/256). This filter can be implemented in an ASIC, an FPGA, or a DSP. Some of the ADC codes with corresponding input voltages are shown in Table 11. Broadcom - 13 - ACPL-C797 Data Sheet Application Information Typical Application Circuit Figure 17 shows a typical application circuit for motor control phase current sensing. By choosing the appropriate shunt resistance, a wide range of current can be monitored, from less than 1A to more than 100A. Figure 17 Typical Application Circuit in Motor Phase Current Setting FLOATING POSITIVE SUPPLY HV+ R1 GATE DRIVE CIRCUIT D1 5.1V MOTOR V IN + – C2 10nF R SENSE C1b 10μF V DD2 V DD1 R2 43 Ω + NON ISOLATED 5V/3.3V ISOLATION BARRIER C1a 0.1μF MCLK C3a 0.1μF V IN – MDAT GND1 GND2 GND1 ACPL -C797 C3b 10μF GND2 HV – Shunt Resistors The current-sensing shunt resistor should have low resistance (to minimize power dissipation), low inductance (to minimize di/dt induced voltage spikes which could adversely affect operation), and reasonable tolerance (to maintain overall circuit accuracy). Choosing a particular value for the shunt is usually a compromise between minimizing power dissipation and maximizing accuracy. Smaller shunt resistances decrease power dissipation, while larger shunt resistances can improve circuit accuracy by utilizing the full input range of the isolated modulator. Figure 18 Motor Output Horsepower vs. Motor Phase Current and Supply MOTOR OUTPUT POWER HORSEPOWER 110 100 440 Vac 90 380 Vac 80 220 Vac 70 120 Vac 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 MOTOR PHASE CURRENT - A (rms) Broadcom - 14 - ACPL-C797 Data Sheet The first step in selecting a shunt is determining how much current the shunt will be sensing. The graph in Figure 18 shows the RMS current in each phase of a three-phase induction motor as a function of average motor output power (in horsepower, hp) and motor drive supply voltage. The maximum value of the shunt is determined by the current being measured and the maximum recommended input voltage of the isolated modulator. The maximum shunt resistance can be calculated by taking the maximum recommended input voltage and dividing by the peak current that the shunt should see during normal operation. For example, if a motor will have a maximum RMS current of 35 Arms and can experience up to 50-percent overloads during normal operation, the peak current is 75A (= 35 × 1.414 × 1.5). Assuming a maximum input voltage of 200 mV without overload condition, the maximum value of shunt resistance in this case would be about 4 m. Under overload conditions, the maximum input voltage will then be 300 mV (75A × 4 m), well within the ±320 mV FSR. The maximum average power dissipation in the shunt can also be easily calculated by multiplying the shunt resistance times the square of the maximum RMS current, which is about 4.9W in the previous example. If the power dissipation in the shunt is too high, the resistance of the shunt can be decreased below the maximum value to decrease power dissipation. The minimum value of the shunt is limited by precision and accuracy requirements of the design. As the shunt value is reduced, the output voltage across the shunt is also reduced, which means that the offset and noise, which are fixed, become a larger percentage of the signal amplitude. The selected value of the shunt will fall somewhere between the minimum and maximum values, depending on the particular requirements of a specific design. When sensing currents large enough to cause significant heating of the shunt, the temperature coefficient (tempco) of the shunt can introduce nonlinearity due to the signal dependent temperature rise of the shunt. The effect increases as the shunt-to-ambient thermal resistance increases. This effect can be minimized either by reducing the thermal resistance of the shunt or by using a shunt with a lower tempco. Lowering the thermal resistance can be accomplished by repositioning the shunt on the PC board, by using larger PC board traces to carry away more heat, or by using a heat sink. For a two-terminal shunt, as the value of shunt resistance decreases, the resistance of the leads becomes a significant percentage of the total shunt resistance. This has two primary effects on shunt accuracy. First, the effective resistance of the shunt can become dependent on factors such as how long the leads are, how they are bent, how far they are inserted into the board, and how far solder wicks up the lead during assembly (these issues will be discussed in more detail shortly). Secondly, the leads are typically made from a material such as copper, which has a much higher tempco than the material from which the resistive element itself is made, resulting in a higher tempco for the shunt overall. Both of these effects are eliminated when a four-terminal shunt is used. A four-terminal shunt has two additional terminals that are Kelvin-connected directly across the resistive element itself; these two terminals are used to monitor the voltage across the resistive element while the other two terminals are used to carry the load current. Because of the Kelvin connection, any voltage drops across the leads carrying the load current should have no impact on the measured voltage. Several two-terminal and four-terminal surface mount type shunt resistors from various suppliers suitable for sensing currents in motor drives up to 70 Arms (71 hp or 53 kW) are shown as examples in Table 12. Table 12 Example of Two-Terminal and Four Terminal Shunt Resistors for Motor Drives up to 70 Arms Manufacturer KOA Sunt Resistor Part Number CSR series Shunt Resistance Maximum RMS Current m A hp kW Four-terminal 20 7 1.8–6.7 1.4–5 Shunt Resistor Type Motor Power Range 120Vac to 440Vac TT Electronics LRMA series Two-terminal — — — — Vishay WSL3637 Four-terminal 8 17 4–17 3–13 Isabellenhütte SMS R008 Two-terminal — — — — Vishay WSLP4026 Four-terminal 4 35 9–36 7–27 KOA SLN5 series Two-terminal — — — — Vishay WSLP2818 Two-terminal 2 70 19–72 14–54 Broadcom - 15 - ACPL-C797 Data Sheet When laying out a PC board for the shunts, a couple of points should be kept in mind. The Kelvin connections to the shunt should be brought together under the body of the shunt and then run very close to each other to the input of the isolated modulator; this minimizes the loop area of the connection and reduces the possibility of stray magnetic fields from interfering with the measured signal. If the shunt is not located on the same PC board as the isolated modulator circuit, a tightly twisted pair of wires can accomplish the same thing. Also, multiple layers of the PC board can be used to increase current carrying capacity. Numerous plated-through vias should surround each non-Kelvin terminal of the shunt to help distribute the current between the layers of the PC board. The PC board should use 2-oz. or 4-oz. copper for the layers, resulting in a current carrying capacity in excess of 20A. Making the current carrying traces on the PC board fairly large can also improve the shunt's power dissipation capability by acting as a heat sink. Liberal use of vias where the load current enters and exits the PC board is also recommended. Shunt Connections The recommended method for connecting the isolated modulator to the shunt resistor is shown in Figure 17. VIN+ of the ACPL-C797 is connected to the positive terminal of the shunt resistor, while VIN- is shorted to GND1, with the power-supply return path functioning as the sense line to the negative terminal of the current shunt. This allows a single pair of wires or PC board traces to connect the isolated modulator circuit to the shunt resistor. By referencing the input circuit to the negative side of the sense resistor, any load current induced noise transients on the shunt are seen as a common-mode signal and will not interfere with the current-sense signal. This is important because the large load currents flowing through the motor drive, along with the parasitic inductances inherent in the wiring of the circuit, can generate both noise spikes and offsets that are relatively large compared to the small voltages that are being measured across the current shunt. If the same power supply is used both for the gate drive circuit and for the current sensing circuit, it is very important that the connection from GND1 of the isolated modulator to the sense resistor be the only return path for supply current to the gate drive power supply in order to eliminate potential ground loop problems. The only direct connection between the isolated modulator circuit and the gate drive circuit should be the positive power supply line. In some applications, however, supply currents flowing through the power-supply return path may cause offset or noise problems. In this case, better performance may be obtained by connecting VIN+ and VIN- directly across the shunt resistor with two conductors, and connecting GND1 to the shunt resistor with a third conductor for the power-supply return path, as shown in Figure 19. The input currents induced by the common-mode of the fully differential amplifier on both of the pins are balanced on the filter resistors, R2a and R2b, and cancelled out each other. Any noise induced on one pin will be coupled to the other pin by the capacitor C2 and creates only common mode noise which is rejected by the device. When connected this way, both input pins should be bypassed. To minimize electromagnetic interference of the sense signal, all of the conductors (whether two or three are used) connecting the isolated modulator to the sense resistor should be either twisted pair wire or closely spaced traces on a PC board. Broadcom - 16 - ACPL-C797 Data Sheet Figure 19 Schematic for Three Conductor Shunt Connection FLOATING POSITIVE SUPPLY HV+ R1 GATE DRIVE CIRCUIT D1 5.1V V DD1 R2a 22Ω V IN + R2b 22Ω MOTOR + NON ISOLATED 5V/3.3V ISOLATION BARRIER C2 10nF C1b 10μF C1a 0.1μF V DD2 MCLK C3a 0.1μF V IN – MDAT GND1 GND2 C3b 10μF – R SENSE ACPL -C799 GND2 GND1 HV – The resistors R2 in Figure 17 or R2a and R2b in Figure 19 which are in series with the input leads form a low pass anti-aliasing filter with the input bypass capacitor C2. These resistors perform another important function as well; to dampen any ringing which might present in the circuit formed by the shunt, the input bypass capacitor, and the inductance of wires or traces connecting the two. Undamped ringing of the input circuit near the input sampling frequency can alias into the baseband producing what might appear to be noise at the output of the device. PC Board Layout The design of the printed circuit board (PCB) should follow good layout practices, such as keeping bypass capacitors close to the supply pins, keeping output signals away from input signals, the use of ground and power planes, and so on. In addition, the layout of the PCB can also affect the isolation transient immunity (CMR) of the isolated modulator, due primarily to stray capacitive coupling between the input and the output circuits. To obtain optimal CMR performance, the layout of the PC board should minimize any stray coupling by maintaining the maximum possible distance between the input and output sides of the circuit and ensuring that any ground or power plane on the PC board does not pass directly below or extend much wider than the body of the isolated modulator. Voltage Sensing The ACPL-C797 can also be used to isolate signals with amplitudes larger than its recommended input range with the use of a resistive voltage divider at its input. The only restrictions are that the impedance of the divider be relatively small (less than 1 k) so that the input resistance (24 k) and input bias current (0.3 μA) do not affect the accuracy of the measurement. An input bypass capacitor is still required, although the damping resistor is not (the resistance of the voltage divider provides the same function). The low-pass filter formed by the divider resistance and the input bypass capacitor may limit the achievable bandwidth. To obtain higher bandwidth, the input bypass capacitor (C2) can be reduced, but it should not be reduced much below 1000 pF to maintain adequate input bypassing of the isolated modulator. Broadcom - 17 - For product information and a complete list of distributors, please go to our web site: www.broadcom.com. Broadcom, the pulse logo, Connecting everything, Avago Technologies, Avago, and the A logo are among the trademarks of Broadcom and/or its affiliates in the United States, certain other countries and/or the EU. Copyright © 2017 by Broadcom. All Rights Reserved. The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries. For more information, please visit www.broadcom.com. Broadcom reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by Broadcom is believed to be accurate and reliable. However, Broadcom does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AV02-2581EN – June 23, 2017