ACPL-C79A-000E

ACPL-C79B, ACPL-C79A, ACPL-C790 Precision Miniature Isolation Amplifiers Data Sheet Description Features The ACPL-C79B/C79A/C790 isolation amplifiers are designed for current and voltage sensing in electronic power converters in applications including motor drives and renewable energy systems. In a typical motor drive implementation, current flows through an external resistor and the resulting analog voltage drop is sensed by the isolation amplifier. A differential output voltage that is proportional to the current is created on the other side of the optical isolation barrier. • ±0.5% High Gain Accuracy (ACPL-C79B) For general applications, the ACPL-C79A (±1% gain tolerance) and the ACPL-C790 (±3% gain tolerance) are recommended. For high precision applications, the ACPL-C79B (±0.5% gain tolerance) can be used. The product operates from a single 5 V supply and provides excellent linearity and dynamic performance of 60 dB SNR. With 200 kHz bandwidth, 1.6 µs fast response time, the product captures transients in short circuit and overload conditions. The high common-mode transient immunity (15 kV/µs) of the ACPL-C79B/C79A/C790 provides the precision and stability needed to accurately monitor motor current in high noise motor control environments, providing for smoother control (less “torque ripple”) in various types of motor control applications. • –40°C to +105°C Operating Temperature Range Combined with superior optical coupling technology, the ACPL-C79B/C79A/C790 implements sigma-delta (∑-∆) analog-to-digital converter, chopper stabilized amplifiers, and a fully differential circuit topology to provide unequaled isolation-mode noise rejection, low offset, high gain accuracy and stability. This performance is delivered in a compact, auto-insertable Stretched SO-8 (SSO-8) package that meets worldwide regulatory safety standards. • Current/Voltage Sensing in AC and Servo Motor Drives • –50 ppm/°C Low Gain Drift • 0.6 mV Input Offset Voltage • 0.05% Excellent Linearity • 60 dB SNR • 200 kHz Wide Bandwidth • 3 V to 5.5 V Wide Supply Range for Output Side • Advanced Sigma-Delta (∑-∆) A/D Converter Technology • Fully Differential Isolation Amplifier • 15 kV/µs Common-Mode Transient Immunity • Compact, Auto-Insertable Stretched SO-8 Package • Safety and Regulatory Approvals: – IEC/EN/DIN EN 60747-5-5: 1414 Vpeak working insulation voltage – UL 1577: 5000 Vrms/1min double protection rating – CSA: Component Acceptance Notice #5 Applications • Solar Inverters, Wind Turbine Inverters • Industrial Process Control • Data acquisition systems • Switching Power Supply Signal Isolation • General Purpose Analog Signal Isolation • Traditional Current Transducer Replacements Functional Diagram VDD1 1 IDD1 IDD2 8 VDD2 VIN+ 2 + + 7 VOUT+ VIN- 3 - - 6 VOUT- GND1 4 SHIELD 5 GND2 NOTE: A 0.1 μF bypass capacitor must be connected between pins 1 and 4 and between pins 5 and 8. Figure 1. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Table 1. Pin Description Pin No. Symbol Description 1 VDD1 Supply voltage for input side (4.5 V to 5.5 V), relative to GND1 2 VIN+ Positive input (± 200 mV recommended) 3 VIN– Negative input (normally connected to GND1) 4 GND1 Input side ground 5 GND2 Output side ground 6 VOUT– Negative output 7 VOUT+ Positive output 8 VDD2 Supply voltage for output side (3 V to 5.5 V), relative to GND2 Table 2. Ordering Information ACPL-C79B/C79A/C790 is UL recognized with 5000 Vrms/1 minute rating per UL 1577. Part number ACPL-C79B ACPL-C79A ACPL-C790 Option (RoHS Compliant) -000E -500E Package Stretched SO-8 Surface Mount Tape & Reel X X X IEC/EN/DIN EN 60747-5-5 Quantity X 80 per tube X 1000 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example: ACPL-C79B-500E to order product of Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval and RoHS compliance. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. 2 Package Outline Drawings Stretched SO-8 Package (SSO-8) RECOMMENDED LAND PATTERN 5.850 ± 0.50 (0.230 ± 0.010) PART NUMBER 8 RoHS-COMPLIANCE INDICATOR 7 6 5 C79B YYWW EEE 1 2 3 DATE CODE 12.650 (0.5) 6.807 ± 0.127 (0.268 ± 0.005) 1.905 (0.1) 4 LOT ID 7° 3.180 ± 0.127 (0.125 ± 0.005) 0.381 ± 0.130 (0.015 ± 0.005) 45° 0.450 (0.018) 0.750 ± 0.250 (0.0295 ± 0.010) 1.590 ± 0.127 (0.063 ± 0.005) 0.200 ± 0.100 (0.008 ± 0.004) 11.50 ± 0.250 (0.453 ± 0.010) 1.270 (0.050) BSG Dimensions in millimeters and (inches). Lead coplanarity = 0.1 mm (0.004 inches). Figure 2. SSO-8 package. Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used. Regulatory Information The ACPL-C79B/C79A/C790 is approved by the following organizations: IEC/EN/DIN EN 60747-5-5 Approved with Maximum Working Insulation Voltage VIORM = 1414 Vpeak. UL Approval under UL 1577, component recognition program up to VISO = 5000 Vrms/1min. File E55361. CSA Approval under CSA Component Acceptance Notice #5, File CA 88324. 3 Table 3. Insulation and Safety Related Specifications Parameter Symbol Value Units Conditions Minimum External Air Gap (External Clearance) L(101) 8.0 mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (External Creepage) L(102) 8.0 mm Measured from input terminals to output terminals, shortest distance path along body 0.5 mm Through insulation distance, conductor to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity >175 V DIN IEC 112/VDE 0303 Part 1 Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) CTI Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Table 4. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics [1] Description Symbol Value Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤ 150 Vrms for rated mains voltage ≤ 300 Vrms for rated mains voltage ≤ 450 V rms for rated mains voltage ≤ 600 Vrms for rated mains voltage ≤ 1000 Vrms I-IV I-IV I-IV I-IV I-III Climatic Classification 55/105/21 Pollution Degree (DIN VDE 0110/1.89) 2 Units Maximum Working Insulation Voltage VIORM 1414 Vpeak Input to Output Test Voltage, Method b VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC VPR 2652 Vpeak Input to Output Test Voltage, Method a VIORM x 1.6 = VPR, Type and Sample Test, tm = 10 sec, Partial Discharge < 5 pC VPR 2262 Vpeak Highest Allowable Overvoltage (Transient Overvoltage, tini = 60 sec) VIOTM 8000 Vpeak Safety-limiting values (Maximum values allowed in the event of a failure) Case Temperature Input Current [2] Output Power [2] TS IS,INPUT PS,OUTPUT 175 230 600 °C mA mW Insulation Resistance at TS, VIO = 500 V RS ≥ 109 Ω Notes: 1. Insulation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits within the application. 2. Safety-limiting parameters are dependent on ambient temperature. The Input Current, IS,INPUT, derates linearly above 25°C free-air temperature at a rate of 2.53 mA/°C; the Output Power, PS,OUTPUT, derates linearly above 25°C free-air temperature at a rate of 4 mW/°C. 4 Table 5. Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature TS –55 +125 °C Ambient Operating Temperature TA –40 +105 °C Supply Voltages VDD1, VDD2 –0.5 6.0 V Steady-State Input Voltage [1, 3] VIN+, VIN– –2 VDD1 + 0.5 V Two-Second Transient Input Voltage [2] VIN+, VIN– –6 VDD1 + 0.5 V Output Voltages VOUT+, VOUT– –0.5 VDD2 + 0.5 V Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane Notes: 1. DC voltage of up to –2 V on the inputs does not cause latch-up or damage to the device; tested at typical operating conditions. 2. Transient voltage of 2 seconds up to –6 V on the inputs does not cause latch-up or damage to the device; tested at typical operating conditions. 3. Absolute maximum DC current on the inputs = 100 mA, no latch-up or device damage occurs. Table 6. Recommended Operating Conditions Parameter Symbol Min. Max. Units Ambient Operating Temperature TA –40 +105 °C VDD1 Supply Voltage VDD1 4.5 5.5 V VDD2 Supply Voltage VDD2 3 5.5 V Input Voltage Range [1] VIN+, VIN– –200 +200 mV Notes: 1. ±200 mV is the nominal input range. Full scale input range (FSR) is ±300 mV. Functional input range is ±2 V. 5 Table 7. Electrical Specifications Unless otherwise noted, TA = –40°C to +105°C, VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, VIN+ = –200 mV to +200 mV, and VIN– = 0 V (single-ended connection). Symbol Min. Typ.[1] Max. Unit Test Conditions/Notes Fig. Input Offset Voltage VOS –1 0.6 2 mV TA = 25°C 3, 4 Magnitude of Input Offset Change vs. Temperature |dVOS/dTA| 3 10 µV/°C TA = –40°C to +105°C; absolute value 5 Gain (ACPL-C79B, ±0.5%) G0 8.16 8.2 8.24 V/V TA = 25°C; Note 2 6, 7 Gain (ACPL-C79A, ±1%) G1 8.12 8.2 8.28 V/V TA = 25°C; Note 2 6, 7 Gain (ACPL-C790, ±3%) G3 7.95 8.2 8.44 V/V TA = 25°C; Note 2 6, 7 Magnitude of Gain Change vs. Temperature dG/dTA –0.00041 V/V/°C TA = –40°C to +105°C; Note 3 8 Nonlinearity over ±200 mV Input Voltage NL200 0.05 % VIN+ = –200 mV to +200 mV, TA = 25°C; Note 2 9, 10 Magnitude of NL200 Change vs. Temperature dNL200/dTA 0.0003 %/°C TA = –40°C to +85°C 11 %/°C TA = +85°C to +105°C 11 Nonlinearity over ±100 mV Input Voltage NL100 0.02 % VIN+ = –100 mV to +100 mV, TA = 25°C; Note 2 9, 10, 11 FSR ±300 mV VIN = VIN+ – VIN–; Note 4 12 VIN+ = 0 V, VIN– = 0 V; Note 5 13 14 Parameter DC CHARACTERISTICS 0.13 0.004 0.06 INPUTS AND OUTPUTS Full-Scale Differential Voltage Input Range Input Bias Current IIN+ –0.1 µA Magnitude of IIN+ Change vs. Temperature dIIN+/dTA –0.05 nA/°C Equivalent Input Impedance RIN 22 kΩ VIN+ or VIN–, single-ended Output Common-Mode Voltage VOCM 1.23 V VOUT+ or VOUT–; Note 6 Output Voltage Range OVR 0 to 2.5 V VOUT+ or VOUT–; Note 4 Output Short-Circuit Current |IOSC| 11 mA VOUT+ or VOUT–, shorted to GND2 or VDD2 Output Resistance ROUT 21 Ω VOUT+ or VOUT– Input DC Common-Mode Rejection Ratio CMRRIN 76 dB Note 2 Signal-to-Noise Ratio SNR 60 dB VIN+ = 300 mVpp 10 kHz sine wave; Note 7 15, 16 Signal-to-(Noise + Distortion) Ratio SNDR 56 dB VIN+ = 300 mVpp 10 kHz sine wave; Note 8 15, 16 Small-Signal Bandwidth (-3 dB) f–3 dB Input to Output 10%-10% Propagation Delay 50%-50% tPD10 1.6 2.3 µs 200 mV/µs step input 19 tPD50 2 2.6 µs 200 mV/µs step input 19 90%-90% tPD90 2.6 3.3 µs 200 mV/µs step input 19 Output Rise/Fall Time (10%-90%) tR/F 1.7 µs Step input 19 Common Mode Transient Immunity CMTI 15 kV/μs VCM = 1 kV, TA = 25°C; Note 2 Power Supply Rejection PSR –78 dB 1 Vpp 1 kHz sine wave ripple on VDD1, differential output; Note 9 Input Side Supply Current IDD1 13 18.5 mA VIN+ = 400 mV; see Note 10 20 Output Side Supply Current IDD2 7 12 mA 5 V supply 20 6.8 11 mA 3.3 V supply 20 –1 12 AC CHARACTERISTICS 140 10 200 kHz 17, 18 POWER SUPPLIES 6 Notes: 1. All Typical values are under Typical Operating Conditions at TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V. 2. See Definitions section. 3. Gain temperature drift can be normalized and expressed as Temperature Coefficient of Gain (TCG) of –50 ppm/°C. 4. When FSR is exceeded, outputs saturate. 5. Because of the switched-capacitor nature of the input sigma-delta converter, time-averaged values are shown. 6. Under Typical Operating Conditions, part-to-part variation ±0.04 V. 7. Under Typical Operating Conditions, part-to-part variation ±1 dB. 8. Under Typical Operating Conditions, part-to-part variation ±1 dB. 9. Ripple voltage applied to VDD1 with a 0.1 µF bypass capacitor connected; differential amplitude of the ripple outputs measured. See Definitions section. 10. The input supply current decreases as the differential input voltage (VIN+ – VIN–) decreases. Table 8. Package Characteristics Parameter Symbol Min. Input-Output Momentary Withstand Voltage VISO 5000 Resistance (Input-Output) RI-O Capacitance (Input-Output) CI-O Typ. Max. Unit Test Condition Note Vrms RH < 50%, t = 1 min., TA = 25°C 1, 2 >1012 Ω VI-O = 500 VDC 3 0.5 pF f = 1 MHz 3 Notes: 1. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 Vrms for 1 second (leakage detection current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 607475-5 Insulation Characteristic Table. 2. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating, refer to the IEC/EN/DIN EN 60747-5-5 insulation characteristics table and your equipment level safety specification. 3. This is a two-terminal measurement: pins 1–4 are shorted together and pins 5–8 are shorted together. 7 Typical Performance Plots 1.0 1.0 0.9 0.9 0.8 0.8 0.7 VDD2 = 3.3V 0.6 OFFSET - mV OFFSET - mV Unless otherwise noted, TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V. VDD2 = 5V 0.5 0.4 0.4 4.75 5 5.25 VDD1 - SUPPLY VOLTAGE - V 0.3 5.5 Figure 3. Input offset vs. supply VDD1. 1.0 8.24 0.9 8.23 0.7 0.6 0.5 4 4.5 VDD2 - SUPPLY VOLTAGE - V 5 5.5 8.21 8.20 VDD2 = 3.3V VDD2 = 5V 8.19 8.18 0.4 8.17 0.3 -40 -20 0 20 40 60 TA - TEMPERATURE - °C 80 100 8.16 4.5 120 Figure 5. Input offset vs. temperature. 8.23 8.26 8.22 8.24 8.21 8.22 G - GAIN - V/V 8.28 8.20 VDD1 = 5V 8.19 8.17 8.14 4 4.5 VDD2 - SUPPLY VOLTAGE - V Figure 7. Gain vs. supply VDD2. 5.5 8.18 8.16 3.5 5 5.25 VDD1 - SUPPLY VOLTAGE - V 8.20 8.18 3 4.75 Figure 6. Gain vs. supply VDD1. 8.24 8.16 3.5 8.22 GAIN - V/V OFFSET - mV 3 Figure 4. Input offset vs. supply VDD2. 0.8 GAIN - V/V VDD1 = 5V 0.6 0.5 0.3 4.5 8 0.7 5 5.5 8.12 -40 -20 0 20 40 60 TA - TEMPERATURE - °C Figure 8. Gain vs. temperature. 80 100 120 0.050 0.045 0.045 NL200, VDD2 = 5V 0.040 NL - NONLINEARITY - % NL - NONLINEARITY - % 0.050 NL200, VDD2 = 3.3V 0.035 0.030 0.025 NL100, VDD2 = 5V 0.020 NL100, VDD2 = 3.3V 0.010 4.5 4.75 5 5.25 VDD1 - SUPPLY VOLTAGE - V 0.025 NL100 0.020 3 3.5 4 4.5 VDD2 - SUPPLY VOLTAGE - V 5 5.5 3.0 2.5 VOUT - OUTPUT VOLTAGE - V NL - LINEARITY - % NL200 NL100 -20 0 20 40 60 TA - TEMPERATURE - °C 80 100 VOUT– 2.0 VOUT+ 1.5 1.0 0.5 0.0 -0.5 -0.4 120 -0.3 -0.2 -0.1 0 0.1 0.2 VIN+ - INPUT VOLTAGE - V 0.3 0.4 Figure 12. Output voltage vs. input voltage. 25 VIN+ = 0 to 300mV RIN - INPUT IMPEDANCE - kohm IIN+ - INPUT CURRENT - µA 0.030 Figure 10. Nonlinearity vs. supply VDD2. Figure 11. Nonlinearity vs. temperature. -0.4 -0.2 0 0.2 VIN+ - INPUT VOLTAGE - V Figure 13. Input current vs. input voltage. 9 NL200 0.035 0.010 5.5 Figure 9. Nonlinearity vs. supply VDD1. 20 15 10 5 0 -5 -10 -15 -20 -25 -30 -0.6 0.040 0.015 0.015 0.20 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 -40 VDD1 = 5V 0.4 0.6 24 23 22 21 -40 -20 0 20 40 60 TA - TEMPERATURE - °C Figure 14. Input impedance vs. temperature. 80 100 120 64 64 61 58 SNDR 55 52 49 43 -20 0 20 40 60 TA - TEMPERATURE - °C 80 100 5 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 100 150 200 250 300 VIN+ - INPUT VOLTAGE - m Vpp 350 400 Figure 16. SNR, SNDR vs. input voltage. 180 150 120 90 60 30 0 -30 -60 -90 -120 -150 -180 100 PHASE - DEGREES NORMALIZED GAIN - dB 1,000 10,000 100,000 FREQUENCY - Hz 1,000,000 tPD90 tPD50 tR/F tPD10 tPD10, tPD50, tPD90: 200mV/µs step input; tR/F: step input -20 0 20 40 60 TA - TEMPERATURE - °C 1,000 10,000 FREQUENCY - Hz 100,000 1,000,000 Figure 18. Phase frequency response. IDD - SUPPLY CURRENT - mA PROPAGATION DELAY - µs 49 40 100 120 Figure 17. Gain frequency response. 80 100 Figure 19. Propagation delay, output rise/fall time vs. temperature. 10 52 43 VIN+ = 300mVpp 10 kHz sine wave Figure 15. SNR, SNDR vs. temperature. 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 -40 SNDR 55 46 46 40 -40 SNR 58 SNR, SNDR - dB SNR, SNDR - dB 61 SNR 120 15 14 13 12 11 10 9 8 7 6 5 -0.4 IDD1 (VDD1 = 5V) IDD2 (VDD2 = 5V) IDD2 (VDD2 = 3.3V) -0.3 -0.2 -0.1 0 0.1 0.2 VIN+ - INPUT VOLTAGE - V Figure 20. Supply current vs. input voltage. 0.3 0.4 Definitions Gain Gain is defined as the slope of the best-fit line of differential output voltage (VOUT+ – VOUT–) vs. differential input voltage (VIN+ – VIN–) over the nominal input range, with offset error adjusted out. Nonlinearity Nonlinearity is defined as half of the peak-to-peak output deviation from the best-fit gain line, expressed as a percentage of the full-scale differential output voltage. Input DC Common Mode Rejection Ratio, CMRRIN CMRRIN is defined as the ratio of the differential signal gain (signal applied differentially between pins VOUT+ and VOUT–) to the input side common-mode gain (input pins tied together and the signal applied to both inputs with respect to pin GND1), expressed in dB. PSR is the ratio of differential amplitude of the ripple outputs over power supply ripple voltage, referred to the input, expressed in dB. C1 0.1 µF R3 *** U1 78L05 IN OUT R5 10 VDD1 C2 0.1 µF 10.0 K VDD2 (+5 V) 1 8 2 7 C3 47 nF 3 U2 C4 0.1 µF +15 V 2.00 K R2 6 4 GND1 HV- Figure 21. Typical application circuit for motor phase current sensing. 5 ACPL-C79B/ ACPL-C79A/ ACPL-C790 C6 47 pF GND2 C8 0.1 µF GND2 – U3 + TL032A R1 2.00 K + – RSENSE *** 11 Power Supply Rejection, PSR C5 47 pF GATE DRIVE CIRCUIT *** CMTI is tested by applying an exponentially rising/falling voltage step on pin 4 (GND1) with respect to pin 5 (GND2). The rise time of the test waveform is set to approximately 50 ns. The amplitude of the step is adjusted until the differential output (VOUT+ – VOUT–) exhibits more than a 200 mV deviation from the average output voltage for more than 1μs. The ACPL-C79B/C79A/C790 will continue to function if more than 10 kV/μs common mode slopes are applied, as long as the breakdown voltage limitations are observed. POSITIVE FLOATING SUPPLY HV+ MOTOR Common Mode Transient Immunity, CMTI, also known as Common Mode Rejection C7 R4 0.1 µF 10.0 K -15 V GND2 GND2 VOUT Application Information Application Circuit The typical application circuit is shown in Figure 21. A floating power supply (which in many applications could be the same supply that is used to drive the high-side power transistor) is regulated to 5 V using a simple threeterminal voltage regulator (U1). The voltage from the current sensing resistor, or shunt (RSENSE), is applied to the input of the ACPL-C79B/C79A/C790 through an RC anti-aliasing filter (R5 and C3). And finally, the differential output of the isolation amplifier is converted to a groundreferenced single-ended output voltage with a simple differential amplifier circuit (U3 and associated components). Although the application circuit is relatively simple, a few recommendations should be followed to ensure optimal performance. Power Supplies and Bypassing As mentioned above, an inexpensive 78L05 three-terminal regulator can be used to reduce the gate-drive power supply voltage to 5 V. To help attenuate high frequency power supply noise or ripple, a resistor or inductor can be used in series with the input of the regulator to form a low-pass filter with the regulator’s input bypass capacitor. The power supply for the isolation amplifier is most often obtained from the same supply used to power the power transistor gate drive circuit. If a dedicated supply is required, in many cases it is possible to add an additional winding on an existing transformer. Otherwise, some sort of simple isolated supply can be used, such as a line powered transformer or a high-frequency DC-DC converter. As shown in Figure 21, 0.1 µF bypass capacitors (C2, C4) should be located as close as possible to the pins of the isolation amplifier. The bypass capacitors are required because of the high-speed digital nature of the signals inside the isolation amplifier. A 47 nF bypass capacitor (C3) is also recommended at the input pins due to the switched-capacitor nature of the input circuit. The input bypass capacitor also forms part of the anti-aliasing filter, which is recommended to prevent high-frequency noise from aliasing down to lower frequencies and interfering with the input signal. The input filter also performs an important reliability function – it reduces transient spikes from ESD events flowing through the current sensing resistor. 12 PC Board Layout The design of the printed circuit board (PCB) should follow good layout practices, such as keeping bypass capacitors close to the supply pins, keeping output signals away from input signals, the use of ground and power planes, etc. In addition, the layout of the PCB can also affect the isolation transient immunity (CMTI) of the ACPL-C79B/C79A/C790, due primarily to stray capacitive coupling between the input and the output circuits. To obtain optimal CMTI performance, the layout of the PC board should minimize any stray coupling by maintaining the maximum possible distance between the input and output sides of the circuit and ensuring that any ground or power plane on the PC board does not pass directly below or extend much wider than the body of the ACPL-C79B/C79A/C790. Figure 22 shows an example PCB layout. TO GND1 TO VDD1 TO VDD2 TO GND2 C4 C2 U2 TO RSENSE+ R5 VOUT+ VOUT– C3 TO RSENSE– Note: Drawing not to scale ACPL-C79B/C79A/C790 Figure 22. Example printed circuit board layout. Shunt Resistor Selection The current sensing resistor should have low resistance (to minimize power dissipation), low inductance (to minimize di/dt induced voltage spikes which could adversely affect operation), and reasonable tolerance (to maintain overall circuit accuracy). Choosing a particular value for the resistor is usually a compromise between minimizing power dissipation and maximizing accuracy. Smaller sense resistance decreases power dissipation, while larger sense resistance can improve circuit accuracy by utilizing the full input range of the ACPL-C79B/C79A/C790. The first step in selecting a sense resistor is determining how much current the resistor will be sensing. The graph in Figure 23 shows the RMS current in each phase of a threephase induction motor as a function of average motor output power (in horsepower, hp) and motor drive supply voltage. The maximum value of the sense resistor is determined by the current being measured and the maximum recommended input voltage of the isolation amplifier. The maximum sense resistance can be calculated by taking the maximum recommended input voltage and dividing by the peak current that the sense resistor should see during normal operation. For example, if a motor will have a maximum RMS current of 10 A and can experience up to 50% overloads during normal operation, then the peak current is 21.1 A (=10 x 1.414 x 1.5). Assuming a maximum input voltage of 200 mV, the maximum value of sense resistance in this case would be about 10 mΩ. The maximum average power dissipation in the sense resistor can also be easily calculated by multiplying the sense resistance times the square of the maximum RMS current, which is about 1 W in the previous example. If the power dissipation in the sense resistor is too high, the resistance can be decreased below the maximum value to decrease power dissipation. The minimum value of the sense resistor is limited by precision and accuracy requirements of the design. As the resistance value is reduced, the output voltage across the resistor is also reduced, which means that the offset and noise, which are fixed, become a larger percentage of the signal amplitude. The selected value of the sense resistor will fall somewhere between the minimum and maximum values, depending on the particular requirements of a specific design. When sensing currents large enough to cause significant heating of the sense resistor, the temperature coefficient (tempco) of the resistor can introduce nonlinearity due to the signal dependent temperature rise of the resistor. The effect increases as the resistor-to-ambient thermal resisMOTOR OUTPUT POWER - HORSEPOWER 40 440 V 380 V 220 V 120 V 35 30 25 20 15 10 5 0 0 5 15 10 20 25 MOTOR PHASE CURRENT - A (rms) 30 Figure 23. Motor output horsepower vs. motor phase current and supply voltage. 13 35 tance increases. This effect can be minimized by reducing the thermal resistance of the current sensing resistor or by using a resistor with a lower tempco. Lowering the thermal resistance can be accomplished by repositioning the current sensing resistor on the PC board, by using larger PC board traces to carry away more heat, or by using a heat sink. For a two-terminal current sensing resistor, as the value of resistance decreases, the resistance of the leads become a significant percentage of the total resistance. This has two primary effects on resistor accuracy. First, the effective resistance of the sense resistor can become dependent on factors such as how long the leads are, how they are bent, how far they are inserted into the board, and how far solder wicks up the leads during assembly (these issues will be discussed in more detail shortly). Second, the leads are typically made from a material, such as copper, which has a much higher tempco than the material from which the resistive element itself is made, resulting in a higher tempco overall. Both of these effects are eliminated when a four-terminal current sensing resistor is used. A four-terminal resistor has two additional terminals that are Kelvin connected directly across the resistive element itself; these two terminals are used to monitor the voltage across the resistive element while the other two terminals are used to carry the load current. Because of the Kelvin connection, any voltage drops across the leads carrying the load current should have no impact on the measured voltage. When laying out a PC board for the current sensing resistors, a couple of points should be kept in mind. The Kelvin connections to the resistor should be brought together under the body of the resistor and then run very close to each other to the input of the ACPL-C79B/C79A/ C790; this minimizes the loop area of the connection and reduces the possibility of stray magnetic fields from interfering with the measured signal. If the sense resistor is not located on the same PC board as the isolation amplifier circuit, a tightly twisted pair of wires can accomplish the same thing. Also, multiple layers of the PC board can be used to increase current carrying capacity. Numerous platedthrough vias should surround each non-Kelvin terminal of the sense resistor to help distribute the current between the layers of the PC board. The PC board should use 2 or 4 oz. copper for the layers, resulting in a current carrying capacity in excess of 20 A. Making the current carrying traces on the PC board fairly large can also improve the sense resistor’s power dissipation capability by acting as a heat sink. Liberal use of vias where the load current enters and exits the PC board is also recommended. Shunt Resistor Connections The typical method for connecting the ACPL-C79B/C79A/ C790 to the current sensing resistor is shown in Figure 21. VIN+ (pin 2) is connected to the positive terminal of the sense resistor, while VIN– (pin 3) is shorted to GND1 (pin 4), with the power-supply return path functioning as the sense line to the negative terminal of the current sense resistor. This allows a single pair of wires or PC board traces to connect the isolation amplifier circuit to the sense resistor. By referencing the input circuit to the negative side of the sense resistor, any load current induced noise transients on the resistor are seen as a common-mode signal and will not interfere with the current-sense signal. This is important because the large load currents flowing through the motor drive, along with the parasitic inductances inherent in the wiring of the circuit, can generate both noise spikes and offsets that are relatively large compared to the small voltages that are being measured across the current sensing resistor. If the same power supply is used both for the gate drive circuit and for the current sensing circuit, it is very important that the connection from GND1 of the ACPL-C79B/C79A/ C790 to the sense resistor be the only return path for supply current to the gate drive power supply in order to eliminate potential ground loop problems. The only direct connection between the ACPL-C79B/C79A/C790 circuit and the gate drive circuit should be the positive power supply line. Differential Input Connection The differential analog inputs of the ACPL-C79B/C79A/ C790 are implemented with a fully-differential, switchedcapacitor circuit. In the typical application circuit (Figure 21), the isolation amplifier is connected in a single-ended input mode. Given the fully differential input structure, a differential input connection method (balanced input mode as shown in Figure 24) is recommended to achieve better performance. The input currents created by the switching actions on both of the pins are balanced on the filter resistors and cancelled out each other. Any noise induced on one pin will be coupled to the other pin by the capacitor C and creates only common mode noise which is rejected by the device. Typical value for Ra and Rb is 10 Ω and 22 nF for C. For product information and a complete list of distributors, please go to our web site: 5V +Input –Input VDD1 Ra Rb VIN+ C VIN– ACPL-C79B/ ACPL-C79A/ ACPL-C790 GND1 Figure 24. Simplified differential input connection diagram. Output Side The op-amp used in the external post-amplifier circuit should be of sufficiently high precision so that it does not contribute a significant amount of offset or offset drift relative to the contribution from the isolation amplifier. Generally, op-amps with bipolar input stages exhibit better offset performance than op-amps with JFET or MOSFET input stages. In addition, the op-amp should also have enough bandwidth and slew rate so that it does not adversely affect the response speed of the overall circuit. The postamplifier circuit includes a pair of capacitors (C5 and C6) that form a single-pole low-pass filter; these capacitors allow the bandwidth of the post-amp to be adjusted independently of the gain and are useful for reducing the output noise from the isolation amplifier. The gain-setting resistors in the post-amp should have a tolerance of 1% or better to ensure adequate CMRR and adequate gain tolerance for the overall circuit. Resistor networks can be used that have much better ratio tolerances than can be achieved using discrete resistors. A resistor network also reduces the total number of compo­ nents for the circuit as well as the required board space. Voltage Sensing The ACPL-C79B/C79A/C790 can also be used to isolate signals with amplitudes larger than its recommended input range with the use of a resistive voltage divider at its input. The only restrictions are that the impedance of the divider be relatively small (less than 1 kΩ) so that the input resistance (22 kΩ) and input bias current (0.1 µA) do not affect the accuracy of the measurement. An input bypass capacitor is still required, although the 10 Ω series damping resistor is not (the resistance of the voltage divider provides the same function). The low-pass filter formed by the divider resistance and the input bypass capacitor may limit the achievable bandwidth. www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2014 Avago Technologies. All rights reserved. AV02-2460EN - August 28, 2014