ACPL-K33T-000E

ACPL-K33T Automotive 2.5 A Peak High Output Current SiC MOSFET and IGBT Gate Drive Optocoupler with Rail-to-Rail Output Voltage in Stretched SO-8 Data Sheet Description Features Avago Technologies' 2.5 Amp Automotive R2Coupler® Gate Drive Optocoupler contains an AlGaAs LED, which is optically coupled to an integrated circuit with a power output stage. The ACPL-K33T features fast propagation delay and tight timing skew, is ideally designed for driving SiC MOSFET and IGBTs used in AC-DC and DC-DC converters. The high operating voltage range of the output stage provides the drive voltages required by gate-controlled devices. The voltage and high peak output current supplied by this optocoupler make it ideally suited for direct driving SiC MOSFET and IGBTs at high frequency for high efficiency conversion.  Avago R2Coupler isolation products provide reinforced insulation and reliability that delivers safe signal isolation critical in automotive and high-temperature industrial applications. CAUTION           It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.  Qualified to AEC-Q100 Grade 1 Test Guidelines Automotive temperature range: -40 °C to +125 °C Peak output current: 2.0 A min. Rail-to-rail output voltage Propagation delay: 120 ns max. Dead time distortion: +50 ns/–40 ns LED input threshold current hysteresis Common Mode Rejection (CMR): 50 kV/μs min. at VCM = 1500 V Low supply current allow bootstrap half-bridge topology: ICC = 4.2 mA max. Under Voltage Lock-Out (UVLO) protection with hysteresis for SiC MOSFET and IGBT Wide operating VCC range: 15 V to 30 V Safety Approvals: — UL Recognized 5000 VRMS for 1 min — CSA — IEC/EN/DIN EN 60747-5-5 VIORM = 1140 Vpeak Applications     Avago Technologies -1- Hybrid Power Train DC/DC Converter EV/PHEV Charger Automotive Isolated IGBT Gate Drive AC and Brushless DC Motor Drives ACPL-K33T Data Sheet Functional Diagram Functional Diagram Figure 1 ACPL-K33T Functional Diagram 8 VCC ANODE 1 7 VOUT NC 2 6 NC CATHODE 3 NC 4 NOTE 5 VEE SHIELD Minimum 1 μF bypass capacitor must be connected between pins VCC and VEE. Truth Table VCC – VEE LED VOUT OFF 0 – 30 V LOW ON < VUVLO- LOW ON > VUVLO+ HIGH Ordering Information Part Number ACPL-K33T Option (RoHS Compliant) -000E Surface Mount Package Stretched SO-8 Tape and Reel UL 5000 Vrms/1 Minute rating X X -060E X X -500E X X X -560E X X X IEC/EN/DIN EN 60747-5-5 Quantity 80 per tube X 80 per tube 1000 per reel X 1000 per reel To order, choose a part number from the Part Number column and combine it with the desired option from the Option column to form an order entry. Example 1: ACPL-K33T-560E to order product of SSO-8 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval and is RoHS compliant. Option data sheets are available. Contact your Avago sales representative or authorized distributor for information. Avago Technologies -2- ACPL-K33T Data Sheet Package Outline Drawings (Stretched SO-8) Package Outline Drawings (Stretched SO-8) RECOMMENDED LAND PATTERN 5.850 ± 0.254 (0.230 ± 0.010) 8 7 6 PART NUMBER DATE CODE 5 KXXT YWW EE RoHS-COMPLIANCE INDICATOR 1 2 12.650 (0.498) 6.807 ± 0.127 (0.268 ± 0.005) 1.905 (0.075) 3 4 EXTENDED DATE CODE FOR LOT TRACKING 0.64 (0.025) 7° 1.590 ± 0.127 (0.063 ± 0.005) 45° 0.450 (0.018) 3.180 ± 0.127 (0.125 ± 0.005) 0.750 ± 0.250 (0.0295 ± 0.010) 11.50 ± 0.250 (0.453 ± 0.010) 0.200 ± 0.100 (0.008 ± 0.004) 0.381 ± 0.127 (0.015 ± 0.005) 1.270 (0.050) BSG 0.254 ± 0.100 (0.010 ± 0.004) Dimensions in millimeters (inches). Notes: 1. Lead coplanarity = 0.1 mm (0.004 inches). 2. Floating lead protrusion = 0.25 mm (10 mils) max. Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). NOTE Non-halide flux should be used. Regulatory Information The ACPL-K33T is approved by the following organizations: UL UL 1577, component recognition program up to VISO = 5 kVRMS CSA CSA Component Acceptance Notice #5 IEC/EN/DIN EN 60747-5-5 IEC/EN/DIN EN 60747-5-5 Avago Technologies -3- ACPL-K33T Data Sheet IEC/EN/DIN EN 60747-5-5 Insulation Related Characteristic (Option 060 and 560 only) IEC/EN/DIN EN 60747-5-5 Insulation Related Characteristic (Option 060 and 560 only) Description Symbol Option 060 and 560 Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage < 600 VRMS for rated mains voltage < 1000 VRMS I - IV I - III Climatic Classificationa 40/125/21 Pollution Degree (DIN VDE 0110/1.89) 2 Units Maximum Working Insulation Voltage VIORM 1140 Vpeak Input to Output Test Voltage, Method b VIORM × 1.875=VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC VPR 2137 Vpeak Input to Output Test Voltage, Method a VIORM × 1.6 = VPR, Type and Sample Test with tm=10 sec, Partial discharge < 5 pC VPR 1824 Vpeak Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) VIOTM 8000 Vpeak Safety-limiting values – maximum values allowed in the event of a failure Case Temperature Input Current Output Power Ts IS, INPut PS,OUTPUT 175 230 600 °C mA mW Insulation Resistance at Ts, VIO=500 V Rs > 109  a. Climatic classification denotes //. Insulation and Safety-Related Specifications Parameter Symbol ACPL-K33T Units Conditions Minimum External Air Gap (Clearance) L(101) 8 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (Creepage) L(102) 8 mm Measured from input terminals to output terminals, shortest distance path along body. 0.08 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. 175 V DIN IEC 112/VDE 0303 Part 1 Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group (DIN VDE0109) CTI IIIa Avago Technologies -4- Material Group (DIN VDE 0109) ACPL-K33T Data Sheet Absolute Maximum Ratings Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature TS –55 150 °C Operating Temperature TA –40 125 °C IC Junction Temperaturea TJ 150 °C Average Input Current IF(AVG) 20 mA Peak Input Current (50% duty cycle, < 1 ms pulse width) IF(PEAK) 40 mA Peak Transient Input Current ( 5 V 7 Threshold Input Voltage High to Low VFHL 0.8 Input Forward Voltage VF 1.25 IF = 10 mA 7 High Level Peak Output Current IOH Low Level Peak Output Current IOL High Output Transistor RDS(ON)a RDS,OH 2.2 Low Output Transistor RDS(ON)a RDS,OL 1.0 High Level Output Voltageb, c VOH Low Level Output Voltage VOL 0.1 High Level Supply Current ICCH Low Level Supply Current 2.0 -2.0 Units 4 Vcc – 0.45 Vcc –.2 V 1.5 Temperature Coefficient of Input Forward VF/TA Voltage 1.85 -1.5 mV/ °C Input Reverse Breakdown Voltage BVR Input Capacitance CIN UVLO Threshold VUVLO+ 12.1 13 13.9 VUVLO- 11.1 12 12.9 UVLOHYS 0.5 1.0 UVLO Hysteresis V 6 90 V IR = 100 μA pF f = 1 MHz, VF = 0 V V VO > 5 V IF = 10 mA V a. Output is source at –2.0 A or 2.0 A with a maximum pulse width of 10 μs. b. In this test, VOH is measured with a DC load current. When driving capacitive loads VOH will approach VCC as IOH approaches zero amperes. c. Maximum pulse width = 1 ms. Avago Technologies -6- 8 8 ACPL-K33T Data Sheet Switching Specifications (AC) Switching Specifications (AC) Unless otherwise noted, all Minimum/Maximum specifications are at Recommended Operating Conditions. All typical values are at TA = 25 °C, VCC – VEE = 15 V, VEE = Ground. Parameter Symbol Min. Typ. Max. Units Propagation Delay Time to High Output Levela tPLH 30 65 120 ns Propagation Delay Time to Low Output Level tPHL 30 65 120 ns Pulse Width Distortion (tPHL – tPLH)b PWD –40 0 40 ns Dead Time Distortion Caused by Any DTD Two Parts (tPLH – tPHL)c –40 50 ns Rise Time tR 15 ns Fall Time tF 15 ns Output High Level Common Mode Transient Immunityd , e |CMH| 50 >75 kV/μs Output Low Level Common Mode Transient Immunityd , f |CML| 50 >75 kV/μs Test Conditions Fig. VCC = 15 V RG = 7.5  CL = 10 nF f = 20 kH Duty Cycle = 50% Vin = 4.5 V to 5.5 V Rin = 350  9,12,14 VCC = 15 V CL = 1 nF f= 20 kHz Duty Cycle = 50% Vin = 4.5 V to 5.5 V Rin = 350  13,14 10,12,14 11 15 TA = 25 °C VCC = 30 V, VCM=1500 V, with split resistors a. This load condition approximates the gate load of a 600 V/50 A power devices. b. Pulse Width Distortion (PWD) is defined as tPHL – tPLH for any given device. c. Dead Time Distortion (DTD) is defined as tPLH – tPHL between any two parts under the same test condition. A negative DTD reduces original system dead time; while a positive DTD increases original system dead time. d. Pin 2 and Pin 4 need to be connected to LED common. e. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to ensure that the output will remain in the high state, (i.e., VO > 15 V). f. Common mode transient immunity in a low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to ensure that the output will remain in a low state (i.e., VO < 1.0 V). Package Characteristics Unless otherwise noted, all Minimum/Maximum specifications are at Recommended Operating Conditions. All typical values are at TA = 25 °C.The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an Parameter Symbol Min. VISO 5000 Input-Output Resistancec RI-O 109 Input-Output Capacitance CI-O Input-Output Momentary Withstand Voltagea, Typ. Max. Units Test Conditions VRMS RH < 50%, t = 1 min TA = 25 °C 1014  VI-O = 500 VDC 0.6 pF f =1 MHz b, c a. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating, refer to your equipment level safety specification or Avago Technologies Application Note 1074 “Optocoupler Input-Output Endurance Voltage.” b. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage≥ 6000 VRMS for 1 second. c. Device considered a two-terminal device: pins 1, 2, 3 and 4 shorted together and pins 5, 6, 7 and 8 shorted together. Avago Technologies -7- ACPL-K33T Data Sheet Typical Performance Plots Po - OUTPUT IC POWER DISSIPATION - mW Figure 2 Output IC Power Dissipation Derating Chart 600 PO 500 400 300 200 100 0 0 25 50 75 100 125 Ta- AMBIENT TEMPERATURE - °C 150 175 Typical Performance Plots Figure 3 IOH vs. (VCC –VOH) Figure 4 IOL vs. VOL 125 °C 25 °C –40 °C -0.5 -1 IOL - OUTPUT LOW CURRENT - A IOH - OUTPUT HIGH CURRENT - A 0 -1.5 -2 -2.5 -3 -3.5 -4 -4.5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (VCC - V0H) - HIGH OUTPUT VOLTAGE DROP - V Figure 5 ICCH vs. Temperature 6 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 V0L - OUTPUT LOW VOLTAGE - V 3.4 ICCL - LOW LEVEL SUPPLY CURRENT - mA ICCH - HIGH LEVEL SUPPLY CURRENT - mA 1 Figure 6 ICCL vs. Temperature 3.4 3.2 3 2.8 2.6 2.4 VCC=15 V VCC=20 V VCC=30 V 2.2 2 -40 125 °C 25 °C –40 °C -20 0 20 40 60 80 TA -TEMPERATURE - °C 100 120 140 Avago Technologies -8- 3.2 3 2.8 2.6 2.4 VCC=15 V VCC=20 V VCC=30 V 2.2 2 -40 -20 0 20 40 60 80 TA -TEMPERATURE - °C 100 120 140 ACPL-K33T Data Sheet Typical Performance Plots Figure 8 IF vs. VF 1.8 14 1.7 12 IF - INPUT CURRENT - mA VF - INPUT FORWARD VOLTAGE - V Figure 7 VF vs. Temperature 1.6 1.5 1.4 1.3 1.2 1.1 1 8 6 4 2 -20 0 20 40 60 80 TA - TEMPERATURE - °C 100 120 0 140 Figure 9 tPLH vs. Temperature 85 85 80 80 75 70 65 60 Vin=4.5 V Vin=5 V Vin=5.5 V 55 50 -40 -20 0 20 40 PWD - PULSE WIDTH DISTORTION - ns 1.7 1.8 60 80 100 120 140 65 60 50 -40 15 10 5 0 -5 Vin=4.5 V Vin=5 V Vin=5.5 V -10 -15 20 40 60 80 TA - TEMPERATURE - °C 100 120 Vin=4.5 V Vin=5 V Vin=5.5 V 55 20 0 1.2 1.3 1.4 1.5 1.6 VF - INPUT FORWARD VOLTAGE - V 70 Figure 11 PWD vs. Temperature -20 1.1 75 TA - TEMPERATURE - °C -20 -40 1 Figure 10 tPHL vs. Temperature tPHL - PROPAGATION DELAY - ns tPLH - PROPAGATION DELAY - ns 10 IF=10mA -40 125 °C 25 °C –40 °C 140 Avago Technologies -9- -20 0 20 40 60 80 TA - TEMPERATURE - °C 100 120 140 ACPL-K33T Data Sheet Typical Performance Plots Figure 12 tPLH and tPHL Test Circuit R in=350 : + _ Vin =4.5 to 5.5V 50% Duty Cycle 20 kHz 8 1 2 7 1 PF VOUT _+ VCC=15 V 6 3 RG=7.5 CL=1 nF 4 SHIELD 5 Figure 13 tr and tf Test Circuit R in=350 : + _ Vin =4.5 to 5.5V 50% Duty Cycle 20 kHz 8 1 2 7 1 PF VOUT _+ VCC=15 V 3 6 CL=1 nF 4 SHIELD 5 Figure 14 tPLH, tPHL, tr, and tf Reference Waveforms Vin tr tf 90% 50% VOUT 10% tPLH tPHL Avago Technologies - 10 - ACPL-K33T Data Sheet Typical High-Speed SiC MOSFET/IGBT Gate Drive Circuit Figure 15 CMR Test Circuit 5V + _ Rin1 210 Ω A 0.1 PF B 8 1 2 1 PF VOUT 7 _+ VCC=20 V 3 6 Rin2 140 : 4 5 + _ SHIELD Switch at A: CMH test VCM=1500 V Switch at B: CML test Typical High-Speed SiC MOSFET/IGBT Gate Drive Circuit Figure 16 Typical High-Speed SiC MOSFET/IGBT Gate Drive Circuit +5 V VDD 0.1 μF +HVDC U5 μP PHA Rin1 Rin2 PHA U6 U1 U3 AN VCC VOUT NC NC CA NC V EE ACPL-K33T +12 V LED(U2) Q1 AN VCC VOUT NC NC CA NC V EE ACPL-K33T Rin3 Rin4 AN NC CA NC 10 μF 7.5 Ω Q3 15 V D2 D1 U4 U2 PHA LED(U1) 7.5 Ω 10 μF Anti-cross conduction drive logic PHA 10 μF VCC VOUT NC V EE 10 μF 7.5 Ω Q2 AN NC CA NC VCC VOUT NC V EE ACPL-K33T ACPL-K33T 10 μF 7.5 Ω Q4 –HVDC Anti-Cross Conduction Drive One of the many benefits of using ACPL-K33T is the ease of implementing anti-cross conduction drive between the high side and the low side gate drivers to prevent a shoot-through event. This safety interlock drive can be realized by interlocking the output of buffer U5 and U6 to both the high and the low side gate drivers, as shown in Figure 16. Due to the difference in propagation delay between optocouplers, however, a certain amount of dead time has to be added to ensure sufficient dead time at the MOSFET gate. For more details, see the “Dead Time and Propagation Delay” section. Avago Technologies - 11 - ACPL-K33T Data Sheet Recommended LED Drive Circuits Recommended LED Drive Circuits There will be common mode noise whenever there is a difference in the ground level of the optocoupler’s input control circuitry and that of the output control circuitry. Figure 17 and Figure 18 show the recommended LED drive circuits that use logic gate (CMOS buffer) for high common mode rejection (CMR) performance of the optocoupler gate driver. Split limiting resistors are used to balance the impedance at both anode and cathode of the input LED for high common mode noise rejection. The output impedance of the CMOS buffer (shown as RO in Figure 17 and Figure 18) has to be included in the calculation for LED drive current. On the other hand, Figure 19 and Figure 20 show the recommended LED drive circuits that use a single transistor. During the LED off state, M1 and Q1 in Figure 19 and Figure 20 will shunt current, which results in greater power consumption. It is not recommended to have open drain and open collector drive circuits, as shown in Figure 21 and Figure 22. This is because during the off state of the MOSFET/transistor, the cathode of the input LED sees high impedance and becomes sensitive to noise. Drive Power If a CMOS buffer is used to drive the LED, it is recommended that you connect the CMOS buffer at the LED cathode. This is because the sinking capability of the NMOS is usually greater than the driving capability of the PMOS in a CMOS buffer. Drive Logic The designer can configure LED drive circuits for non-inverting and inverting logic as recommended in Figure 17 and Figure 18. For the inverting and non-inverting logic to work, the external power supply VDD1 must be connected to the CMOS buffer. If the VDD1 supply is lost, the LED will be permanently off and output will be low. Bypass and Reservoir Capacitors Supply bypass capacitors are necessary at the input buffer and ACPL-K33T output supply pin. A ceramic capacitor with the value of 0.1 μF is recommended at the input buffer to provide high frequency bypass, which also helps to improve CMR performance. At the output supply pin (VCC – VEE), it is recommended to use a 10 μF, low ESR and low ESL capacitor as a charge reservoir to supply instant driving current to IGBT at VOUT during switching. Avago Technologies - 12 - ACPL-K33T Data Sheet Bypass and Reservoir Capacitors Figure 17 Recommended Non-Inverting Logic Gate Drive Circuit Figure 18 Recommended Inverting Logic Gate Drive Circuit ISOLATION V DD1 0.1 μF R in1 V DD1 ISOLATION VDD1 0.1 μF V CC Rin1 AN VDD1 AN VCC V OUT V OUT R in2 10 μF CA 10 μF CA Ro Ro V EE Rin2 V EE ACPL-K33T ACPL-K33T VDD1= 5 V ± 10% Ratio Rin1: (Rin2+Ro) = 1.5:1 Recommended Ro+Rin1+Rin2 = 350  VDD1= 5 V ± 10% Ratio Rin1: (Rin2+Ro) = 1.5:1 Recommended Ro+Rin1+Rin2 = 350  Figure 19 Recommended Single Transistor Drive Circuit Figure 20 Recommended Single Transistor Drive Circuit ISOLATION ISOLATION V DD1 V DD1 0.1 μF 0.1 μF V CC Rin/2 V CC Rin/2 AN AN V OUT M1 10 μF CA 10 μF CA V EE Rin /2 V OUT Q1 V EE Rin /2 ACPL-K33T ACPL-K33T VDD1= 5 V ± 10% Ratio Rin1: Rin2 = 1.5:1 Recommended Rin1+Rin2 = 350  VDD1= 5 V ± 10% Ratio Rin1: Rin2 = 1.5:1 Recommended Rin1+Rin2 = 350  Figure 21 Not Recommended – Open Drain/Open Collector Drive Circuit Figure 22 Not Recommended – Open Drain/Open Collector Drive Circuit R in ED 10 μF CA V EE Not recommended. V OUT 10 μF CA V EE M1 ACPL-K33T NOTE ED RE CO M M V OUT V CC NO T R in 0.1 μF AN NO T RE CO M M AN V CC EN D 0.1 μF ISOLATION V DD1 EN D ISOLATION V DD1 ACPL-K33T NOTE Avago Technologies - 13 - Not recommended. ACPL-K33T Data Sheet Initial Power Up and UVLO Operation Initial Power Up and UVLO Operation Insufficient gate voltage to IGBT can increase IGBT turn-on resistance, resulting in a large power loss and damage to IGBT due to high heat dissipation. ACPL-K33T constantly monitors the output power supply. During initial power up, the ACPL-K33T requires a maximum of 50 μs initial startup time for the internal bias and circuitry to get ready. The gate driver output (VOUT ) is held at off state during initial startup time. Thereafter, when the output power supply is lower than the under voltage lockout (VUVLO-) threshold, the gate driver output will shut off to protect IGBT from low voltage bias. When the output power supply is more than the VUVLO+ threshold, VOUT is released from low state and it follows the input LED drive signal, as shown in Figure 23. Figure 23 ACPL-K33T Initial Power-Up and UVLO Operation VUVLO+ VCC VUVLO– VUVLO+ Vin(LED) Initial startup time VOUT Dead Time Distortion and Propagation Delay Dead time is the period of time during which both high side and low side power transistors (shown as Q1 and Q2 in Figure 16) are off. Originally, the system is required to design in some amount of dead time to compensate for the turn-off delay needed for the MOSFET to discharge the input capacitance after the gate is switched off. In this application note, this amount of dead time is called system original dead time. When an optocoupler is used, the designer has to consider the effect of the optocoupler’s dead time distortion (DTD) toward system original dead time. The optocoupler’s negative DTD decreases system original dead time; on the other hand, the optocoupler’s positive DTD increases system original dead time. Therefore, the designer must add extra dead time to system original dead time to compensate for the optocoupler’s negative DTD. Figure 24 and Figure 25 illustrate the effect of the optocoupler’s DTD to system original dead time. Dead Time and Propagation Delay Waveforms Figure 24 Negative DTD Reduces Original DT Figure 25 Positive DTD Increases Original DT Original DT Original DT Vin(LED1) Vin(LED1) Vin(LED2) Vin(LED2) tPLH VOUT2 tPLH VOUT1 VOUT1 VOUT2 tPHL tPHL DT after optocoupler Avago Technologies - 14 - DT after optocoupler ACPL-K33T Data Sheet Programmable Dead Time Here is an example of total dead time calculation for a typical optocoupler drive circuit for MOSFET. Total dead time required = System original dead time + |optocoupler’s negative DTD| = System original dead time + |40 ns| where system original dead time = MOSFET turn-off delay NOTE The propagation delays used to calculate dead time distortion (DTD) are taken at equal temperatures and test conditions as the optocouplers used under consideration are typically mounted in close proximity to each other and are switching same type of MOSFETs. Programmable Dead Time Programmable dead time can be introduced to an optocoupler gate driver by adding an external capacitor (CDT) across the input LED (Anode and Cathode) as shown in Figure 26. This simple circuitry offers you the flexibility to optimize gate drive switching timing for various MOSFETs and applications through hardware configuration. The value of the external capacitor (CDT) can be calculated based on the minimum dead time requirement for the system, as shown in the following equation. The added dead time will delay the turn-on timing of the gate signal, as shown in Figure 27. DT(min) CDT(min) = – VF(min) – Vin(off) Rin(min) ln 1 – Vin(on) – Vin(off) where DT: Total dead time required for a system, inclusive of original dead time and the optocoupler’s negative DTD Rin: Total input LED current-limiting resistor CDT: External Dead time programming capacitor VF: Input LED forward voltage Vin: Input PWM voltage Figure 26 Add CDT for Dead Time Programming Rin 5V 0V 8 Vin 2 7 VAN 3 6 1 Vin VAN Figure 27 Timing Diagram with and without CDT IF CDT DT IF DT t PLH 4 SHIELD 5 Waveform with CDT Waveform without CDT VOUT Avago Technologies - 15 - tPHL+DT t PHL ACPL-K33T Data Sheet Thermal Resistance Model for ACPL-K33T Thermal Resistance Model for ACPL-K33T The diagram for measurement is shown in Figure 28. Here, one die is first heated and the temperatures of all the dice are recorded after thermal equilibrium is reached. Then, the second die is heated and all the dice temperatures are recorded. With the known ambient temperature, the die junction temperature and power dissipation, the thermal resistance can be calculated. The thermal resistance calculation can be cast in matrix form. This yields a 2 by 2 matrix for our case of two heat sources. Figure 28 Diagram of ACPL-K33T for Measurement 1 2 3 8 Die1: LED 7 Die 2: Detector 6 4 R11 R21 5 R12 R22 ΔT1 P1 • P2 = ΔT2 R11: Thermal Resistance of Die1 due to heating of Die1 (°C/W) R12: Thermal Resistance of Die1 due to heating of Die2 (°C/W) R21: Thermal Resistance of Die2 due to heating of Die1 (°C/W) R22: Thermal Resistance of Die2 due to heating of Die2 (°C/W) P1: Power dissipation of Die1 (W) P2: Power dissipation of Die2 (W) T1: Junction temperature of Die1 due to heat from all dice (°C) T2: Junction temperature of Die2 due to heat from all dice (°C) Ta: Ambient temperature (°C) T1: Temperature difference between Die1 junction and ambient (°C) T2: Temperature deference between Die2 junction and ambient (°C) T1 = (R11 × P1 + R12 × P2) + Ta ------------------(1) T2 = (R21 × P1 + R22 × P2) + Ta ------------------(2) Avago Technologies - 16 - ACPL-K33T Data Sheet Thermal Resistance Model for ACPL-K33T Measurement is done on both low and high conductivity boards as shown in the following table. Layout Measurement Data Low conductivity board per JEDEC 51-3: R11 = 191 °C/W R12 = R21 = 68.5 °C/Wx 22 = 77 °C/W High conductivity board per JEDEC 51-7: R11 = 155 °C/W R12 = R21 = 64 °C/W R22=41 °C/W 76.2 mm 76.2 mm NOTE These thermal resistances R11, R12, R21 and R22 can be improved by increasing the ground plane/copper area. Application and environment design for ACPL-K33T needs to ensure that the junction temperature of the internal IC and LED within the gate drive optocoupler do not exceed 150 °C. Use equation (1) and equation (2) to estimate the junction temperatures. For example: Calculation of LED and output IC power dissipation: LED power dissipation, PE = IF(LED) (Recommended Max) × VF(LED) (at 125 °C) × Duty Cycle = 13 mA × 1.25 V × 50% = 8.125 mW Output IC power dissipation, PO = VCC (Recommended Max) × ICC(Max) + PHS + PLS = 30 V × 4.2 mA + 60 mW + 34.3 mW = 220.3 mW where PHS = High side switching power dissipation = (VCC × QG × fPWM) × RDS,OH(MAX)/(RDS,OH(MAX) + RGH)/2 = (30 V × 80 nC × 200 kHz) × 4 /(4 +12 )/2 = 60 mW PLS = Low side switching power dissipation = (VCC × QG × fPWM) × RDS,OL(MAX)/(RDS,OL(MAX) + RGL)/2 = (30 V × 80 nC × 200 kHz) × 2 /(2 +12 )/2 = 34.3 mW QG = Gate charge at supply voltage fPWM = LED switching frequency RGH = Gate charging resistance RGL = Gate discharging resistance Avago Technologies - 17 - Calculation of LED junction temperature and output IC junction temperature at Ta=125 °C based on a high conductivity board thermal resistance model: LED junction temperature, T1 = (R11 × PE + R12 × PO) + Ta = (155 °C/W × 8.125 mW + 64 °C/W × 220.3 mW) + 125 °C = 140 °C < TJ(absolute max) of 150 °C Output IC junction temperature, T2 = (R21 × PE + R22 × PO) + Ta = (64 °C/W × 8.125 mW + 41 °C/W × 220.3 mW) + 125 °C = 135 °C < TJ(absolute max) of 150 °C For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago Technologies, the A logo, and R2Coupler are trademarks of Avago Technologies in the United States and other countries. All other brand and product names may be trademarks of their respective companies. Data subject to change. Copyright © 2014–2016 Avago Technologies. All Rights Reserved. AV02-4575EN – March 31, 2016