ACPL-K44T-000E

ACPL-K43T, ACPL-K44T Automotive R2Coupler® Wide Operating Temperature 1 MBd Digital Optocoupler in a Stretched 8-Pin Surface Mount Plastic Package Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features The ACPL-K43T is a single channel, high temperature, high CMR, high speed digital optocoupler in an eight lead miniature footprint specifically used in the automotive applications. The ACPL-K44T is a dual channel equivalent of the ACPL-K43T. Both products are available in the stretched SO-8 package outline, designed to be compatible with standard surface mount processes.  High Temperature and Reliability low speed digital interface for Automotive Application This digital optocoupler uses an insulating layer between the light emitting diode and an integrated photo detector to provide electrical insulation between input and output. Separate connections for the photodiode bias and output transistor collector increase the speed up to a hundred times over that of a conventional photo-transistor coupler by reducing the base-collector capacitance. Avago R2Coupler® isolation products provide with reinforced insulation and reliability that delivers safe signal isolation critical in automotive and high temperature industrial applications.  Ultra low drive for status feedback at IF = 0.8 mA or 1.5 mA  30 kV/s (Typ) High Common-Mode Rejection at VCM = 1500 V  Compact, Auto-Insertable Stretched SO8 Packages  Qualified to AEC Q100 Grade 1 Test Guidelines  Wide Operating Temperature Range: –40°C to +125°C  High Speed: 1 MBd  Low Propagation Delay: 1 s max. at IF = 10 mA  Worldwide Safety Approval: – UL 1577 approval, 5 kVRMS/1 min. – CSA Approval – IEC/EN/DIN EN 60747-5-5 Applications Functional Diagram ACPL-K43T  Automotive IPM Driver for DC-DC converters and motor inverters ACPL-K44T ANODE 1 8 VCC ANODE1 1 8 VCC  Status Feedback and Wake-Up Signal Isolation CATHODE 2 7 VO CATHODE1 2 7 VO1  CANBus and SPI Communications Interface NC 3 6 NC CATHODE2 3 6 VO2  High Temperature Digital/Analog Signal Isolation NC 4 5 GND ANODE2 4 5 GND Truth Table LED Vo ON LOW OFF HIGH Note: The connection of a 0.1 F bypass capacitor between pins 5 and 8 is recommended. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Ordering Information Specify part number followed by option number (if desired). Part number Option (RoHS Compliant) ACPL-K43T -000E -060E Surface Mount Package Stretched SO-8 -500E -560E ACPL-K44T -000E -060E Stretched SO-8 Tape & Reel UL 5000 Vrms / 1 Minute rating X X X X X X X X IEC/EN/DIN EN 60747-5-5 80 per tube X 80 per tube X 1000 per reel X X X X X -500E X X X -560E X X X Quantity X 1000 per reel 80 per tube X 80 per tube 1000 per reel X 1000 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: ACPL-K43T-560E to order product of SSO-8 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval in RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Schematic ACPL-K43T ACPL-K44T ICC + 8 VCC IF ICC 1 IF1 + 8 VF1 IO1 – 2 ANODE 1 VF IO 7 VO – CATHODE 3 3 – 7 IO2 6 VO2 + 5 GND 4 5 USE OF 0.1 PF BYPASS CAPACITOR CONNECTED BETWEEN PINS 5 AND 8 IS RECOMMENDED. 2 VO1 IF2 VF2 SHIELD VCC GND Package Outline Dimensions (Stretched SO8) RECOMMENDED LAND PATTERN 5.850 ± 0.254 (0.230 ± 0.010) PART NUMBER DATE CODE 8 7 6 5 KXXT YWW EE RoHS-COMPLIANCE INDICATOR 1 2 12.650 (0.498) 6.807 ± 0.127 (0.268 ± 0.005) 1.905 (0.075) 3 4 EXTENDED DATECODE FOR LOT TRACKING 0.64 (0.025) 7° 1.590 ± 0.127 (0.063 ± 0.005) 45° 0.450 (0.018) 3.180 ± 0.127 (0.125 ± 0.005) 0.200 ± 0.100 (0.008 ± 0.004) 0.381 ± 0.127 (0.015 ± 0.005) 1.270 (0.050) BSG 0.750 ± 0.250 (0.0295 ± 0.010) 11.50 ± 0.250 (0.453 ± 0.010) 0.254 ± 0.100 (0.010 ± 0.004) Dimensions in millimeters and (inches). Note: Lead coplanarity = 0.1 mm (0.004 inches). Floating lead protrusion = 0.25mm (10mils) max. Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Note: Non-halide flux should be used. Regulatory Information The ACPL-K43T and ACPL-K44T are approved by the following organizations: UL UL 1577, component recognition program up to VISO = 5 kVRMS. CSA CSA Component Acceptance Notice #5. IEC/EN/DIN EN 60747-5-5 IEC 60747-5-5 EN 60747-5-5 DIN EN 60747-5-5 3 Insulation and Safety Related Specifications Parameter Symbol ACPL-K43T ACPL-K44T Units Conditions Minimum External Air Gap (Clearance) L(101) 8 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (Creepage) L(102) 8 mm Measured from input terminals to output terminals, shortest distance path along body. 0.08 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. 175 V DIN IEC 112/VDE 0303 Part 1 Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) CTI Isolation Group (DIN VDE0109) IIIa Material Group (DIN VDE 0109) IEC/EN/DIN EN 60747-5-5 Insulation Related Characteristic (Option 060E and 560E) Description Symbol Characteristic Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤ 150 Vrms for rated mains voltage ≤ 300 Vrms for rated mains voltage ≤ 450 Vrms for rated mains voltage ≤ 600 Vrms for rated mains voltage ≤ 1000 Vrms I – IV I – IV I – IV I – IV I – III Climatic Classification 55/100/21 Pollution Degree (DIN VDE 0110/1.89) 2 Units Maximum Working Insulation Voltage VIORM 1140 Vpeak Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial discharge < 5 pC VPR 2137 Vpeak Input to Output Test Voltage, Method a* VIORM x 1.6 = VPR, Type and Sample Test, tm = 10 sec, Partial discharge < 5 pC VPR 1824 Vpeak Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) VIOTM 8000 Vpeak Safety Limiting Values (Maximum values allowed in the event of a failure) Case Temperature Input Current Output Power TS IS, INPUT PS, OUTPUT 175 230 600 °C mA mW Insulation Resistance at TS, VIO = 500 V RS >109  4 Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature TSTG -55 150 °C Operating Ambient Temperature TA -40 125 °C Average Forward Input Current IF(avg) 20 mA Peak Forward Input Current (50% duty cycle, 1 ms pulse width) IF(peak) 40 mA Peak Transient Input Current (≤ 1 s pulse width, 300 ps) IF(trans) 100 mA Reversed Input Voltage VR 5 V Input Power Dissipation (per channel) PIN 30 mW Output Power Dissipation PO 100 mW Average Output Current IO 8 mA Peak Output Current IO(pk) 16 mA Supply Voltag VCC -0.5 30 V Output Voltage VO -0.5 20 V Temperature 260 °C Time 10 s Max. Units 20 V 125 °C Lead Soldering Cycle Note Recommended Operating Conditions Parameter Symbol Supply Voltage VCC Operating Temperature TA Min. -40 Note Electrical Specifications (DC) Over recommended operating TA = -40° C to 125° C, unless otherwise specified Parameter Sym. Min. Typ. Max. Units Test Conditions Fig. Current Transfer Ratio CTR 32 65 100 % TA = 25°C 1, 2, 4 1 24 65 33 160 VCC = 4.5 V, VO = 0.4 V, IF = 1.5 mA 25 165 VCC = 4.5 V, VO = 0.4 V, IF = 0.8 mA Logic Low Output Voltage VOL Logic High Output Current IOH Logic Low Supply Current (per Channel) ICCL Logic High Supply Current (per Channel) ICCH Input Forward Voltage VF 0.1 0.5 V VCC = 4.5 V, IO = 0.2 mA, IF = 0.8 mA 0.1 Input Reversed Breakdown Voltage VCC = 4.5 V, IO = 2.4 mA, IF = 10 mA VCC = 4.5 V, IO = 0.5 mA, IF = 1.5 mA 0.1 3x10-5 0.5 8x10-5 5 85 200 A TA = 25°C A IF = 0 mA 11, 12 IF = 10 mA, VO = open, VCC = 20 V IF = 1.5 mA, VO = open, VCC = 20 V 1 A TA = 25°C IF = 0 mA, VO = open, VCC = 20 V V TA = 25°C IF = 10 mA V IR = 10 A 2.5 BVR 1.45 1.55 1.75 1.25 1.55 1.85 5 Temperature Coefficient VF/ TA of Forward Voltage –1.5 mV/°C IF =10 mA –1.8 IF =1.5 mA Input Capacitance 90 5 VO = VCC = 5.5 V VO = VCC = 20 V 15 0.02 VCC = 4.5 V, VO = 0.4 V, IF = 10 mA CIN pF F = 1 MHz, VF = 0 3 Note Switching Specifications (AC) Over recommended operating (TA = –40°C to 125°C), VCC = 5.0 V unless otherwise specified. Parameter Symbol Min Typ Max Units Test Conditions Fig. Propagation Delay Time to Logic Low at Output tPHL 0.07 0.15 0.8 s TA = 25°C 5, 6, 7, 2, 3 8, 9, 10, 13 Propagation Delay Time to Logic High at Output 0.06 tPLH 0.15 1.0 0.7 5 1 10 0.5 0.8 0.03 5 2 10 Pulse Width Distortion PWD 0.35 0.45 Propagation Delay Difference Between Any 2 Parts PDD 0.35 0.5 Pulse: f = 10 kHz, Duty cycle = 50%, VCC = 5.0 V, CL = 15 pF, IF = 1.5 mA, V THHL = 1.5 V RL = 10 k IF = 0.8 mA, RL = 27 k s TA = 25°C 1.0 0.9 IF = 10 mA, RL = 1.9 k Note IF = 10 mA, RL = 1.9 k Pulse: f = 10 kHz, Duty cycle = 50%, VCC = 5.0 V, CL = 15 pF, IF = 1.5 mA, V THHL = 2.0 V RL = 10 k 5, 6, 7, 2, 3 8, 9, 10, 13 IF = 0.8 mA, RL = 27 k s TA = 25°C Pulse: f = 10 kHz, Duty cycle = 50%, IF = 10 mA, VCC = 5.0 V, RL = 1.9 k, 2, 3, 4 s TA = 25°C Pulse: f = 10 kHz, Duty cycle = 50%, IF = 10 mA, VCC = 5.0 V, RL = 1.9 k, CL = 15 pF, V THHL = 1.5 V, 2, 3, 5 0.85 0.9 Common Mode |CMH| Transient Immunity at Logic High Output 15 30   kV/s  IF = 0 mA Common Mode |CML| Transient Immunity at Logic Low Output 15 30   kV/s  IF = 10 mA Common Mode |CMH| Transient Immunity at Logic High Output 5   kV/s  IF = 0 mA Common Mode |CML| Transient Immunity at Logic Low Output 5   kV/s  IF = 1.5 mA VCM = 1500 Vp-p, RL = 1.9 k, VCC = 5 V, TA = 25°C 14 6 VCM = 1500 Vp-p, RL = 10 k, VCC = 5 V, TA = 25°C 14 6 Package Characteristics Parameter Symbol Min. Input-Output Momentary Withstand Voltage* VISO 5000 Input-Output Resistance RI-O Input-Output Capacitance CI-O * Typ. Max. Units Test Conditions VRMS RH ≤ 50%, t = 1 min., TA = 25°C Fig. Note 1014  VI-O = 500 Vdc 7 0.6 pF f = 1 MHz, VI-O = 0 Vdc 7 7, 8 The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. Notes: 1. Current Transfer Ratio in percent is defined as the ratio of output collector current, IO, to the forward LED input current, IF, times 100. 2. Use of a 0.1 F bypass capacitor connected between pins 5 and 8 is recommended. 3. The 1.9 k load represents 1 TTL unit load of 1.6 mA and the 5.6 k pull-up resistor. 4. Pulse Width Distortion (PWD) is defined as |tPHL – tPLH| for any given device. 5. The difference between tPLH and tPHL between any two parts under the same test condition. 6. Common transient immunity in a Logic High level is the maximum tolerable (positive) dVCM/dt on the rising edge of the common mode pulse, VCM, to assure that the ouput will remain in a Logic High state (i.e., VO > 2.0 V). Common mode transient immunity in a Logic Low level is the maximum tolerable (negative) dVCM/dt on the falling edge of the common mode pulse signal, VCM to assure that the output will remain in a Logic Low state (i.e., VO < 0.8 V). 7. Device considered a two terminal device: pins 1, 2, 3 and 4 shorted together, and pins 5, 6, 7 and 8 shorted together. 8. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage > 6000 VRMS for 1 second. 6 VCC = 5.0 V TA = 25° C IO - OUTPUT CURRENT - mA 25 40 mA 35 mA 30 mA 25 mA 20 mA 20 15 mA 15 10 mA 10 IF = 5 mA 5 0 0 10 VO - OUTPUT VOLTAGE - V 20 Figure 1. DC and Pulsed Transfer Characteristics NORMALIZED CURRENT TRANSFER RATIO IF - FORWARD CURRENT - mA TA = 125° C TA = 25° C TA = -40° C 1.20 1.30 1.40 1.50 1.60 1.70 VF - FORWARD VOLTAGE - V 1.80 1.90 2.0 1.5 1.0 0.5 0.0 0.1 1.0 10.0 IF - INPUT CURRENT - mA 100.0 1.0 0.9 Normalized IF = 10 mA, VO = 0.4 V VCC = 5.0 V TA = 25° C 0.8 0.7 0.6 -60 -20 20 60 TA - TEMPERATURE - °C 100 140 Figure 4. Current Transfer Ratio vs. Temperature 1.2 TLH, Vcc = 5 V TLH, Vcc = 3.3 V THL, Vcc = 5 V THL, Vcc = 3.3 V 1.2 1.0 0.8 0.6 0.4 0.2 Propagation Delay Time - μs 1.4 Propagation Delay Time - μs 2.5 1.1 Figure 3. Input Current vs. Forward Voltage TLH, Vcc = 20 V TLH, Vcc = 15 V THL, Vcc = 20 V THL, Vcc = 15 V 1.0 0.8 0.6 0.4 0.2 0.0 0.0 -55 -35 -15 5 25 45 65 85 105 125 145 Ambient Temperature TA - °C Figure 5, Propagation Delay Time vs. Temperature IF = 10 mA, RL = 1.9 k, CL = 15 pF 7 3.0 Figure 2. Current Transfer Ratio vs. Input Current VO = 0.4 V, VCC = 5 V, TA = 25°C 10.0 1.0 NORMALIZED CURRENT TRANSFER RATIO 30 -55 -35 -15 5 25 45 65 85 105 125 145 Ambient Temperature TA - °C Figure 6. Propagation Delay Time vs. Temperature IF = 10 mA, RL = 20 k, CL = 100 pF TLH, Vcc = 5 V TLH, Vcc = 3.3 V THL, Vcc = 5 V THL, Vcc = 3.3 V 2.5 2.0 Propagation Delay TP - μs Propagation Delay TP - μs 3.0 1.5 1.0 0.5 0.0 1 2 3 4 5 6 7 Load Resistance RL - kΩ 8 9 10 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 TLH, Vcc = 5 V TLH, Vcc = 3.3 V THL, Vcc = 5 V THL, Vcc = 3.3 V 10 11 12 13 14 Input Current IF - mA 15 16 TLH, Vcc = 5 V TLH, Vcc = 3.3 V THL, Vcc = 5 V THL, Vcc = 3.3 V Propagation Delay Tp (μs) Propagation Delay Tp (μs) 3 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 Input Current IF (mA) Figure 10a. Propagation Delay Time vs. Input Current RL = 10 k, CL = 15 pF, TA = 25°C 8 5 10 15 20 25 30 35 Load Resistance RL - kΩ 40 45 50 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 TLH, Vcc = 20 V TLH, Vcc = 15 V THL, Vcc = 20 V THL, Vcc = 15 V 10 11 12 13 14 Input Current IF - mA 15 16 Figure 10. Propagation Delay Time vs. Input Current RL = 20 k, CL = 15 pF, TA = 25°C Figure 9. Propagation Delay Time vs. Input Current RL = 1.9 k, CL = 15 pF, TA = 25°C 2.5 TLH, Vcc = 20 V TLH, Vcc = 15 V THL, Vcc = 20 V THL, Vcc = 15 V Figure 8. Propagation Delay Time vs. Load Resistance Propagation Delay TP - μs Propagation Delay TP - μs Figure 7. Propagation Delay Time vs. Load Resistance 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.5 5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 TLH, Vcc = 5 V TLH, Vcc = 3.3 V THL, Vcc = 5 V THL, Vcc = 3.3 V 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 Input Current IF (mA) Figure 10b. Propagation Delay Time vs. Input Current RL = 27 k, CL = 15 pF, TA = 25°C 3 1000 100 100 10 TA = 125° C IF = 0 mA VCC = VO 1 IOH - LOGIC HIGH OUTPUT - nA IOH - LOGIC HIGH OUTPUT - nA 1000 TA = 25° C 0.1 0.01 TA = -40° C 0.001 0.0001 2 4 6 8 10 12 14 VCC - SUPPLY VOLTAGE - V 16 18 IF = 0 mA VCC = VO = 5 V 10 1 0.1 0.01 0.001 0.0001 -50 20 Figure 11. Logic High Output Current vs. Supply Voltage 0 50 100 TA - TEMPERATURE - °C Figure 12. Logic High Output Current vs. Temperature 10% DUTY CYCLE 1/f < 100 μs PULSE GEN. ZO = 50 Ω tr = 5 ns IF 0 1.5 V +5 V IF MONITOR 5V VO IF 100 Ω 2.0 V 8 2 7 3 6 4 5 RL VO 0.1 μF CL = 15 pF VOL tPHL 1 tPLH Figure 13. Switching Test Circuit IF 1500 V VCM 0V VCC tr, tf = 80 ns 10% 90% tr 90% B 10% 1 8 2 7 tf 5V SWITCH AT A: IF = 0 mA VO VOL SWITCH AT B: IF = 10 mA 3 6 4 5 + - VCM PULSE GEN. Figure 14. Test Circuit for Transient Immunity and Typical Waveforms 9 VO 0.1 μF VFF VO RL A 150 Thermal Resistance Model for ACPL-K43T The diagram of ACPL-K43T for measurement is shown in Figure 15. Here, one die is heated first and the temperatures of all the dice are recorded after thermal equilibrium is reached. Then, the 2nd die is heated and all the dice temperatures are recorded. With the known ambient temperature, the die junction temperature and power dissipation, the thermal resistance can be calculated. The thermal resistance calculation can be cast in matrix form. This yields a 2 by 2 matrix for our case of two heat sources. R11 R21 R12 R22 X P1 P2 = T1 T2 1 R11 : Thermal Resistance of Die1 due to heating of Die1 (˚C/W) 2 R12 : Thermal Resistance of Die1 due to heating of Die2 (˚C/W) R21 : Thermal Resistance of Die2 due to heating of Die1 (˚C/W) R22 : Thermal Resistance of Die2 due to heating of Die2 (˚C/W) 8 Die1: LED Die2: Detector 7 3 6 4 5 P1 : Power dissipation of Die1 (W) Figure 15. Diagram of ACPL-K43T for measurement P2 : Power dissipation of Die2 (W) T1 : Junction temperature of Die1 due to heat from all dice (˚C) T2 : Junction temperature of Die2 due to heat from all dice (˚C) Ta : Ambient temperature (˚C) T1 : Temperature difference between Die1 junction and ambient (˚C) T2 : Temperature deference between Die2 junction and ambient (˚C) T1 = (R11 x P1 + R12 x P2) + Ta T2 = (R21 x P1 + R22 x P2) + Ta Measurement data on a low K board: R11 = 160°C/W, R12= R21 = 74°C/W, R22 = 115°C/W Thermal Resistance Model for ACPL-K44T The diagram of ACPL-K44T for measurement is shown in Figure 16. Here, one die is heated first and the temperatures of all the dice are recorded after thermal equilibrium is reached. Then, the 2nd ,3rd and 4th die is heated and all the dice temperatures are recorded. With the known ambient temperature, the die junction temperature and power dissipation, the thermal resistance can be calculated. The thermal resistance calculation can be cast in matrix form. This yields a 4 by 4 matrix for our case of two heat sources. R11 R21 R31 R41 R11 R12 R13 R14 R21 R22 R23 R24 10 R12 R22 R32 R42 R13 R23 R33 R43 R14 R24 R34 R44 X P1 P2 P3 P4 = T1 T2 T3 T4 : Thermal Resistance of Die1 due to heating of Die1 (˚C/W) : Thermal Resistance of Die1 due to heating of Die2 (˚C/W) : Thermal Resistance of Die1 due to heating of Die3 (˚C/W) : Thermal Resistance of Die1 due to heating of Die4 (˚C/W) : Thermal Resistance of Die2 due to heating of Die1 (˚C/W) : Thermal Resistance of Die2 due to heating of Die2 (˚C/W) : Thermal Resistance of Die2 due to heating of Die3 (˚C/W) : Thermal Resistance of Die2 due to heating of Die4 (˚C/W) 1 8 Die1: LED 1 Die2: Detector 1 2 3 4 7 Die3: LED 1 Die4: Detector 2 6 5 Figure 16. Diagram of ACPL-K44T for measurement R31 : Thermal Resistance of Die3 due to heating of Die1 (˚C/W) R32 : Thermal Resistance of Die3 due to heating of Die2 (˚C/W) R33 : Thermal Resistance of Die3 due to heating of Die3 (˚C/W) R34 : Thermal Resistance of Die3 due to heating of Die4 (˚C/W) R41 : Thermal Resistance of Die4 due to heating of Die1 (˚C/W) R42 : Thermal Resistance of Die4 due to heating of Die2 (˚C/W) R43 : Thermal Resistance of Die4 due to heating of Die3 (˚C/W) R44 : Thermal Resistance of Die4 due to heating of Die4 (˚C/W) P1 : Power dissipation of Die1 (W) P2 : Power dissipation of Die2 P3 : Power dissipation of Die3 (W) P4 : Power dissipation of Die4 T1 : Junction temperature of Die1 due to heat from all dice (˚C) T2 : Junction temperature of Die2 due to heat from all dice (˚C) T3 : Junction temperature of Die3 due to heat from all dice (˚C) T4 : Junction temperature of Die4 due to heat from all dice (˚C) Ta : Ambient temperature (˚C) T1 : Temperature difference between Die1 junction and ambient (˚C) T2 : Temperature deference between Die2 junction and ambient (˚C) T3 : Temperature difference between Die3 junction and ambient (˚C) T4 : Temperature deference between Die4 junction and ambient (˚C) T1 = (R11 x P1 + R12 x P2 + R13 x P3 + R14 x P4 ) + Ta -- (1) T2 = (R21 x P1 + R22 x P2 + R23 x P3 + R24 x P4) + Ta -- (2) T3 = (R31 x P1 + R32 x P2 + R33 x P3 + R34 x P4) + Ta -- (3) T4 = (R41 x P1 + R42 x P2 + R43 x P3 + R44 x P4 ) + Ta -- (4) Measurement data on a low K board: R11 R12 R13 R14 R21 R22 R23 R24 R31 R32 R33 R34 R41 R42 R43 R44 160 76 76 76 76 115 76 76 76 76 160 76 76 76 76 115 For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, the A logo, and R2Coupler are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2012–2016 Avago Technologies. All rights reserved. AV02-3179EN - October 19, 2016