ACPL-M61T
10MBd Wide Operating Temperature Automotive Digital Optocoupler
with R2Coupler™ Isolation and AEC-Q100 Qualification
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
This small outline wide operating temperature, high
CMR, high speed, logic gate optocoupler is a single
channel device in a five lead miniature footprint.
x High Temperature and Reliability CANBus communication interface for Automotive Application.
x 15 kV/Ps High Common-Mode Rejection at VCM = 1000 V
The ACPL-M61T optically coupled gates combine a
AlGaAs light emitting diode and an integrated high
gain photo detector. The output of the detector IC is an
Open-collector Schottky-clamped transistor. The internal
shield provides a guaranteed common mode transient
immunity specification of 15,000 V/μs at VCM=1000V.
x
x
x
x
x
x
This optocoupler is suitable for use in automotive high
speed communications logic interfacing with low propagation delays, input/output buffering and is recommended for use in high operating temperature environment.
This unique design provides maximum AC and DC circuit
isolation while achieving TTL compatibility. The optocoupler AC and DC operational parameters are guaranteed
from -40°C to 125°C.
R2Coupler
Avago
isolation products provide the reinforced insulation and reliability needed for critical in automotive and high temperature industrial applications.
Functional Diagram
ANODE 1
Compact, Auto-Insertable SO5 Packages
Wide Temperature Range: -40°C ~ 125°C
High Speed: 10MBd (Typical)
Low LED Drive Current: 6.5mA (typ)
Low Propagation Delay: 100ns (max)
Worldwide Safety Approval:
− UL 1577, 4000 Vrms/1 min.
− CSA File CA88324, Notice #5
− IEC/EN/DIN EN 60747-5-2 Approved
x Qualified to AEC-Q100 Test Guidelines
Applications
x
x
x
x
Automotive CANBus Communications Interface
High Temperature Digital Signal Isolation
Micro-controller Interface
Digital isolation for A/D, D/A conversion
6 V CC
5 VO
CATHODE
3
4 GND
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
Option
Part Number
(RoHS) Compliant
Package
Surface
Mount
ACPL-M61T
-000E
SO-5
X
Tape
& Reel
IEC/EN/DIN EN
60747-5-2
Quantity
100 per tube
-060E
X
X
-500E
X
X
-560E
X
X
100 per tube
1500 per reel
X
1500 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-M61T-500E to order product of Mini-flat Surface Mount 5-pin package in Tape and Reel packaging with RoHS
compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Schematic
+
Land Pattern Recommendation
IF
ICC
6
1
IO
5
4.4
(0.17)
V CC
VO
1.3
(0.05)
2.5
(0.10)
4
3
GND
TRUTH TABLE
(POSITIVE LOGIC)
LED OUTPUT
L
ON
H
OFF
SHIELD
USE OF A 0.1 μF BYPASS CAPACITOR
MUST BE CONNECTED BETWEEN PINS
6 AND 4 (SEE NOTE 1).
2.0
(0.080)
0.64
(0.025)
8.27
(0.325)
Package Outline Drawings
ACPL-M61T Small Outline SO-5 Package (JEDEC MO-155)
Extended Datecode
for lot tracking
4.4 ± 0.1
(0.173 ± 0.004)
M61T
YWW
EE
7.0 ± 0.2
(0.276 ± 0.008)
DIMENSIONS IN MILLIMETERS (INCHES)
* MAXIMUM MOLD FLASH ON EACH SIDE IS 0.15 mm (0.006)
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
0.4 ± 0.05
(0.016 ± 0.002)
3.6 ± 0.1*
(0.142 ± 0.004)
2.5 ± 0.1
(0.098 ± 0.004)
0.20 ± 0.025
(0.008 ± 0.001)
0.102 ± 0.102
(0.004 ± 0.004)
7 o MAX.
1.27 BSC
(0.050)
0.71 MIN.
(0.028)
MAX. LEAD COPLANARITY
= 0.102 (0.004)
2
Recommended Pb-Free IR Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision).
Note: Non-halide flux should be used.
Regulatory Information
The ACPL-M61T is approved by the following organizations:
UL
IEC/EN/DIN EN 60747-5-2
Approved under UL 1577, component recognition
program up to VISO = 4000 VRMS
Approved under:
IEC 60747-5-2:1997 + A1
EN 60747-5-2:2001 + A1
DIN EN 60747-5-2 (VDE 0884 Teil 2)
CSA
Approved under CSA Component Acceptance Notice #5.
IEC/EN/DIN EN 60747-5-2 Insulation Characteristics*
Description
Symbol
Characteristic
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 600 Vrms
I – IV
I – III
I – II
Climatic Classification
55/125/21
Pollution Degree (DIN VDE 0110/1.89)
2
Unit
Maximum Working Insulation Voltage
VIORM
567
Vpeak
Input to Output Test Voltage, Method b*
VIORM x 1.875=VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC
VPR
1063
Vpeak
Input to Output Test Voltage, Method a*
VIORM x 1.6=VPR, Type and Sample Test, tm=10 sec, Partial discharge < 5 pC
VPR
907
Vpeak
Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec)
VIOTM
6000
Vpeak
Safety-limiting values – maximum values allowed in the event of a failure.
Case Temperature
Input Current
Output Power
TS
IS, INPUT
PS, OUTPUT
175
230
600
°C
mA
mW
Insulation Resistance at TS, VIO = 500 V
RS
>109
:
*
Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/
DIN EN 60747-5-2) for a detailed description of Method a and Method b partial discharge test profiles.
Insulation and Safety Related Specifications
Parameter
Symbol
ACPL-M61T Units
Conditions
Minimum External Air
Gap (Clearance)
L(101)
≥5
mm
Measured from input terminals to output terminals, shortest distance
through air.
Minimum External
Tracking (Creepage)
L(102)
≥5
mm
Measured from input terminals to output terminals, shortest distance
path along body.
0.08
mm
Through insulation distance conductor to conductor, usually the
straight line distance thickness between the emitter and detector.
175
V
DIN IEC 112/VDE 0303 Part 1
Minimum Internal Plastic
Gap (Internal Clearance)
Tracking Resistance
(Comparative Tracking
Index)
Isolation Group
(DIN VDE0109)
3
CTI
IIIa
Material Group (DIN VDE 0109)
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
-55
125
°C
Operating Temperature
TA
-40
125
°C
260
°C
Note
Lead Soldering Cycle
Temperature
10
sec
Input Current
Average
IF(avg)
20
mA
(50% duty cycle, 1ms pulse width)
Peak
IF(peak)
40
mA
( 2.0 V).
8. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., VOUT < 0.8 V).
9. For sinusoidal voltages, (|dVCM|/dt)max = SfCMVCM(p-p).
10. See application section; “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information.
11. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the worst case
operating condition range.
12. Input current derates linearly above 85°C free-air temperature at a rate of 0.25 mA/°C.
13. Input power derates linearly above 85°C free-air temperature at a rate of 0.375mW/°C.
14. Output power derates linearly above 85°C free-air temperature at a rate of 0.475 mW/°C.
5
3.5
0.5
VOL - LOW LEVEL OUTPUT VOLTAGE - V
I OH - HIGH LEVEL OUTPUT CURRENT - uA
V CC = 5.5V
I F = 6.5mA
3
2.5
2
V CC = 5.5V
V O = 5.5V
V F = 0.5V
1.5
1
0.5
0
-60
-40
-20
0
20
40
60
TA - TEMPERATURE - oC
80
100
120
0.4
IO = 16mA
IO = 12.8mA
0.3
IO = 6.4mA
0.2
0.1
-60
140
Figure 1. High Level Output Current vs Temperature
IO = 9.6mA
-40
-20
0
20
40
60
TA - TEMPERATURE - oC
80
100
120
140
Figure 2. Low Level Output Voltage vs. Temperature
100.00
6
VCC =5V
TA= 25oC
TA = 25oC
VO - OUTPUT VOLTAGE - V
IF - FORWARD CURRENT - mA
5
10.00
1.00
0.10
R load = 350Ω
4
R load = 1kΩ
3
R load = 4kΩ
2
1
0.01
1.20
0
1.30
1.40
VF - Forward Voltage - VOLTS
1.50
1.60
IOL - LOW LEVEL OUTPUT CURRENT - mA
VCC = 5.0V
VOL = 0.6V
50
I F = 10mA, 15mA
40
I F = 5mA
30
20
10
-20
0
20
40
60
TA - TEMPERATURE - oC
Figure 5. Low Level Output Current vs. Temperature
6
0.4
0.6
0.8
1
Figure 4. Output Voltage vs Forward Input current
60
-40
0.2
IF - FORWARD INPUT CURRENT - mA
Figure 3. Input Current vs Forward Voltage
0
-60
0
80
100
120
140
1.2
1.4
1.6
PULSE GEN.
Z O = 50 Ω
t f = t r = 5 ns
+5 V
IF
V CC
1
6
RL
0.1μF
BYPASS
OUTPUT V O
MONITORING
NODE
5
*C L
INPUT
MONITORING
NODE
3
GND
4
RM
*C L IS APPROXIMATELY 15 pF WHICH INCLUDES
PROBE AND STRAY WIRING CAPACITANCE.
IF = 6.5 mA
INPUT
IF
IF = 3.25 mA
t PLH
t PHL
OUTPUT
VO
1.5 V
Figure 6. Test Circuit for tPHL and tPLH
90
120
V CC = 5.0V
I F = 6.5mA
80
tPLH, R L = 350Ω
80
t PLH , R L = 1kΩ
60
t PHL
R L = 350Ω
1kΩ
4kΩ
40
20
t PLH , R L = 4Ω
70
60
t PLH , R L = 1kΩ
50
tPLH , R L = 350Ω
tPHL
R L = 350Ω
1kΩ
4kΩ
40
30
-40
-20
0
20
40
60
TA - TEMPERATURE -
Figure 7. Propagation Delay vs. Temperature
7
tP - PROPOGATION DELAY - ns
tp - PROPOGATION DELAY - ns
100
0
-60
V CC = 5.0V
TA = 25oC
t PLH , R L = 4kΩ
oC
80
100
120
140
3
5
7
IF - PULSE INPUT CURRENT - mA
Figure 8. Propagation Delay vs. Pulse Input Current
9
40
350
V CC = 5.0V
I F = 6.5mA
R L = 4kΩ
300
30
R L = 4kΩ
tr, tf - Rise, Fall Time - ns
PWD - PULSE WIDTH DISTORTION - ns
V CC = 5.0V
I F = 6.5mA
20
R L = 350Ω
10
R L = 1kΩ
250
t RISE
t FALL
200
150
100
R L = 1kΩ
0
R L = 350
50
-10
-60
-40
-20
0
20
40
60
TA - TEMPERATURE - oC
80
100
120
0
-60
140
Figure 9. Pulse Width Distortion vs Temperature
R L =350Ω , 1 kΩ , 4 kΩ
-40
+5 V
B
VCC
6
A
0.1 μF
BYPASS
5
V FF
3
GND
350 Ω
OUTPUT V O
MONITORING
NODE
4
_
+
PULSE
GENERATOR
Z O = 50 Ω
V CM (PEAK)
V CM
0V
5V
VO
VO
0.5 V
SWITCH AT A: I F = 0 mA
CM H
V O (MIN.)
SWITCH AT B: I F = 6.5 mA
V O (MAX.)
CM L
Figure 11. Test Circuit for Common Mode Transient Immunity and Typical Waveforms
dVF/dT - FORWARD VOLTAGE
TEMPERATURE COEFFICIENT - mV/oC
-2.300
-2.200
-2.100
-2.000
-1.900
-1.800
0.1
1
10
IF - PULSE INPUT CURRENT - mA
100
Figure 12. Temperature Coefficient for Forward Voltage vs. Input Current
8
0
20
40
60
TA - TEMPERATURE - oC
Figure 10. Rise and Fall Time vs.Temperature
IF
1
-20
80
100
120
140
Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew
Propagation delay is a figure of merit which describes
how quickly a logic signal propagates through a system.
The propagation delay from low to high (tPLH) is the
amount of time required for an input signal to propagate
to the output, causing the output to change from low
to high. Similarly, the propagation delay from high to
low (tPHL) is the amount of time required for the input
signal to propagate to the output, causing the output to
change from high to low (see Figure 6).
Pulse-width distortion (PWD) results when tPLH and tPHL
differ in value. PWD is defined as the difference between
tPLH and tPHL and often determines the maximum data
rate capability of a transmission system. PWD can be
expressed in percent by dividing the PWD (in ns) by
the minimum pulse width (in ns) being transmitted.
Typically, PWD on the order of 20-30% of the minimum
pulse width is tolerable; the exact figure depends on the
particular application (RS232, RS422, T-1, etc.).
Propagation delay skew, tPSK, is an important parameter
to consider in parallel data applications where synchronization of signals on parallel data lines is a concern.
If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause
the data to arrive at the outputs of the optocouplers at
different times. If this difference in propagation delays
is large enough, it will determine the maximum rate at
which parallel data can be sent through the optocouplers.
As mentioned earlier, tPSK can determine the maximum
parallel data transmission rate. Figure 15 is the timing
diagram of a typical parallel data application with both
the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the
inputs and outputs of the optocouplers. To obtain the
maximum data transmission rate, both edges of the clock
signal are being used to clock the data; if only one edge
were used, the clock signal would need to be twice as
fast.
Propagation delay skew represents the uncertainty of
where an edge might be after being sent through an optocoupler. Figure 15 shows that there will be uncertainty
in both the data and the clock lines. It is important that
these two areas of uncertainty not overlap, otherwise the
clock signal might arrive before all of the data outputs
have settled, or some of the data outputs may start to
change before the clock signal has arrived. From these
considerations, the absolute minimum pulse width that
can be sent through optocouplers in a parallel application is twice tPSK. A cautious design should use a slightly
longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem.
The tPSK specified optocouplers offer the advantages
of guaranteed specifications for propagation delays,
pulse-width distortion and propagation delay skew over
the recommended temperature, and input current, and
power supply ranges.
Propagation delay skew is defined as the difference
between the minimum and maximum propagation
delays, either tPLH or tPHL, for any given group of optocouplers which are operating under the same conditions
(i.e., the same drive current, supply voltage, output load,
and operating temperature). As illustrated in Figure 14,
if the inputs of a group of optocouplers are switched
either ON or OFF at the same time, tPSK is the difference
between the shortest propagation delay, either tPLH or
tPHL, and the longest propagation delay, either tPLH or
tPHL.
VCC 1
5V
6
5V
V CC 2
390 Ω
470
IF
5
1
*D1
VF
0.1 μF
BYPASS
3
GND 1
4
2
1
* DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED
FOR UNITS WITH OPEN COLLECTOR OUTPUT.
Figure 13. Recommended TTL/LSTTL to TTL/LSTTL Interface Circuit.
9
GND 2
SHIELD
IF
50%
DATA
INPUTS
1.5 V
VO
IF
CLOCK
50%
DATA
VO
1.5 V
OUTPUTS
t PSK
t PSK
CLOCK
t PSK
Figure 14. Illustration of Propagation Delay Skew – tPSK
Figure 15. Parallel Data Transmission Example
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, the A logo and R2Coupler™ are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved. Obsoletes AV01-0610EN
AV02-0597EN - March 7, 2011
