Data Sheet
ACPL-M75L
High-Speed 15 MBd CMOS Optocoupler
Features
Description
The Broadcom® ACPL-M75L is a 15 MBd CMOS
optocoupler in a SOIC-5 package. This optocoupler utilizes
the latest CMOS IC technology to achieve outstanding
performance with very low power consumption. The basic
building blocks of the ACPL-M75L are high-speed LEDs
and CMOS detector ICs. Each detector incorporates an
integrated photodiode, a high-speed transimpedance
amplifier, and a voltage comparator with an output driver.
Functional Diagram
ACPL-M75L
6 VDD
Anode 1
Applications
5 Vo
Cathode 3
4 GND
SHIELD
NOTE:
Digital field bus isolation:
– RS485, RS232, CANbus
Multiplexed data transmission
Computer peripheral interface
Microprocessor system interface
DC/DC converter
Servo motor
A 0.1-μF bypass capacitor must be connected
between pins 4 and 6.
Truth Table
Broadcom
+3.3V and +5V CMOS compatibility
25 ns max. pulse width distortion
55 ns max. propagation delay
40 ns max. propagation delay skew
High speed: 15 MBd min
10 kV/µs minimum Common-Mode Rejection (CMR)
–40°C to +105°C temperature range
Safety and regulatory approvals:
– UL recognized: 3750 Vrms for 1 min. per UL 1577
– CSA component acceptance Notice #5
– IEC/EN/DIN EN 60747-5-5 approved Option 060
LED
VO, Output
OFF
H
ON
L
CAUTION! It is advised that normal static precautions be
taken in handling and assembly of this
component to prevent damage and/or
degradation which may be induced by ESD.
The components featured in this data sheet are
not to be used in military or aerospace
applications or environments. The components
are not AEC-Q100 qualified and not
recommended for automotive applications.
AV02-0964EN
September 15, 2020
ACPL-M75L Data Sheet
High-Speed 15 MBd CMOS Optocoupler
Ordering Information
ACPL-M75L will be UL Recognized with 3750 Vrms for 1 minute per UL1577.
Part Number
ACPL-M75L
Option
Package
Surface Mount
-000E
SO-5
X
-500E
X
-060E
X
-560E
X
Tape and Reel
IEC/EN/DIN EN
60747-5-5
Quantity
100 per tube
X
X
1500 per reel
X
100 per tube
X
1500 per reel
To order, choose a part number from the part number column and combine with the desired option from the option column
to form an order entry.
Example 1:
Use part number ACPL-M75L-500E to order a product with a Small Outline SO-5 package in Tape and Reel packaging in
RoHS compliant.
Example 2:
Use part number ACPL-M75L-000E to order a product with a Small Outline SO-5 package in tube packaging and in RoHS
compliant.
Option data sheets are available. Contact your Broadcom sales representative or authorized distributor for information.
Broadcom
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ACPL-M75L Data Sheet
High-Speed 15 MBd CMOS Optocoupler
Package Outline Drawing
ACPL-M75L (JEDEC MO-155 Package)
LAND PATTERN RECOMMENDATION
0.33
(0.013)
Device
Part Number
1.27
(0.05)
0.64
(0.025)
Test Rating
Code
4.4 ± 0.1
(0.173 ± 0.004)
Lead Free
NNNN Z
• YYWW
EEE
7.0 ± 0.2
(0.276 ± 0.008)
Date Code
4.39
(0.17)
8.26
(0.325)
Lot ID
Pin 1 Dot
1.80
(0.071)
0.4 ± 0.05
(0.016 ± 0.002)
2.54
(0.10)
3.6 ± 0.1*
(0.142 ± 0.004)
2.5 ± 0.1
(0.098 ± 0.004)
0.102 ± 0.102
(0.004 ± 0.004)
1.27 BSC
(0.050)
0.20 ± 0.025
(0.008 ± 0.001)
0.71 MIN
(0.028)
Dimensions in millimeters (inches).
Note: Foating Lead Protrusion is 0.15 mm (6 mils) max.
7° MAX.
MAX. LEAD COPLANARITY
= 0.102 (0.004)
* Maximum Mold flash on each side is 0.15 mm (0.006).
Reflow Soldering Profile
The recommended reflow soldering conditions are per JEDEC Standard J-STD-020 (latest revision). Non-halide flux should
be used.
Broadcom
AV02-0964EN
3
ACPL-M75L Data Sheet
High-Speed 15 MBd CMOS Optocoupler
Regulatory Information
The ACPL-M75L has been approved by the following organizations:
UL – Recognized under UL 1577, component recognition program, File E55361.
CSA – Approval under CSA Component Acceptance Notice #5, File CA 88324.
IEC/EN/DIN EN 60747-5-5
Insulation and Safety Related Specifications
Parameter
Symbol
Value
Unit
L(I01)
≥5
mm
L(I02)
≥5
mm
0.08
mm
≥175
V
Minimum External Air Gap
(Clearance)
Minimum External Tracking
(Creepage)
Minimum Internal Plastic Gap
(Internal Clearance)
Tracking Resistance
(Comparative Tracking Index)
Isolation Group
CTI
IIIa
Conditions
Measured from input terminals to output terminals,
shortest distance through air.
Measured from input terminals to output terminals,
shortest distance path along body.
Insulation thickness between emitter and detector;
also known as distance through insulation.
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
IEC/EN/DIN EN 60747-5-5 Insulation Related Characteristics (Option 060)
Description
Symbol
Installation Classification per DIN VDE 0110/1.89, Table 1
For Rated Mains Voltage ≤150 Vrms
Option 060
Unit
I-IV
I-III
For Rated Mains Voltage ≤300 Vrms
Climatic Classification
55/105/21
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
ba
Input to Output Test Voltage, Method
VIORM x 1.875 = VPR, 100% Production
2
VIORM
567
VPEAK
VPR
1063
VPEAK
VPR
907
VPEAK
VIOTM
6000
VPEAK
Ts
150
150
600
°C
mA
mW
≥109
Ω
Test with tm = 1s, Partial Discharge < 5 pC
Input to Output Test Voltage, Method aa
VIORM x 1.6 = VPR, Type and Sample Test,
tm = 10s, Partial Discharge < 5 pC
Highest Allowable Overvoltage
(Transient Overvoltage, tini = 60s)
Safety Limiting Values (Maximum values allowed in the event of a failure,
also see Thermal Derating curve, Figure 11.)
Case Temperature
Input Current
Output Power
Insulation Resistance at TS, VIO = 500V
Is, INPUT
Ps, OUTPUT
RIO
a. Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section,
(IEC/EN/DIN EN 60747-5-5) for a detailed description of Method a and Method b partial discharge test profiles.
Broadcom
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ACPL-M75L Data Sheet
High-Speed 15 MBd CMOS Optocoupler
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Unit
Storage Temperature
TS
–55
+125
°C
Ambient Operating Temperature
TA
–40
+105
°C
Supply Voltages
VDD
0
6.0
V
Output Voltage
VO
–0.5
VDD + 0.5
V
Average Forward Input Current
IF
—
10.0
mA
Average Output Current
IO
—
10.0
mA
Lead Solder Temperature
260°C for 10s, 1.6 mm below seating plane
Solder Reflow Temperature Profile
See Reflow Soldering Profile.
Recommended Operating Conditions
Parameter
Ambient Operating Temperature
Supply Voltages
Symbol
Min.
Max.
Unit
TA
–40
+105
°C
VDD
4.5
5.5
V
3.0
3.6
V
IF
4
8
mA
VF(OFF)
0
0.8
V
SR
0.5
500
V/ms
Input Current (ON)
Forward Input Voltage (OFF)
Supply Voltage Slew Rate
a
a. Slew rate of supply voltage ramping is recommended to ensure no glitch more than 1V to appear at the output pin.
Electrical Specifications
Over recommended temperature (TA = –40°C to +105°C), 3.0V ≤ VDD ≤ 3.6V and 4.5V ≤ VDD ≤ 5.5V.
All typical specifications are at TA = +25°C, VDD = +3.3V.
Parameter
Symbol
Min.
Typ.
Max.
Unit
VF
1.3
1.5
1.8
V
IF = 6 mA
Input Reverse Breakdown Voltage
BVR
5.0
—
—
V
IR = 10 µA
Logic High Output Voltage
VOH
VDD – 1
VDD – 0.3
—
V
IF = 0, IO = –4 mA, VDD = 3.3V
VDD – 1
VDD – 0.2
—
V
IF = 0, IO = –4 mA, VDD = 5V
—
0.2
0.8
V
IF = 6 mA, IO = 4 mA, VDD = 3.3V
Input Forward Voltage
Test Conditions
Logic Low Output Voltage
VOL
—
0.35
0.8
V
Input Threshold Current
ITH
—
1
3
mA
IOL = 20 µA
Logic Low Output Supply Current
IDDL
—
4.5
6.5
mA
IF = 6 mA
Logic High Output Supply Current
IDDH
—
4
6
mA
IF = 0
Broadcom
IF = 6 mA, IO = 4 mA, VDD = 5V
AV02-0964EN
5
ACPL-M75L Data Sheet
High-Speed 15 MBd CMOS Optocoupler
Switching Specifications
Over recommended temperature (TA = –40°C to +105°C), 3.0V ≤ VDD ≤ 3.6V and 4.5V ≤ VDD ≤ 5.5V.
All typical specifications are at TA = +25°C, VDD = +3.3V.
Parameter
Symbol
Min.
Typ.
Max.
Unit
Propagation Delay Time to Logic Low Outputa
tPHL
—
25
55
ns
Propagation Delay Time to Logic High Outputa
tPLH
—
21
55
ns
Pulse Width
tPW
66.7
—
—
ns
|PWD |
0
4
25
ns
tPSK
—
—
40
ns
Output Rise Time (10% to 90%)
tR
—
3.5
—
ns
Output Fall Time (90% to 10%)
tF
—
3.5
—
ns
| CMH |
10
15
—
kV/µs
30
35
—
kV/µs
10
15
—
kV/µs
30
35
—
kV/µs
Pulse Width Distortionb
Propagation Delay Skewc
Common Mode Transient Immunity at Logic High
Outputd
Common Mode Transient Immunity at Logic Low
Outpute
| CML |
Test Conditions
IF = 6 mA, CL= 15 pF
CMOS signal levels
IF = 6 mA, CL= 15 pF,
CMOS signal levels
IF = 6 mA, CL= 15 pF,
CMOS signal levels
IF = 6 mA, CL= 15 pF
CMOS signal levels
IF = 6 mA, CL= 15 pF
CMOS signal levels
IF = 6 mA, CL= 15 pF
CMOS signal levels
VCM = 1000V, TA = 25°C,
IF = 0 mA (Figure 18)
Using Broadcom’s Application
Circuit (Figure 13)
VCM = 1000V, TA = 25°C,
IF = 6 mA (Figure 18)
Using Broadcom’s Application
Circuit (Figure 13)
a. tPHL propagation delay is measured from the 50% VDD level on the rising edge of the input pulse to the 50% VDD level of the falling edge of
the VO signal. tPLH propagation delay is measured from the 50% VDD level on the falling edge of the input pulse to the 50% VDD level of the
rising edge of the VO signal
b. PWD is defined as |tPHL – tPLH|.
c. tPSK is equal to the magnitude of the worst-case difference in tPHL and/or tPLH that will be seen between units at any given temperature within
the recommended operating conditions.
d. CMH is the maximum tolerable rate of rise of the common mode voltage to ensure that the output remains in a high logic state.
e. CML is the maximum tolerable rate of fall of the common mode voltage to ensure that the output remains in a low logic state.
Package Characteristics
All typical specifications are at TA = 25°C.
Parameter
Symbol
Min.
Typ.
Max.
Unit
II-O
—
—
1.0
µA
45% RH, t = 5s, VI-O = 3 kV DC,
TA = 25°C
Input-Output Momentary Withstand Voltagea
VISO
3750
—
Vrms
RH ≤ 50%, t = 1 min., TA = 25°C
Input-Output Resistance
R I-O
—
—
Ω
VI-O = 500 V dc
Input-Output Capacitance
C I-O
—
—
pF
f = 1 MHz, TA = 25°C
Input-Output Insulation
1012
0.6
Test Conditions
a. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 Vrms for 1 second (Leakage
detection current limit, II-O ≤ 5 μA).
Broadcom
AV02-0964EN
6
ACPL-M75L Data Sheet
High-Speed 15 MBd CMOS Optocoupler
Figure 1: Typical Input Diode Forward Characteristic
Ith -INPUT THRESHOLD CURRENT-mA
10
I F -FORWARD CURRENT-mA
IF
TA=25°C
1
VF
0.1
0.01
1.2
1.3
1.4
1.5
VF -FORWARD VOLTAGE-V
1.6
4
3
2
VDD=5V
VDD=3.3V
0
20
40
60
TA -TEMPERATURE- oC
80
100
35
TPHL
25
20
TPLH
15
10
Broadcom
PWD
5
0
VDD=5V
Ta=25°C
4
1.000
0.800
I oL=20uA
0.600
5V
3.3V
0.400
0.200
0.000
-40
-20
0
20
40
60
80
100
120
5
6
7
IF – PULSE INPUT CURRENT – mA
8
6
5
4
3
2
VDD=5.0V
VDD=3.3V
1
0
-40
-20
0
20
40
60
TA -TEMPERATURE- oC
80
100
Figure 6: Typical Switching Speed vs. Pulse Input Current at
3.3V Supply Voltage
t p – PROPAGATION DELAY;
PWD-PULSE WIDTH DISTORTION – ns
t p – PROPAGATION DELAY;
PWD-PULSE WIDTH DISTORTION – ns
Figure 5: Typical Switching Speed vs. Pulse Input Current at
5V Supply Voltage
30
1.200
IDDL-LOGIC LOW OUTPUT SUPPLY CURRENT-mA
I DDH -LOGIC HIGH OUTPUT SUPPLY CURRENT -mA
5
-20
1.400
Figure 4: Typical Logic Low O/P Supply Current vs.
Temperature
6
0
-40
1.600
TA -TEMPERATURE- oC
Figure 3: Typical Logic High O/P Supply Current vs.
Temperature
1
Figure 2: Typical Input Threshold Current vs. Temperature
35
TPHL
30
25
20
TPLH
15
10
PWD
5
0
VDD =3.3V
Ta=25°C
4
5
6
7
IF – PULSE INPUT CURRENT – mA
8
AV02-0964EN
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ACPL-M75L Data Sheet
High-Speed 15 MBd CMOS Optocoupler
Propagation Delay, Pulse-Width
Distortion and Propagation Delay
Skew
Figure 7: Typical VF vs. Temperature
VF - FORWARD VOLTAGE - C
1.8
1.7
1.6
Propagation delay is a figure of merit which describes how
quickly a logic signal propagates through a system. The
propagation delay from low to high (tPLH) is the amount of
time required for an input signal to propagate to the output,
causing the output to change from low to high.
1.5
1.4
1.3
1.2
1.1
1
- 40
-20
0
20
40
60
TA - TEMPERATURE - oC
80
100
Figure 8: Recommended Printed Circuit Board Layout
Iin
50%
VDD2
C
XXX
YWW
GND1
Figure 9: Propagation Delay and Skew Waveform
IF
5
1
Similarly, the propagation delay from high to low (tPHL) is the
amount of time required for the input signal to propagate to
the output, causing the output to change from high to low
(see Figure 9).
2
4
VO
3
GND2
C = 0.01 uF to 0.1 uF
2.5 V,
CMOS
VO
t PSK
IF
50%
Application Information
Bypassing and PC Board Layout
The ACPL-M75L optocoupler is extremely easy to use.
ACPL-M75L provides CMOS logic output due to the highspeed CMOS IC technology used.
The external components required for proper operation are
the input limiting resistor and the output bypass capacitor.
Capacitor values should be between 0.01 µF and 0.1 µF.
They should be placed as close as possible to the power
supply and ground pins of the optocoupler.
2.5 V,
CMOS
VO
Figure 10: Parallel Data Transmission Example
DATA
INPUTS
CLOCK
DATA
OUTPUTS
t PSK
CLOCK
t PSK
Broadcom
AV02-0964EN
8
ACPL-M75L Data Sheet
High-Speed 15 MBd CMOS Optocoupler
clock signal are being used to clock the data; if only one
edge were used, the clock signal would need to be twice as
fast.
Pulse-width distortion (PWD) results when tPLH and tPHL differ
in value. PWD is defined as the difference between tPLH and
tPHL and often PWD determines the maximum data rate
capability of a transmission system. PWD can be expressed
in percent by dividing the PWD (in ns) by the minimum pulse
width (in ns) being transmitted. Typically, PWD on the order of
20% to 30% of the minimum pulse width is tolerable; the exact
figure depends on the particular application (RS232, RS422,
T-1, etc.).
Propagation delay skew represents the uncertainty of where
an edge might be after being sent through an optocoupler.
Figure 10 shows that there will be uncertainty in both the data
and the clock lines. It is important that these two areas of
uncertainty not overlap; otherwise the clock signal might
arrive before all of the data outputs have settled, or some of
the data outputs might start to change before the clock signal
has arrived.
Propagation delay skew, tPSK, is an important parameter to
consider in parallel data applications where synchronization
of signals on parallel data lines is a concern.
From these considerations, the absolute minimum pulse
width that can be sent through optocouplers in a parallel
application is twice tPSK. A cautious design should use a
slightly longer pulse width to ensure that any additional
uncertainty in the rest of the circuit does not cause a problem.
If the parallel data is being sent through a group of
optocouplers, differences in propagation delays will cause the
data to arrive at the outputs of the optocouplers at different
times. If this difference in propagation delays is large enough,
it will determine the maximum rate at which parallel data can
be sent through the optocouplers.
The tPSK specified optocouplers offer the advantages of
guaranteed specifications for propagation delays, pulse-width
distortion and propagation delay skew over the
recommended temperature, and power supply ranges.
Propagation delay skew is defined as the difference between
the minimum and maximum propagation delays, either tPLH or
tPHL, for any given group of optocouplers that are operating
under the same conditions (i.e., the same supply voltage,
output load, and operating temperature). As illustrated in
Figure 10, if the inputs of a group of optocouplers are
switched either ON or OFF at the same time, tPSK is the
difference between the shortest propagation delay, either tPLH
or tPHL, and the longest propagation delay, either tPLH or tPHL.
As mentioned earlier, tPSK can determine the maximum
parallel data transmission rate.
Figure 11: Connection of Peaking Capacitor (Cpeak) in Parallel
of the Input Limiting Resistor (Rlimit) to Improve Speed
Performance
C peak
R drv = 50 :
+
VDD2
R limit
Vin
0.1 μF
-
Figure 10 is the timing diagram of a typical parallel data
application with both the clock and the data lines being sent
through optocouplers. The figure shows data and clock
signals at the inputs and outputs of the optocouplers. To
obtain the maximum data transmission rate, both edges of the
GND1
VO
GND2
SHIEL
SHIELD
Figure 12: Improvement of tp and PWD with Added 100 pF Peaking Capacitor in Parallel of Input Limiting Resistor
35
40
t PHL
t PHL
35
30
t PLH
25
With peaking cap
Without peaking cap
t PLH
20
t PLH
30
25
t PLH
20
15
15
t PHL
10
5
5
0
0
-40
-20
0
20
40
60
80
(i) VDD = 5V, Cpeak = 100 pF, Rlimit = 530Ω
Broadcom
With peaking cap
Without peaking cap
t PHL
10
|PWD|
100
|PWD|
-40
-20
0
20
40
60
80
100
(ii) VDD = 3.3V, Cpeak = 100 pF, Rlimit = 250Ω
AV02-0964EN
9
ACPL-M75L Data Sheet
High-Speed 15 MBd CMOS Optocoupler
Powering Sequence
VDD needs to achieve a minimum level of 3V before
powering up the output connecting component.
Input Limiting Resistors
ACPL-M75L is direct current driven (Figure 8), and thus
eliminate the need for input power supply. To limit the
amount of current flowing through the LED, it is
recommended that a 530Ω resistor is connected in series
with anode of LED (i.e., Pin 1 for ACPL-M75L) at 5V input
signal. At 3.3V input signal, it is recommended to connect
250Ω resistor in series with anode of LED. The
recommended limiting resistors is based on the assumption
that the driver output impedence is 50Ω (as shown in
Figure 11).
Speed Improvement
A peaking capacitor can be placed across the input current
limit resistor (Figure 11) to achieve enhanced speed
performance. The value of the peaking cap is dependent to
the rise and fall time of the input signal and supply voltages
and LED input driving current (IF). Figure 12 shows
significant improvement of propagation delay and pulse
width distortion with added peak capacitor at driving current
of 6 mA for both 3.3V and 5V power supply.
Common Mode Rejection for
ACPL-M75L
Figure 13 shows the recommended drive circuit for the
ACPL-M75L for optimal common-mode rejection
performance.
Two LED-current setting resistors are used instead of one.
This is to balance the common mode impedance at LED
anode and cathode. Common-mode transients can
capacitively couple from the LED anode (or cathode) to the
output-side ground causing current to be shunted away
from the LED (which can be bad if the LED is on) or
conversely cause current to be injected into the LED (bad if
the LED is meant to be off). Figure 14 shows the parasitic
capacitances which exists between LED anode/cathode
and output ground (CLA and CLC). Also shown in Figure 14
on the input side is an AC-equivalent circuit.
Table 1 indicates the directions of ILP and ILN flow
depending on the direction of the common-mode transient.
For transients occurring when the LED is on, common-mode
rejection (CML, since the output is in the low state) depends
upon the amount of LED current drive (IF). For conditions
where IF is close to the switching threshold (ITH), CML also
depends on the extent that ILP and ILN balance each other.
In other words, any condition where common-mode
transients cause a momentary decrease in IF (that is, when
dVCM/dt > 0 and |IFP| > |IFN|, refer to Table 1) will cause
common-mode failure for transients that are fast enough.
Likewise for common-mode transients that occur when the
LED is off (i.e., CMH, since the output is high), if an
imbalance between ILP and ILN results in a transient IF equal
to or greater than the switching threshold of the optocoupler,
the transient signal might cause the output to spike below
2V (which constitutes a CMH failure).
By using the recommended circuit in Figure 13, good CMR
can be achieved. The resistors recommended in Figure 13
include both the output impedence of the logic driver circuit
and the external limiting resistor. The balanced ILED-setting
resistors help equalize the common-mode voltage change
at anode and cathode to reduce the amount by which ILED
is modulated from transient coupling through CLA and CLC.
Table 1: Effects of Common Mode Pulse Direction on Transient ILED
If dVCM/dt Is:
Then ILP Flows:
And ILN Flows:
If |ILP| < |ILN|,
LED IF Current
Is Momentarily:
If |ILP| > |ILN|,
LED IF Current
Is Momentarily:
positive (>0)
away from LED
anode through CLA
away from LED
cathode through CLC
increased
decreased
negative (
