ACPL-W456-000E

ACPL-P456 and ACPL-W456 High CMR Intelligent Power Module and Gate Drive Interface Optocoupler Data Sheet Description Features The ACPL-P456 and ACPL-W456 contain a GaAsP LED optically coupled to an integrated high-gain photo detector. Minimized propagation delay difference between devices make these optocouplers excellent solutions for improving inverter efficiency through reduced switching dead time. Specifications and performance plots are given for typical IPM applications.  ANODE 1 6 VCC N.C. 2 5 VO SHIELD     Functional Diagram CATHODE 3   4 Ground Note: A 0.1 μF bypass capacitor must be connected between pins 4 and 6. Truth Table (Positive Logic) Specifications  LED V0 ON LOW  OFF HIGH  Applications     IPM Isolation Isolated IGBT/MOSFET Gate Drive AC and Brushless DC Motor Drives Industrial Inverters Performance Specified for Common IPM Applications Over Industrial Temperature Range Short Maximum Propagation Delays Minimized Pulse Width Distortion (PWD) Very High Common Mode Rejection (CMR) High CTR Available in Stretched SO-6 Package with 8 mm creepage and clearance Safety Approval: — UL Recognized with 3750VRMS for 1 minute (5000VRMS for 1 minute for all ACPL-W456 devices and Option 020 device for ACPL-P456) per UL1577 — CSA Approved — IEC/EN/DIN EN 60747-5-5 approved with VIORM = 1140Vpeak (ACPL-W456) and VIORM = 891Vpeak (ACPL-P456) for Option 060   Wide Operating Temperature Range: –40°C to 100°C Maximum Propagation Delay tPHL = 400 ns, tPLH = 490 ns Maximum Pulse Width Distortion (PWD) = 450 ns 15 kV/μs Minimum Common Mode Rejection (CMR) at VCM = 1500V CTR > 44% at IF = 10 mA CAUTION Broadcom -1- It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. ACPL-P456 and ACPL-W456 Data Sheet Ordering Information ACPL-P456 and ACPL-W456 are UL Recognized with 3750VRMS (5000VRMS for ACPL-W456) for 1 minute per UL1577 and are approved under CSA Component Acceptance Notice #5, File CA 88324. Option Part Number Package Surface Mount Tape and Reel RoHS Compliant ACPL-P456 ACPL-W456 -000E X -500E X -060E -560E Stretched SO-6 Quantity 100 per tube X X X IEC/EN/DIN EN 60747-5-5 X 1000 per tube X 100 per tube X 1000 per tube To order, choose a part number from the part number column and combine with the desired option from the option column to form an ordering part number. Example 1: ACPL-P456-560E to order product of Stretched SO-6 package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval in RoHS compliant. Example 2: ACPL-P456-000E to order product of Stretched SO-6 package in tube packaging and RoHS compliant. Option data sheets are available. Contact your Broadcom sales representative or authorized distributor for information. Solder Reflow Profile The recommended reflow profile is per JEDEC Standard, J-STD-020 (latest revision). Non-halide flux should be used. Regulatory Information The ACPL-P456 and ACPL-W456 are approved by the following organizations:    IEC/EN/DIN EN 60747-5-5 (Option 060 only): Approved with Maximum Working Insulation Voltage VIORM = 1140Vpeak (ACPL-W456) and VIORM = 891Vpeak (ACPL-P456). UL: Approval under UL 1577, component recognition program up to VISO = 3750VRMS (or 5000VRMS for ACPLW456). File E55361. CSA: Approval under CSA Component Acceptance Notice #5, File CA 88324. Broadcom -2- ACPL-P456 and ACPL-W456 Data Sheet Package Outline Drawings ACPL-P456 Stretched SO-6 Package (7 mm Clearance) 4.580 0.381 ±0.127 0.015 ±0.005 0 +0.010 0.180 - 0.000 1.27 BSG 0.050 10.7 0.421 1.27 0.050 7.62 0.300 6.81 0.268 0.45 0.018 45° 2.16 0.085 3.180 ±0.127 0.125 ±0.005 1.590 ±0.127 0.063 ±0.005 7° 0.76 0.030 7° 7° 7° 0.20 ±0.10 0.008 ±0.004 0.254 ±0.050 0.010 ±0.002 Floating Lead Protusions max. 0.25 [0.01] 5 NOM. 1±0.250 0.040 ±0.010 Dimensions in Millimeters [ Inches ] Lead Coplanarity= 0.1mm [0.004 Inches ] 9.7 ±0.250 0 382 0 010 ACPL-W456 Stretched SO-6 Package (8 mm Clearance) 0.381 ±0.127 0.015 ±0.005 1 12.650 0.498 0.760 0.030 6 2 5 3 4 7.62 [0.300] +0.127 6.807 -0.000 +0.005 0.268 - 0.000 0.45 0.018 +0.254 0 +0.010 0.180 - 0.000 *4.580 1.27 BSG 0.050 7° 45° 1.905 0.075 1.270 0.050 1.590 ±0.127 0.063 ±0.005 3.180 ±0.127 0.125 ±0.005 0.20 ±0.10 0.008 ±0.004 7° 0.750 ±0.250 [0.0295 ±0.010] 35° NOM. 11.500 ±0.25 0.453 ±0.010 0.254 ±0.050 0.010 ±0.002 Floating Lead protusion max. = 0.25 mm [0.01 inches] Lead Coplanarity = 0.1 mm [0.004 inches] Dimensions in millimeters [inches] *Total Package Width = 4.834 ±0.254 mm (inclusive of mold flash) Broadcom -3- 7° 7° ACPL-P456 and ACPL-W456 Data Sheet IEC/EN/DIN EN 60747-5-5 Insulation Characteristics (Option 060) Description Symbol ACPL-W456 ACPL-P456 I– IV I – IV I – IV I – IV I – III I – IV I – IV I – III I – III Installation Classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤ 150VRMS for rated mains voltage ≤ 300VRMS for rated mains voltage ≤ 450VRMS for rated mains voltage ≤ 600VRMS for rated mains voltage ≤ 1000VRMS Climatic Classification Unit 55/100/21 Pollution Degree (DIN VDE 0110/39) 2 VIORM 1140 891 Vpeak Input to Output Test Voltage, Method ba VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC VPR 2138 1671 Vpeak Input to Output Test Voltage, Method aa VIORM x 1.5 = VPR, Type and Sample Test, tm = 10 sec, VPR 1824 1425 Vpeak VIOTM 8000 6000 Vpeak Maximum Working Insulation Voltage Partial Discharge < 5 pC Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) Safety-limiting values – maximum values allowed in the event of a failure TS 175 °C Input Current IS, INPUT 230 mA Output Power PS, OUTPUT 600 mW RS >109 Ω Case Temperature Insulation Resistance at TS, VIO = 500V a. Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under the Product Safety Regulations section, (IEC/EN/DIN EN 60747-5-5), for a detailed description of Method a and Method b partial discharge test profiles. Insulation and Safety Related Specifications Parameter Symbol ACPL-P456 ACPL-W456 Unit Condition Minimum External Air Gap (External Clearance) L(101) 7.0 8.0 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (External Creepage) L(102) 8.0 8.0 mm Measured from input terminals to output terminals, shortest distance path along body. Minimum Internal Plastic Gap (Internal Clearance) 0.08 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. Minimum Internal Tracking (Internal Creepage) N/A mm Measured from input terminals to output terminals, along internal cavity. >175 V Tracking Resistance (Comparative Tracking Index) Isolation Group CTI IIIa Broadcom -4- DIN IEC 112/VDE 0303 Part 1. Material Group (DIN VDE 0110, 1/89, Table 1). ACPL-P456 and ACPL-W456 Data Sheet Absolute Maximum Ratings Parameter Symbol Min. Max. Unit Storage Temperature TS –55 +125 °C Operating Temperature TA –40 +100 °C Average Input Current IF(AVG) 25 mA 1 Peak Input Current (50% duty cycle, 3.0V). 12. Common mode transient immunity in a Logic Low level is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in a Logic Low state (i.e., VO < 1.0V). 13. Pulse Width Distortion (PWD) is defi ned as |tPHL – tPLH| for any given device. Broadcom -7- ACPL-P456 and ACPL-W456 Data Sheet Figure 1 Typical Transfer Characteristics Figure 2 Normalized Output Current vs. Temperature 1.05 NORMALIZED OUTPUT CURRENT IO – OUTPUT CURRENT – mA 10 8 6 4 VO = 0.6V 2 0 100°C 25°C -40°C 0 5 10 15 IF – FORWARD CURRENT – mA IF = 10 mA VO = 0.6V 0.85 -20 0 20 40 60 TA – TEMPERATURE – °C 1000 VF = 0.8V VCC = VO = 4.5V OR 30V 1.5 4.5V 30V 1.0 0.5 -20 0 20 40 60 80 100 TA = 25°C IF IF – FORWARD CURRENT – mA IOH – HIGH LEVEL OUTPUT CURRENT – μA 0.90 Figure 4 Input Current vs. Forward Voltage 2.0 0 -40 0.95 0.80 -40 20 Figure 3 High Level Output Current vs. Temperature 1.00 80 100 10 1.0 0.1 0.01 0.001 1.10 100 + VF - 1.20 1.30 1.40 1.50 1.60 VF – FORWARD VOLTAGE – VOLTS TA – TEMPERATURE – °C Figure 5 Propagation Delay Test Circuit IF(ON) = 10 mA 1 + - If 6 2 5 3 4 SHIELD VOUT + C L* VCC = 15 tf VO tr 90% 90% 10% 10% VTHHL * TOTAL LOAD CAPACITANCE VTHLH tPHL Broadcom -8- tPLH ACPL-P456 and ACPL-W456 Data Sheet Figure 6 CMR Test Circuit and Waveforms VCM IF B A + 1 6 2 5 3 4 SHIELD VOUT + 100 pF * V = CM VCC = 15 OV * 100 pF TOTAL CAPACITANCE VFF - VO + - VCC SWITCH AT A: IF = 0 mA VCM = 1500V VO VOL SWITCH AT B: IF = 10 mA Figure 7 Propagation Delay with External 20 kΩ RL vs. Temp. Figure 8 Propagation Delay vs. Load Resistance 800 IF = 10 mA VCC = 15V CL = 100 pF RL = 20 kΩ 400 300 tP – PROPAGATION DELAY – ns tP – PROPAGATION DELAY – ns 500 tPLH tPHL 200 100 -40 -20 0 20 40 60 TA – TEMPERATURE – °C 80 100 Figure 9 Propagation Delay vs. Load Capacitance 1000 tPLH tPHL 200 10 20 30 RL – LOAD RESISTANCE – kΩ 1400 tPLH tPHL 800 400 40 50 Figure 10 Propagation Delay vs. Supply Voltage IF = 10 mA VCC = 15V RL = 20 kΩ TA = 25°C 1200 600 0 tP – PROPAGATION DELAY – ns tP – PROPAGATION DELAY – n 1400 IF = 10 mA VCC = 15V CL = 100 pF TA = 25°C 600 400 200 IF = 10 mA CL = 100 pF RL = 20 kΩ TA = 25°C 1200 1000 800 tPLH tPHL 600 400 200 0 0 0 100 200 300 400 CL – LOAD CAPACITANCE – pF 5 500 Broadcom -9- 10 15 20 VCC – SUPPLY VOLTAGE – V 25 30 ACPL-P456 and ACPL-W456 Data Sheet Figure 13 Optocoupler Input to Output Capacitance Model for Unshielded Optocouplers Figure 11 Propagation Delay vs. Input Current tP – PROPAGATION DELAY – ns 500 VCC = 15V CL = 100 pF RL = 20 kΩ TA = 25°C 400 tPLH tPHL 1 CLEDP 6 2 300 3 0 5 15 10 IF – FORWARD LED CURRENT – mA 20 Figure 14 Optocoupler Input to Output Capacitance Model for Shielded Optocouplers Applications Information LED Drive Circuit Considerations For Ultra High CMR Performance 1 Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure 13. The ACPL-P456/W456 improve CMR performance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. However, this shield does not eliminate the capacitive coupling between the LED and the optocoupler output pin and output ground as shown in Figure 14. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off) during common mode transients. For example, the recommended application circuit (Figure 12), can achieve 15 kV/μs CMR while minimizing component complexity. Note that a CMOS gate is recommended in Figure 12 to keep the LED off when the gate is in the high state. Figure 12 Recommended LED Drive Circuit +5V 1 6 2 5 3 4 VOUT + CL* CMOS SHIELD 4 CLEDN Another cause of CMR failure for a shielded optocoupler is direct coupling to the optocoupler output pins through CLEDO1 in Figure 14. Many factors influence the effect and magnitude of the direct coupling including: the position of the LED current setting resistor and the value of the capacitor at the optocoupler output (CL). 200 100 5 * 100 pF TOTAL CAPACITANCE VCC = 15V CLEDP CLED01 2 3 6 5 CLEDN SHIELD 4 CMR With The LED On (CMRL) A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. The recommended minimum LED current of 10 mA provides adequate margin over the maximum ITH of 4.0 mA (see Figure 1) to achieve 15 kV/μs CMR. The placement of the LED current setting resistor effects the ability of the drive circuit to keep the LED on during transients and interacts with the direct coupling to the optocoupler output. For example, the LED resistor in Figure 15 is connected to the anode. Figure 16 shows the AC equivalent circuit for Figure 15 during common mode transients. During a +dVCM/dt in Figure 16, the current available at the LED anode (Itotal) is limited by the series resistor. The LED current (IF) is reduced from its DC value by an amount equal to the current that flows through CLEDP and CLEDO1. The situation is made worse because the current through CLEDO1 has the effect of trying to pull the output high (toward a CMR failure) at the same time the LED current is being reduced. For this reason, the recommended LED drive circuit (Figure 12) places the current setting resistor in series with the LED cathode. Figure 17 is the AC equivalent circuit for Figure 12 during common mode Broadcom - 10 - ACPL-P456 and ACPL-W456 Data Sheet transients. In this case, the LED current is not reduced during a +dVCM/dt transient because the current fl owing through the package capacitance is supplied by the power supply. During a -dVCM/dt transient, however, the LED current is reduced by the amount of current flowing through CLEDN. But, better CMR performance is achieved since the current fl owing in CLEDO1 during a negative transient acts to keep the output low. Figure 15 LED Drive Circuit with Resistor Connected to LED Anode (Not Recommended) +5V 1 6 2 5 VOUT + - VCC = 15V CL* 3 4 SHIELD CMOS * 100 pF TOTAL CAPACITANCE Figure 16 AC Equivalent Circuit for Figure 15 During Common Mode Transients ITOTAL* 300 Ω ICLEDP 1 ICLED01 IF 6 CLED01 2 20 kΩ 5 VOUT 100pF 3 CLEDN SHIELD 4 * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW DURING + dVCM /dt CMR With The LED Off (CMRH) A high CMR LED drive circuit must keep the LED off (VF ≤ VF(OFF)) during common mode transients. For example, during a +dVCM/dt transient in Figure 17, the current flowing through CLEDN is supplied by the parallel combination of the LED and series resistor. As long as the voltage developed across the resistor is less than VF(OFF) the LED will remain off and no common mode failure will occur. Even if the LED momentarily turns on, the 100 pF capacitor from pins 5-4 will keep the output from dipping below the threshold. The recommended LED drive circuit (Figure 12) provides about 10V of margin between the lowest optocoupler output voltage and a 3V IPM threshold during a 15 kV/μs transient with VCM = 1500V. Additional margin can be obtained by adding a diode in parallel with the resistor, as shown by the dashed line connection in Figure 17, to clamp the voltage across the LED below VF(OFF). Since the open collector drive circuit, shown in Figure 18, cannot keep the LED off during a +dVCM/dt transient, it is not desirable for applications requiring ultra high CMRH performance. Figure 19 is the AC equivalent circuit for Figure 18 during common mode transients. Essentially all the current flowing through CLEDN during a +dVCM/dt transient must be supplied by the LED. CMRH failures can occur at dv/dt rates where the current through the LED and CLEDN exceeds the input threshold. Figure 20 is an alternative drive circuit which does achieve ultra high CMR performance by shunting the LED in the off state. + - Figure 18 Not Recommended Open Collector LED Drive Circuit VCM +5V Figure 17 AC Equivalent Circuit for Figure 12 During Common Mode Transients 1 1 6 2 5 3 SHIELD 4 Q1 CLEDP 6 CLED01 + VR**- 2 5 VOUT 100 pF 3 ICLEDN* CLEDN SHIELD 4 Figure 19 AC Equivalent Circuit for Figure 18 During Common Mode Transients * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW FOR + dVCM /dt TRANSIENTS. ** OPTIONAL CLAMPING DIODE FOR IMPROVED CMH PERFORMANCE. V R < VF (OFF) DURING + dVCM /dt 1 CLEDP 6 CLED01 + - 2 20 5 VOUT 100 pF Q1 3 VCM ICLEDN* CLEDN SHIELD 4 + - * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW FOR + dVCM /dt TRANSIENTS. VCM Broadcom - 11 - ACPL-P456 and ACPL-W456 Data Sheet Figure 20 Recommended LED Drive Circuit for Ultra High CMR +5V 1 6 2 5 3 4 SHIELD IPM Dead Time and Propagation Delay Specifications The ACPL-P456/W456 includes a Propagation Delay Difference specification intended to help designers minimize “dead time” in their power inverter designs. Dead time is the time period during which both the high and low side power transistors (Q1 and Q2 in Figure 21) are off. Any overlap in Q1 and Q2 conduction will result in large currents flowing through the power devices between the high and low voltage motor rails. To minimize dead time the designer must consider the propagation delay characteristics of the optocoupler as well as the characteristics of the IPM IGBT gate drive circuit. Considering only the delay characteristics of the optocoupler (the characteristics of the IPM IGBT gate drive circuit can be analyzed in the same way) it is important to know the minimum and maximum turn on (tPHL) and turn-off (tPLH) propagation delay specifications, preferably over the desired operating temperature range. The limiting case of zero dead time occurs when the input to Q1 turns off at the same time that the input to Q2 turns on. This case determines the minimum delay between LED1 turn-off and LED2 turn-on, which is related to the worst case optocoupler propagation delay waveforms, as shown in Figure 22. A minimum dead time of zero is achieved in Figure 22 when the signal to turn on LED2 is delayed by (tPLH max – tPHL min) from the LED1 turn off. Note that the propagation delays used to calculate PDD are taken at equal temperatures since the optocouplers under consideration are typically mounted in close proximity to each other. (Specifically, previous equation are not the same as the tPLH max and tPHL min, over the full operating temperature range, specified in the data sheet.) This delay is the maximum value for the propagation delay difference specification which is specified at 450 ns for the ACPL-P456/W456 over an operating temperature range of –40°C to +100°C. Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time occurs in the highly unlikely case where one optocoupler with the fastest tPLH and another with the slowest tPHL are in the same inverter leg. The maximum dead time in this case becomes the sum of the spread in the tPLH and tPHL propagation delays as shown in Figure 23. The maximum dead time is also equivalent to the difference between the maximum and minimum propagation delay difference specifications. The maximum dead time (due to the optocouplers) for the ACPL-P456/W456 are 600 ns (= 450 ns – (–150 ns)) over an operating temperature range of –40°C to +100°C. Figure 21 Typical Application Circuit IPM +HV ILED1 +5V 310 1 6 2 5 3 CMOS SHIELD VCC1 VOUT1 4 M ILED2 +5V 1 6 2 5 VCC2 20 310 CMOS 3 SHIELD 4 VOUT2 ACPL-P/W456 --HV ACPL-P/W456 ACPL-P/W456 ACPL-P/W456 ACPL-P/W456 Broadcom - 12 - ACPL-P456 and ACPL-W456 Data Sheet Figure 22 Minimum LED Skew for Zero Dead Time Figure 23 Waveforms for Deadtime Calculation ILED1 ILED1 VOUT1 VOUT2 Q1 OFF Q1 ON Q2 OFF VOUT1 VOUT2 Q1 OFF Q1 ON Q2 OFF Q2 ON Q2 ON ILED2 ILED2 tPLH MIN. tPLH MAX. tPLH MAX. tPHL MIN. PDD* MAX. PDD* MAX. = (tPLH-tPHL) MAX. = tPLH MAX. - tPHL MIN. tPHL MIN. tPHL MAX. MAX. DEAD TIME *PDD = PROPAGATION DELAY DIFFERENCE MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) NOTE: THE PROPAGATION DELAYS USED TO CALCULATE PDD ARE TAKEN AT EQUAL TEMPERATURES. = (tPLH MAX. - tPLH MIN.) + (tPHL MAX. - tPHL MIN.) = (tPLH MAX. - tPHL MIN.) - (tPLH MIN. - tPHL MAX.) = PDD* MAX. - PDD* MIN. *PDD = PROPAGATION DELAY DIFFERENCE NOTE: THE PROPAGATION DELAYS USED TO CALCULATE THE MAXIMUM DEAD TIME ARE TAKEN AT EQUAL TEMPERATURES. Broadcom - 13 - For product information and a complete list of distributors, please go to our web site: www.broadcom.com. Broadcom, the pulse logo, Connecting everything, Avago Technologies, Avago, and the A logo are among the trademarks of Broadcom and/or its affiliates in the United States, certain other countries and/or the EU. Copyright © 2017 by Broadcom. All Rights Reserved. The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries. For more information, please visit www.broadcom.com. Broadcom reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by Broadcom is believed to be accurate and reliable. However, Broadcom does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AV02-1306EN – June 19, 2017