ACPL-W70L-000E

ACPL-W70L-000E and ACPL-K73L-000E Single-Channel and Dual-Channel High-Speed 15-MBd CMOS Optocoupler with Glitch-Free Power-Up Feature Data Sheet Description Features The ACPL-W70L (single-channel) and ACPL-K73L (dual-channel) are 15-MBd CMOS optocouplers in SSOIC-6 and SSOIC-8 package respectively. The optocouplers utilize the latest CMOS IC technology to achieve outstanding performance with very low power consumption. Basic building blocks of ACPL-W70L and ACPL-K73L are high-speed LEDs and CMOS detector ICs. Each detector incorporates an integrated photodiode, a high-speed transimpedance amplifier, and a voltage comparator with an output driver. Features         Component Image  ACPL-W70L 6 VDD Anode 1 +3.3V and 5V CMOS compatibility 25 ns max pulse width distortion 55 ns max propagation delay 40 ns max propagation delay skew High speed: 15 MBd min 10 kV/μs minimum common-mode rejection –40 to +105°C temperature range Glitch-free power-up feature Safety and regulatory approvals: — UL recognized: 5000 V rms for 1 min. per UL 1577 — CSA component acceptance Notice #5 — IEC/EN/DIN EN 60747-5-5 approval for Reinforced Insulation 5 Vo NC* 2 Applications Cathode 3 4 GND SHIELD   ACPL-K73L Anode1 1 8 VDD 7 Vo 1 Cathode1 2 Cathode2 3    Digital field bus isolation: — CANBus, RS485, USB Multiplexed data transmission Computer peripheral interface Microprocessor system interface DC/DC converter 6 Vo 2 Anode2 4 5 GND SHIELD Truth Table LED ON OFF VO, Output CAUTION H L A 0.1-μF bypass capacitor must be connected between pins VDD and GND. Broadcom -1- It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation that may be induced by ESD. ACPL-W70L-000E and ACPL-K73L-000E Data Sheet Ordering Information Ordering Information ACPL-W70L and ACPL-K73L are UL Recognized with 5000 Vrms for 1 minute per UL1577. Part Number Option RoHS Compliant Package Surface Mount ACPL-W70L -000E SSO-6 X -500E X -060E X -560E ACPL-K73L -000E X SSO-8 Tape & Reel X X X -500E X -060E X -560E X X X UL 5000 Vrms/ 1 Minute Rating IEC/EN/DIN EN 60747-5-5 Quantity X 100 per tube X 1000 per reel X X 100 per tube X X 1000 per reel X 80 per tube X 1000 per reel X X 80 per tube X X 1000 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example: ACPL-W70L-500E to order product of stretched SO-6 package in Tape and Reel packaging in RoHS compliant. Option data sheets are available. Contact your Broadcom sales representative or authorized distributor for information. Broadcom -2- ACPL-W70L-000E and ACPL-K73L-000E Data Sheet Package Dimensions Package Dimensions ACPL-W70L (Stretched SO-6 Package) LAND PATTERN RECOMMENDATION 12.65 (0.498) 1.27 (0.050) BSG 0.381 0.127 (0.015 0.005) 1 6 2 5 3 4 +0.127 6.807 0 (0.268 +0.005) - 0.000 0.45 (0.018) 7 45 +0.254 4.580 0 +0.010 (0.180 ) - 0.000 0.76 (0.030) 1.91 (0.075) 1.590 0.127 (0.063 0.005) 7 3.180 0.127 (0.125 0.005) 0.20 0.10 (0.008 0.004) 0.750 0.250 (0.0295 0.010) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.1 mm (0.004 INCHES). 11.50 0.250 (0.453 0.010) ACPL-K73L (Stretched S0-8 Package) LAND PATTERN RECOMMENDATION 12.650 (0.5) 1.270 (0.050) BSG 0.381 0.13 (0.015 0.005) 0.450 (0.018) 1 8 2 7 3 6 4 5 7 45 1.905 (0.1) 1.590 0.127 (0.063 0.005) 7 3.180 0.127 (0.125 0.005) 0.200 0.100 (0.008 0.004) 0.750 0.250 (0.0295 0.010) +0.25 5.850 0 +0.010 (0.230 ) - 0.000 6.807 0.127 (0.268 0.005) 11.5 0.250 (0.453 0.010) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.1 mm (0.004 INCHES). Broadcom -3- ACPL-W70L-000E and ACPL-K73L-000E Data Sheet Solder Reflow Profile Solder Reflow Profile The recommended reflow soldering conditions are per JEDEC Standard J-STD-020 (latest revision). Non-halide flux should be used. Regulatory Information The ACPL-W70L and ACPL-K73L are approved by the following organizations: UL Recognized under UL 1577, component recognition program, File E55361. CSA Approval under CSA Component Acceptance Notice #5, File CA 88324. IEC/EN/DIN EN 60747-5-5 Approved. Insulation and Safety Related Specifications Parameter Symbol Value Unit Minimum External Air Gap (Clearance) L(101) 8.0 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (Creepage) L(102) 8.0 mm Measured from input terminals to output terminals, shortest distance path along body. 0.08 mm Insulation thickness between emitter and detector; also known as distance through insulation. >175 V Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI IIIa Conditions DIN IEC 112/VDE 0303 Part 1. Material Group (DIN VDE 0110, 1/89, Table 1.) All Avago Technologies data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. There are recommended techniques such as grooves and ribs that can be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances also change depending on factors such as pollution degree and insulation level. Broadcom -4- IEC/EN/DIN EN 60747-5-5 Insulation Characteristicsa ACPL-W70L-000E and ACPL-K73L-000E Data Sheet IEC/EN/DIN EN 60747-5-5 Insulation Characteristicsa Descriptiona Symbol Option 060 Unit Installation Classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤ 150 Vrmsa I – IV for rated mains voltage ≤ 300 Vrms I – IV for rated mains voltage ≤ 450 Vrms I – IV for rated mains voltage ≤ 600 Vrms I – IV for rated mains voltage ≤ 1000 Vrms I – III 55/105/21 Climatic Classification 2 Pollution Degree (DIN VDE 0110/1.89) Maximum Working Insulation Voltage Input to Output Test Voltage, Method bb VIORM 1140 Vpeak VPR 2137 Vpeak VPR 1824 Vpeak VIOTM 8000 Vpeak TS 175 °C IS, INPUT 230 mA PS, OUTPUT 600 mW RIO >109 Ω VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC Input to Output Test Voltage, Method ab VIORM x 1.6 = VPR, Type and Sample Test, tm = 10 sec, Partial Discharge < 5 pC Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) Safety-limiting Values – Maximum Values Allowed in the Event of a Failure Case Temperature Input Currentb Output Powerb Insulation Resistance at TS, VIO = 500V a. Isolation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits in application. Surface mount classification is class A in accordance with CECCOO802. b. Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section IEC/EN/DIN EN 60747-5-5, for a detailed description of Method a and Method b partial discharge test profiles. Note: These optocouplers are suitable for safe electrical isolation only within the safety limit data. Maintenance of the safety data must be ensured by means of protective circuits. The surface mount classification is Class A in accordance with CECC 00802. Broadcom -5- ACPL-W70L-000E and ACPL-K73L-000E Data Sheet Absolute Maximum Ratings Absolute Maximum Ratings Parameter Symbol Min Max Unit Storage Temperature TS –55 +125 °C Ambient Operating Temperature TA –40 +105 °C Supply Voltage VDD 0 6 V Output Voltage VO –0.5 VDD + 0.5 V Average Forward Input Current IF — 10 mA Average Output Current Io — 10 mA Lead Solder Temperature 260°C for 10 sec, 1.6 mm below seating plane Solder Reflow Temperature Profile See Solder Reflow Profile section. Recommended Operating Conditions Parameter Symbol Min Max Unit TA –40 +105 °C VDD 4.5 5.5 V Ambient Operating Temperature Supply Voltages 3.0 3.6 V Input Current (ON) IF 4 8 mA Supply Voltage Slew Ratea SR 0.5 500 V/ms a. Slew rate of supply voltage ramping is recommended to ensure no glitch more than 1V to appear at the output pin. Electrical Specifications Over recommended temperature (TA = –40°C to +105°C), 3.0V ≤ VDD ≤ 3.6V and 4.5V ≤ VDD ≤ 5.5V. All typical specifications are at TA = +25°C, VDD = +3.3V. Parameter Input Forward Voltage Symbol Part Number VF Min Typ Max Unit Test Conditions 1.2 1.5 1.85 V IF = 6 mA Input Reverse Breakdown Voltage BVR 5.0 — — V IR = 10 μA Logic High Output Voltage VOH VDD – 1 VDD – 0.3 — V IF = 6 mA, IO = –4 mA, VDD = 3.3V VDD – 1 VDD – 0.2 — V IF = 6 mA, IO = –4 mA, VDD = 5V — 0.2 0.8 V IF = 0 mA, IO = 4 mA, VDD = 3.3V — 0.2 0.8 V IF = 0 mA, IO = 4 mA, VDD = 5V — 1 3 mA IOL = 20 μA ACPL-W70L — 4.1 6.5 mA IF = 0 mA ACPL-K73L — 8.2 13 mA IF = 0 mA ACPL-W70L — 3.8 6 mA IF = 6 mA ACPL-K73L — 7.6 12 mA IF = 6 mA Logic Low Output Voltage VOL Input Threshold Current ITH Logic Low Output Supply Current IDDL Logic Low Output Supply Current IDDH Broadcom -6- ACPL-W70L-000E and ACPL-K73L-000E Data Sheet Switching Specifications Switching Specifications Over recommended temperature (TA = –40°C to +105°C), 3.0V ≤ VDD ≤ 3.6V and 4.5V ≤ VDD ≤ 5.5V. All typical specifications are at TA = +25°C, VDD = +3.3V. Parameter Symbol Min Typ Max Unit tPHL — 23 55 ns Propagation Delay Time to Logic Low Outputa Test Conditions IF = 6 mA, CL= 15 pF CMOS Signal Levels tPLH Propagation Delay Time to Logic High Outputa — 27 55 ns IF = 6 mA, CL= 15 pF CMOS Signal Levels tPW 66.7 — — ns |PWD| 0 4 25 ns Pulse Width Pulse Width Distortionb — IF = 6 mA, CL = 15 pF CMOS Signal Levels tPSK Propagation Delay Skewc — — 40 ns IF = 6 mA, CL = 15 pF CMOS Signal Levels Output Rise Time (10% to 90%) tR — 3.5 — ns IF = 6 mA, CL = 15 pF CMOS Signal Levels Output Fall Time (90% to 10%) — tF 3.5 — ns IF = 0 mA, CL = 15 pF CMOS Signal Levels Common-Mode Transient Immunity at Logic High Outputd |CMH| 10 15 — kV/μs VCM = 1000V, TA = 25°C, IF = 6 mA Common-Mode Transient Immunity at Logic Low Outpute |CML| 10 15 — kV/μs VCM = 1000V, TA = 25°C, IF = 0 mA a. tPHL propagation delay is measured from the 50% level on the rising edge of the input pulse to the 50% level on the falling edge of the VO signal. tPLH propagation delay is measured from the 50% level on the falling edge of the input pulse to the 50% level on the rising edge of the VO signal. b. PWD is defined as |tPHL – tPLH|. c. tPSK is equal to the magnitude of the worst-case difference in tPHL and/or tPLH that is seen between units at any given temperature within the recommended operating conditions. d. CMH is the maximum tolerable rate of rise of the common-mode voltage to assure that the output remains in a high logic state. e. CML is the maximum tolerable rate of fall of the common-mode voltage to assure that the output remains in a low logic state. Package Characteristics All typical at TA = 25°C. Parameter Input-Output Insulation Symbol Min Typ Max Unit II-O — — 1.0 μA Test Conditions 45% RH, t = 5 sec VI-O = 3 kV dc, TA = 25°C Input-Output Momentary Withstand Voltage VISO 5000 — — Vrms Input-Output Resistance R I-O — 10 12 — Ω V I-O = 500V dc Input-Output Capacitance C I-O — 0.6 — pF f = 1 MHz, TA = 25°C Broadcom -7- RH ≤ 50%, t = 1 min., TA = 25°C ACPL-W70L-000E and ACPL-K73L-000E Data Sheet Package Characteristics Figure 1 Typical Input Diode Forward Characteristic Figure 2 Typical Input Threshold Current vs. Temperature 10 1.600 Ith - INPUT THRESHOLD CURRENT-mA IF - FORWARD CURRENT-mA IF TA=25°C 1 VF 0.1 0.01 1.2 1.3 1.4 1.5 VF - FORWARD VOLTAGE-V IDDL -LOGIC LOW OUTPUT SUPPLY CURRENT-mA 6 4 VDD=5V VDD=3.3V 0 0 20 40 60 T A -TEMPERATURE- oC 80 100 tp – PROPAGATION DELAY; PWD-Pulse Width h Distortion – ns 0.200 -20 0 20 40 60 T A-TEMPERATURE- oC 80 100 120 12 10 8 6 4 VDD=5V VDD=3.3V 2 0 -20 0 20 40 60 T A-TEMPERATURE- oC 80 100 Figure 6 Typical Switching Speed vs. Pulse Input Current at 3.3V Supply Voltage 35 35 t PLH CH2 t PHL CH1 25 20 15 5V 3.3V 0.400 -40 Figure 5 Typical Switching Speed vs. Pulse Input Current at 5V Supply Voltage 30 I OL =20uA 0.600 tp – PROPAGATION DELAY; PWD-Pulse Width Distortion – ns I DDH -LOGIC HIGH OUTPUT SUPPLY CURRENT-mA 8 -20 0.800 Figure 4 Typical Logic Low Output Supply Current vs. Temperature for Dual Channel (ACPL-K73L) 10 -40 1.000 -40 12 2 1.200 0.000 1.6 Figure 3 Typical Logic High Output Supply Current vs. Temperature for Dual Channel (ACPL-K73L) 1.400 t PHL CH2 10 5 VDD=5V TA=25°C 0 5 4 t PLH CH1 |PWD| CH1 |PWD| CH2 6 7 8 IF – PULSE INPUT CURRENT – mA 9 10 Broadcom -8- t PLH CH2 30 t PHL CH1 25 20 15 t PLH CH1 t PHLCH2 10 |PWD| CH1 |PWD| CH2 5 VDD=5V TA=25°C 0 5 4 6 7 8 IF – PULSE INPUT CURRENT – mA 9 10 ACPL-W70L-000E and ACPL-K73L-000E Data Sheet Bypassing and PC Board Layout Propagation delay skew, tPSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it determines the maximum rate at which parallel data can be sent through the optocouplers. Figure 7 Typical VF vs. Temperature 1.8 V F FORWARD VOLTAGE-V 1.7 1.6 1.5 1.4 1.3 Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either tPLH or tPHL, for any given group of optocouplers that are operating under the same conditions (i.e., the same supply voltage, output load, and operating temperature). As illustrated in Figure 10, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, tPSK is the difference between the shortest propagation delay, either tPHL or tPHL, and the longest propagation delay, either tPHL or tPHL. As mentioned earlier, tPSK can determine the maximum parallel data transmission rate. 1.2 1.1 1 -40 -20 0 20 40 60 T A-TEMPERATURE- o C 80 100 Bypassing and PC Board Layout The ACPL-W70L and ACPL-K73L optocouplers are extremely easy to use. ACPL-W70L and ACPL-K73L provide CMOS logic output due to the high-speed CMOS IC technology used. The external components required for proper operation are the input limiting resistor and the output bypass capacitor. Capacitor values should be between 0.01 μF and 0.1 μF. For each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm. Propagation Delay, Pulse-Width Distortion, and Propagation Delay Skew Propagation delay is a figure of merit that describes how quickly a logic signal propagates through a system. The propagation delay from low to high (tPLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (tPHL) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see Figure 9). Pulse-width distortion (PWD) results when tPLH and tPHL differ in value. PWD is defined as the difference between tPLH and tPHL. This parameter determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20% to 30% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS232, RS422, T-1, etc.). Figure 10 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 10 shows that there is uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap; otherwise, the clock signal might arrive before all of the data outputs have settled, or some of the data outputs might start to change before the clock signal has arrived. With these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tPSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The tPSK specified optocouplers offer the advantages of guaranteed specifications for propagation delays, pulse-width distortion, and propagation delay skew over the recommended temperature and power supply ranges. Broadcom -9- ACPL-W70L-000E and ACPL-K73L-000E Data Sheet Propagation Delay, Pulse-Width Distortion, and Propagation Delay Skew Figure 8 Recommended Printed Circuit Board Layout 1 IF 3 4 GND 1 2 GND 1 3 IF2 4 Vo GND2 ACPL-W70L ACPL-K73L Figure 9 Propagation Delay Skew Waveform 50% 2.5 V, CMOS VO tPSK VI 50% 2.5 V, CMOS VO Figure 10 Parallel Data Transmission Example DATA INPUTS CLOCK DATA OUTPUTS 7 VO1 6 VO2 5 C=0.01μF to 0.1μF VI VDD 8 XXX YWW GND1 5 1 C C XXX YWW 2 IF1 V DD 6 tPSK CLOCK tPSK Broadcom - 10 - GND 2 ACPL-W70L-000E and ACPL-K73L-000E Data Sheet Powering Sequence Powering Sequence Figure 12 Improvement of tp and PWD with Added 100-pF Peaking Capacitor in Parallel of Input Limiting Resistor VDD must achieve a minimum level of 3V before powering up the output connecting component. 35 t PLH 30 Input Limiting Resistor The ACPL-W70L and ACPL-K73L are direct current driven (Figure 8), and thus eliminate the need for input power supply. To limit the amount of current flowing through the LED, it is recommended that a 530Ω resistor is connected in series with anode of LED (i.e., Pin 1 for ACPL-W70L, Pin 1 and P4 for ACPL-K73L) at 5V input signal. At 3.3V input signal, it is recommended to connect a 250Ω resistor in series with anode of LED. The recommended limiting resistors is based on the assumption that the driver output impedance is 50Ω (as shown in Figure 11). Figure 11 Connection of Peaking Capacitor (Cpeak) in Parallel of the Input Limiting Resistor (Rllimit) to Improve Speed Performance t PHL 25 t PHL 20 15 t PLH 10 |PWD| 5 0 -40 -20 0 + Vi C peak 0.1μF - GND1 SHIELD VDD2 25 VO 20 60 80 100 tPHL tPLH t PHL 15 t PLH 10 GND 2 40 40 30 Rlimit 20 (i) VDD2 = 5V, Cpeak = 100 pF, Rlimit = 530Ω 35 R drv = 50: With peaking cap Without peaking cap 5 With peaking cap Without peaking cap |PWD| 0 -40 -20 0 20 40 60 (ii) VDD2 = 3.3V, Cpeak = 100 pF, Rlimit = 250Ω Speed Improvement A peaking capacitor can be placed across the input current limit resistor (Figure 11) to achieve enhanced speed performance. The value of the peaking cap is dependent on the rise and fall time of the input signal and supply voltages and LED input driving current (IF). Figure 12 shows significant improvement of propagation delay and pulse width distortion with added 100-pF peak capacitor at driving current of 6 mA and 5V power supply. Broadcom - 11 - 80 100 ACPL-W70L-000E and ACPL-K73L-000E Data Sheet Common-Mode Rejection for ACPL-W70L AND ACPL-K73L Common-Mode Rejection for ACPL-W70L AND ACPL-K73L For conditions where IF is close to the switching threshold (ITH), CML also depends on the extent that ILP and ILN balance each other. In other words, any condition where common-mode transients cause a momentary decrease in IF (i.e., when dVCM/dt>0 and |IFP| > |IFN|, referring to Table 1) causes common-mode failure for transients that are fast enough. Figure 13 shows the recommended driving circuit for the ACPL-W70L and ACPL-K73L for optimal common-mode rejection performance. Two LED-current setting resistors are used instead of one. This is to balance the common-mode impedance at LED anode and cathode. Common-mode transients can capacitively couple from the LED anode (or cathode) to the output-side ground causing current to be shunted away from the LED (which can be bad if the LED is on) or conversely cause current to be injected into the LED (bad if the LED is meant to be off ). Figure 14 shows the parasitic capacitances that exist between LED anode/cathode and output ground (CLA and CLC). Also shown in Figure 14 on the input side is an AC-equivalent circuit. Likewise, for common-mode transients that occur when the LED is off (i.e., CMH, since the output is high), if an imbalance between ILP and ILN results in a transient IF equal to or greater than the switching threshold of the optocoupler, the transient signal can cause the output to spike below 2V (which constitutes a CMH failure). By using the recommended circuit in Figure 13, good CMR can be achieved. The resistors recommended in Figure 13 include both the output impedance of the logic driver circuit and the external limiting resistor. The balanced ILED-setting resistors help equalize the common-mode voltage change at anode and cathode to reduce the amount by which ILED is modulated from transient coupling through CLA and CLC. Table 1 indicates the directions of ILP and ILN flow depending on the direction of the common-mode transient. For transients occurring when the LED is on, common-mode rejection (CML, since the output is in the low state) depends upon the amount of LED current drive (IF). Figure 13 Recommended Drive Circuit for ACPL-W70L and ACPL-K73L for High-CMR Rtotal =300Ω for VDD=3.3V = 580Ω for VDD=5V 1/2R total V DD2 V DD1 VO 0.1μF 1/2R total 74LS04 OR ANY TOTEMPOLE OUTPUT LOGIC GATE GND 2 SHIELD GND 1 Figure 14 AC Equivalent of ACPL-W70L and ACPL-K73L ½ R total V DD2 ILP C LA ½ R total VO 0.1μF 15pF ILN C LC SHIELD GND 2 Broadcom - 12 - ACPL-W70L-000E and ACPL-K73L-000E Data Sheet CMR with Other Drive Circuits Table 1 Effects of Common-Mode Pulse Direction on Transient ILED If |ILP| < |ILN|, If |ILP| > |ILN|, LED IF Current Is Momentarily: LED IF Current Is Momentarily: If dVCM/dt Is: Then ILP Flows: And ILN Flows: Positive (>0) Away from LED anode through CLA Away from LED cathode through CLC Increased Decreased Negative (