ACPM-5040-TR1

ACPM-5040 3 x 3 mm Power Amplifier Module LTE Band-40 (2300-2400 MHz) Data Sheet Description Features The ACPM-5040 is a fully matched 10-pin surface mount Power Amplifier Module developed (PAM) for TD-LTE Band-40 applications. This power amplifier module operates in the 2300-2400 MHz bandwidth. The ACPM-5040 meets stringent LTE (MPR = 0 dB) linearity requirements up to 27.7 dBm output power. The 3 x 3 mm form factor package is self contained, incorporating 50 ohm input and output matching networks. x Thin Package (0.9 mm typ.) The ACPM-5040 features the 5th generation of CoolPAM (CoolPAM5) circuit technology, which supports 3 power modes (active bypass, mid power and high power modes) with 2-bit digital control. The CoolPAM is a stage bypass PA technology enhancing PAE (power added efficiency) in the low and medium power ranges. The active bypass feature is added to CoolPAM-5 to enhance the PAE further in the low output power range and it enables to have exceptionally low quiescent current. It dramatically saves the average power consumption and accordingly extends the talk time of handsets with a given battery capacity. A high performance directional coupler is integrated into the module and both coupling and isolation ports are available to support daisy chain connection for multiband applications. The integrated coupler has excellent coupler directivity, which minimizes the coupled output power variation or delivered power variation caused by the load mismatch from the antenna. The coupler directivity, or the output power variation into the mismatched load, is critical to the TRP and SAR performance of the mobile phones in real field operations as well as compliance tests for the system certifications. Vref and a bias switch are integrated in the ACPM-5040, so an external LDO regulator and a bias switch transistor are not required. It also makes the PA fully digitalcontrollable by the Ven pin that simply turns the PA x Excellent Linearity x 3-mode power control with Vbp and Vmode Bypass / Mid Power Mode / High Power Mode x High Efficiency at max output power x 10-pin surface mounting package x Internal 50 ohm matching networks for both RF input and output x Integrated coupler Coupler and Isolation ports for daisy chain x Green – Lead-free and RoHS compliant Applications x TD-LTE Band-40 Ordering Information Part Number Number of Devices Container ACPM-5040-TR1 1000 178 mm (7”) Tape/Reel ACPM-5040-BLK 100 Bulk Description (Cont.) on and off from the digital control logic input from a baseband chip. All of the digital control input pins such as the Ven, Vmode and Vbp are fully CMOS logic compatible and “Hi” logic state can operate down to 1.35 V. The current consumption by digital control pins is negligible. This power amplifier is fabricated with an advanced InGaP HBT (hetero-junction Bipolar Transistor) MMIC (microwave monolithic integrated circuit) process, offering state-ofthe-art reliability, temperature stability and ruggedness. Absolute Maximum Ratings No damage assuming only one parameter is set at limit at a time with all other parameters set at or below nominal value Operation of any single parameter outside these conditions with the remaining parameters set at or below nominal values may result in permanent damage. Description Min. RF Input Power (Pin) Typ. Max. Unit 0 10.0 dBm DC Supply Voltage (Vcc1, Vcc2) 0 3.4 5.0 V Enable Voltage (Ven) 0 2.6 3.3 V Mode Control Voltage (Vmode) 0 2.6 3.3 V Bypass Control (Vbp) 0 2.6 3.3 V Storage Temperature (Tstg) -55 25 +125 °C Min. Typ. Max. Unit Recommended Operating Condition Description DC Supply Voltage (Vcc1, Vcc2) 3.2 3.4 4.2 V Enable Voltage (Ven) Low High 0 1.35 0 2.6 0.5 3.1 V V Mode Control Voltage (Vmode) Low High 0 1.35 0 2.6 0.5 3.1 V V Bypass Control Voltage (Vbp) Low High 0 1.35 0 2.6 0.5 3.1 V V 2400 MHz 90 °C Operating Frequency (fo) 2300 Ambient Temperature (Ta) -20 25 Operating Logic Table Power Mode Ven Vmode Vbp Pout (LTE MPR = 0 dB) High Power Mode High Low Low ~ 27.7 dBm Mid Power Mode High High Low ~ 16.5 dBm Bypass Mode High High High ~ 7 dBm Shut Down Mode Low Low Low – 2 Electrical Characteristics for LTE – Conditions: Vcc = 3.4 V, Ven = 2.6 V, T = 25 :, Zin/Zout = 50 ohm – Signal Configuration: 3GPP 10 MHz 12RB QPSK Up-Link unless specified otherwise. Characteristics Condition Min. Typ. Max. Unit Operating Frequency Range Maximum Output Power (High Power Mode)   LTE, MPR = 0 dB (High Power Mode) LTE, MPR = 0 dB (Mid Power Mode) LTE, MPR = 0 dB (Bypass Mode) High Power Mode, Pout = 27.7 dBm Mid Power Mode, Pout = 16.5 dBm Bypass Mode, Pout = 7 dBm High Power Mode, Pout = 27.7 dBm Mid Power Mode, Pout = 16.5 dBm Mid Power Mode, Pout = 13.5 dBm Bypass Mode, Pout = 7 dBm Bypass Mode, Pout = 3.5 dBm High Power Mode, Pout = 27.7 dBm Mid Power Mode, Pout = 16.5 dBm Mid Power Mode, Pout = 13.5 dBm Bypass Mode, Pout = 7 dBm Bypass Mode, Pout = 3.5 dBm High Power Mode Mid Power Mode Bypass Mode High Power Mode Mid Power Mode Bypass Mode Mid Power Mode Bypass Mode Bypass Ven = 0 V, Vmode = 0 V, Vbp = 0 V Pout < (maximum power -MPR) Pout < (maximum power -MPR) Pout < (maximum power -MPR) High Power Mode, Pout = 27.7 dBm 2300 27.7 16.5 7 25 17 8 32.6 14.5 – 2400 135 26 6 100 100 100 100 100 100 10 -33 -36 -39 -35 -42 5 3 MHz dBm dBm dBm dB dB dB % % % % % mA mA mA mA mA mA mA mA PA PA PA PA PA PA PA dBc dBc dBc dBc/1 MHz dBc/1 MHz % % -143 -87 -60 -140 -80 dBc dBm/Hz dBm/Hz -102 -94 dBm/Hz -111 -108 dBm/Hz Gain Power Added Efficiency Total Supply Current Quiescent Current Enable Current Mode Control Current Bypass Control Current Total Current in Power-down mode LTE E-UTRAACLR Adjacent Channel UTRAACLR1 Leakage Ratio UTRAACLR2 Harmonics Second Suppression Third RMS EVM Input VSWR Stability (Spurious Output) GPS Band Noise Power (Vcc = 4.2 V) ISM Band Noise Power (Vcc = 3.2 V) Phase Discontinuity Ruggedness Coupling factor Delivered Power Variation by Load Mismatch with Constant Coupled Power Daisy Chain Insertion Loss 6.1 75 12 2 Pout < (maximum power -MPR) Pout < (maximum power -MPR -3 dB)   VSWR 5:1, All phase High Power Mode, Pout = 27.7 dBm High Power Mode, 20 MHz 100RB QPSK, fc = 2390 MHz, Pout = 26.7 dBm 2420 ~ 2440 MHz High Power Mode, 20 MHz 100RB QPSK, fc = 2390 MHz, Pout = 26.7 dBm 2440 ~ 2460 MHz High Power Mode, 20 MHz 100RB QPSK, fc = 2390 MHz, Pout = 26.7 dBm 2460 ~ 2480 MHz low power mode lmid power mode, at Pout = 7 dBm mid power mode lhigh power mode, at Pout = 16 dBm Pout < 27.7 dBm, Pin < 10 dBm, All phase High Power Mode RF Out to CPL port Load VSWR = 2.5:1 All Phase, Constant Pcpl ISO port to CPL port, Ven = Low At below 3.3 V operation, 0.5 dB backoff is allowed for maximum power output. 3 27.7 21.5 12.5 36.4 20.1 14.5 9.3 6.4 475 65 45.3 15 9.6 106 19 4 4 4 4 4 4 4 -37 -38.5 -60 -37 -51 24 16 530 90 23 2:1 31 deg 5 deg 10:1 VSWR 20 ±0.3 ±1.0 dB dB 0.25 dB Electrical Characteristics for TD-SCDMA – Conditions: Vcc = 3.4 V, Ven = 2.6 V, T = 25° C, Zin/Zout = 50 ohm Characteristics Condition Min. Typ. Max. Unit Operating Frequency Range   2300 – 2400 MHz Gain High Power Mode, Pout = 27.7 dBm 25 27.7 dB Mid Power Mode, Pout = 16 dBm 17 21.5 dB Bypass Mode, Pout = 6 dBm 8 12.5 High Power Mode, Pout = 27.7 dBm 31.7 35.3 Power Added Efficiency Total Supply Current Adjacent Channel Leakage Ratio Harmonics Suppression dB % Mid Power Mode, Pout = 16 dBm 12.9 19.5 % Bypass Mode, Pout = 6 dBm 5.5 8.5 % High Power Mode, Pout = 27.7 dBm 490 545 mA Mid Power Mode, Pout = 16 dBm 60 90 mA Bypass Mode, Pout = 6 dBm 13 20 mA 1.6 MHz offset 3.2 MHz offset High Power Mode, Pout = 27.7 dBm -42 -54 -36 -46 dBc dBc 1.6 MHz offset 3.2 MHz offset Mid Power Mode, Pout = 16 dBm -54 -67 -36 -46 dBc dBc 1.6 MHz offset 3.2 MHz offset Bypass Mode, Pout = 6 dBm -45 -60 -36 -46 dBc dBc Second Third High Power Mode, Pout = 27.7 dBm -32 -54 At below 3.3 V operation, 0.5 dB backoff is allowed for maximum power output. 4 16 dBc dBc Footprint All dimensions are in millimeter 1.50 0.10 0.125 Pin 1 0.60 0.35 0.35 0.25 0.10 0.3 X-RAY TOP VIEW Pin Description Pin # Name Description Pin # Name Description 1 Vcc1 DC Supply Voltage 6 CPL Coupling port of Coupler 2 RFin RF Input 7 GND Ground 3 Vbp Bypass Control 8 ISO Isolation port of Coupler 4 Vmode Mode Control 9 RFOut RF Out 5 Ven PA Enable 10 Vcc2 DC Supply Voltage Package Dimensions All dimensions are in millimeter 0.6 Pin 1 Mark 1 10 2 9 3 8 4 7 5 6 3 ± 0.1 5 3 ± 0.1 1.0 ± 0.1 Marking Specification Pin 1 Mark A5040 Manufacturing Part Number PYYWW Lot Number P Manufacturing Info YY Manufacturing Year WW Work Week AAAAA Assemby Lot Number AAAAA Metallization Solder Paste Stencil Aperture on 0.5 mm pitch Ø 0.3 mm 0.55 0.45 0.35 0.45 0.30 1.10 0.60 0.60 0.475 0.35 0.475 connected to a inner layer through a via hole for a better isolation between CPL_IN(ISO) and RFout 0.55 Solder Mask Opening 0.65 PCB Design Guidelines The recommended PCB land pattern is shown in figures on the left side. The substrate is coated with solder mask between the I/O and conductive paddle to protect the gold pads from short circuit that is caused by solder bleeding/bridging. 0.50 Stencil Design Guidelines 0.45 1.30 0.60 0.525 1.50 6 1.10 A properly designed solder screen or stencil is required to ensure optimum amount of solder paste is deposited onto the PCB pads. The recommended stencil layout is shown here. Reducing the stencil opening can potentially generate more voids. On the other hand, stencil openings larger than 100% will lead to excessive solder paste smear or bridging across the I/O pads or conductive paddle to adjacent I/O pads. Considering the fact that solder paste thickness will directly affect the quality of the solder joint, a good choice is to use laser cut stencil composed of 0.100 mm (4 mils) or 0.127 mm (5 mils) thick stainless steel which is capable of producing the required fine stencil outline. Evaluation Board Schematic Vcc1 Vcc2 1 Vcc1 RF In C5 2.2 PF Vcc2 10 C4 1000 pF C6 1000 pF RF Out 9 2 RF In Isolation Vbp 3 Vbp Vmode C3 100 pF Ven C2 100 pF C1 100 pF ISO 8 4 Vmode GND 7 5 Ven CPL 6 50 ohm Coupler Evaluation Board Description C5 C7 C4 C6 A5040 PYYWW AAAAA C3 C2 7 C7 2.2 PF RF Out C1 Tape and Reel Information A5040 PYYWW AAAAA Dimension List Annote Millimeter Annote Millimeter A0 3.40±0.10 P2 2.00±0.05 B0 3.40±0.10 P10 40.00±0.20 K0 1.35±0.10 E 1.75±0.10 D0 1.55±0.05 F 5.50±0.05 D1 1.60±0.10 W 12.00±0.30 P0 4.00±0.10 T 0.30±0.05 P1 8.00±0.10 Tape and Reel Format – 3 mm x 3 mm 8 Reel Drawing BACK VIEW Shading indicates thru slots 18.4 max. 178 +0.4 -0.2 50 min. 25 min wide (ref) Slot for carrier tape insertion for attachment to reel hub (2 places 180° apart) 12.4 +2.0 -0.0 FRONT VIEW 1.5 min. 13.0 ± 0.2 21.0 ± 0.8 Plastic Reel Format (all dimensions are in millimeters) 9 NOTES: 1. Reel shall be labeled with the following information (as a minimum). a. manufacturers name or symbol b. Avago Technologies part number c. purchase order number d. date code e. quantity of units 2. A certificate of compliance (c of c) shall be issued and accompany each shipment of product. 3. Reel must not be made with or contain ozone depleting materials. 4. All dimensions in millimeters (mm) Handling and Storage ESD (Electrostatic Discharge) Electrostatic discharge occurs naturally in the environment. With the increase in voltage potential, the outlet of neutralization or discharge will be sought. If the acquired discharge route is through a semiconductor device, destructive damage will result. ESD countermeasure methods should be developed and used to control potential ESD damage during handling in a factory environment at each manufacturing site. MSL (Moisture Sensitivity Level) Plastic encapsulated surface mount package is sensitive to damage induced by absorbed moisture and temperature. Avago Technologies follows JEDEC Standard J-STD 020B. Each component and package type is classified for moisture sensitivity by soaking a known dry package at various temperatures and relative humidity, and times. After soak, the components are subjected to three consecutive simulated reflows. The out of bag exposure time maximum limits are determined by the classification test describe below which corresponds to a MSL classification level 6 to 1 according to the JEDEC standard IPC/JEDEC J-STD-020B and J-STD-033. ACPM-5040 is MSL3. Thus, according to the J-STD-033 p.11 the maximum Manufacturers Exposure Time (MET) for this part is 168 hours. After this time period, the part would need to be removed from the reel, de-taped and then re-baked. MSL classification reflow temperature for the ACPM-5040 is targeted at 260° C +0/-5° C. Figure and table on next page show typical SMT profile for maximum temperature of 260 +0/-5° C. Moisture Classification Level and Floor Life MSL Level Floor Life (out of bag) at factory ambient = < 30° C/60% RH or as stated 1 Unlimited at = < 30° C/85% RH 2 1 year 2a 4 weeks 3 168 hours 4 72 hours 5 48 hours 5a 24 hours 6 Mandatory bake before use. After bake, must be reflowed within the time limit specified on the label Note: 1. The MSL Level is marked on the MSL Label on each shipping bag. 10 Reflow Profile Recommendations tp Tp Critical Zone TL to Tp Temperature Ramp-up TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25° C to Peak Time Typical SMT Reflow Profile for Maximum Temperature = 260 +0/-5° C Typical SMT Reflow Profile for Maximum Temperature = 260 +0/-5° C Profile Feature Sn-Pb Solder Pb-Free Solder Average ramp-up rate (TL to TP) 3° C/sec max 3° C/sec max Preheat – Temperature Min (Tsmin) – Temperature Max (Tsmax) – Time (min to max) (ts) 100° C 150° C 60-120 sec 150° C 200° C 60-180 sec Tsmax to TL – Ramp-up Rate 3° C/sec max Time maintained above: – Temperature (TL) – Time (TL) 183° C 60-150 sec 217° C 60-150 sec Peak temperature (TP) 240 +0/-5° C 260 +0/-5° C Time within 5° C of actual Peak Temperature (TP) 10-30 sec 20-40 sec Ramp-down Rate 6° C/sec max 6° C/sec max Time 25° C to Peak Temperature 6 min max 8 min max 11 Storage Condition Removal for Failure Analysis Packages described in this document must be stored in sealed moisture barrier, antistatic bags. Shelf life in a sealed moisture barrier bag is 12 months at < 40° C and 90% relative humidity (RH) J-STD-033 p.7. Not following the above requirements may cause moisture/ reflow damage that could hinder or completely prevent the determination of the original failure mechanism. Baking of Populated Boards Out-of-Bag Time Duration After unpacking the device must be soldered to the PCB within 168 hours as listed in the J-STD-020B p.11 with factory conditions < 30° C and 60% RH. Baking It is not necessary to re-bake the part if both conditions (storage conditions and out-of bag conditions) have been satisfied. Baking must be done if at least one of the conditions above have not been satisfied. The baking conditions are 125° C for 12 hours J-STD-033 p.8. CAUTION Tape and reel materials typically cannot be baked at the temperature described above. If out-of-bag exposure time is exceeded, parts must be baked for a longer time at low temperatures, or the parts must be de-reeled, de-taped, re-baked and then put back on tape and reel. (See moisture sensitive warning label on each shipping bag for information of baking). Board Rework Component Removal, Rework and Remount If a component is to be removed from the board, it is recommended that localized heating be used and the maximum body temperatures of any surface mount component on the board not exceed 200° C. This method will minimize moisture related component damage. If any component temperature exceeds 200° C, the board must be baked dry per 4-2 prior to rework and/or component removal. Component temperatures shall be measured at the top center of the package body. Any SMD packages that have not exceeded their floor life can be exposed to a maximum body temperature as high as their specified maximum reflow temperature. Some SMD packages and board materials are not able to withstand long duration bakes at 125° C. Examples of this are some FR-4 materials, which cannot withstand a 24 hr bake at 125° C. Batteries and electrolytic capacitors are also temperature sensitive. With component and board temperature restrictions in mind, choose a bake temperature from Table 4-1 in J-STD 033; then determine the appropriate bake duration based on the component to be removed. For additional considerations see IPC-7711 and IPC-7721. Derating due to Factory Environmental Conditions Factory floor life exposures for SMD packages removed from the dry bags will be a function of the ambient environmental conditions. A safe, yet conservative, handling approach is to expose the SMD packages only up to the maximum time limits for each moisture sensitivity level as shown in next table. This approach, however, does not work if the factory humidity or temperature is greater than the testing conditions of 30° C/60% RH. A solution for addressing this problem is to derate the exposure times based on the knowledge of moisture diffusion in the component package materials ref. JESD22-A120). Recommended equivalent total floor life exposures can be estimated for a range of humidities and temperatures based on the nominal plastic thickness for each device. Table on next page lists equivalent derated floor lives for humidities ranging from 20-90% RH for three temperature, 20° C, 25° C, and 30° C. Table on next page is applicable to SMDs molded with novolac, biphenyl or multifunctional epoxy mold compounds. The following assumptions were used in calculating this table: 1. Activation Energy for diffusion = 0.35eV (smallest known value). 2. For ≤ 60% RH, use Diffusivity = 0.121exp (-0.35eV/kT) mm2/s (this used smallest known Diffusivity @ 30° C). 3. For > 60% RH, use Diffusivity = 1.320exp (-0.35eV/kT) mm2/s (this used largest known Diffusivity @ 30° C). 12 Recommended Equivalent Total Floor Life (days) @ 20° C, 25° C & 30° C, 35° C For ICs with Novolac, Biphenyl and Multifunctional Epoxies (Reflow at same temperature at which the component was classified) Maximum Percent Relative Humidity Maximum Percent Relative Humidity Package Type and Body Thickness Body Thickness ≥3.1 mm Including PQFPs >84 pin, PLCCs (square) All MQFPs or All BGAs ≥1 mm Moisture Sensitivity Level Level 2a Level 3 Level 4 Level 5 Level 5a Body 2.1 mm ≤ Thickness