ACSL-6xx0
Multi-Channel and Bi-Directional,
15 MBd Digital Logic Gate Optocoupler
Data Sheet
Description
ACSL-6xx0 are truly isolated,
multi-channel and bi-directional,
high-speed optocouplers. Integration of multiple optocouplers in
monolithic form is achieved
through patented process technology. These devices provide full
duplex and bi-directional isolated data transfer and communication capability in compact
surface mount packages. Available in 15 Mbd speed option and
wide supply voltage range.
These high channel density make
them ideally suited to isolating
data conversion devices, parallel
buses and peripheral interfaces.
They are available in 8-pin and
16–pin narrow-body SOIC
package and are specified over
the temperature range of
-40°C to +100° C.
Applications
• Full duplex communication
• Isolated line receiver
• Computer-peripheral interfaces
Features
• Available in dual, triple and quad
channel configurations
• Bi-directional
• Microprocessor system interfaces
• Wide supply voltage range
3.0V to 5.5V
• Digital isolation for A/D and D/A
conversion
• High-speed: 15 MBd typical,
10 MBd minimum
• Switching power supply
• Instrument input/output isolation
• 10 kV/µs minimum Common Mode
Rejection (CMR) at Vcm = 1000 V
• Ground loop elimination
• LSTTL/TTL compatible
• Pulse transformer replacement
• Safety and regulatory approvals
(Pending)
– 2500Vrms for 1 min per UL1577
– CSA Component Acceptance
– IEC/EN/DIN EN 60747-5-2
• 16 Pin narrow-body SOIC package
for triple and quad channel
• -40 to 100°C temperature range
CAUTION:
It is advised that normal static precautions be taken in handling and
assembly of this component to prevent damage and/or degradation,
which may be induced by ESD.
Device Selection Guide
Device Number
Channel Configuration
Package
ACSL-6210
Dual, Bi-Directional`
8-pin Small Outline
ACSL-6300*
Triple, All-in-One
16-pin Small Outline
ACSL-6310*
Triple, Bi-Directional, 2/1
16-pin Small Outline
ACSL-6400
Quad, All-in-One
16-pin Small Outline
ACSL-6410*
Quad, Bi-Directional, 3/1
16-pin Small Outline
ACSL-6420*
Quad, Bi-Directional, 2/2
16-pin Small Outline
* Advanced Information
Ordering Information
ACSL-6XX0-X Y Z E
Lead Free Option
Channel Configuration
(Refer to the Device
Selection Guide)
R = SO-8 Package, 100 units per tube
T = SO-16 Package, 50 units per tube
6 = IEC/EN/DIN EN 60747-5-2,
VIORM = 560V peak Option
5 = Tape and Reel Packaging Option,
1500 units per reel for SO-8 Package
and 1000 units per reel for SO-16 Package
Pin Description
Symbol
Description
Symbol
Description
VDD1
Power Supply 1
GND1
Power Supply Ground 1
VDD2
Power Supply 2
GND2
Power Supply Ground 2
ANODEx
LED Anode
NC
Not Connected
CATHODEx
LED Cathode
VOX
Output Signal
Truth Table (Positive Logic)
LED
OUTPUT
ON
L
OFF
H
2
Functional Diagrams
ACSL-6210 - Dual-Ch, Bi-Dir
ACSL-6300 - Triple-Ch, All-in-One*
1
8
4
5
ACSL-6310 - Triple-Ch, Bi-Dir (2/1)*
ACSL-6400 - Quad-Ch, All-in-One
ACSL-6410 - Quad-Ch, Bi-Dir (3/1)*
ACSL-6420 - Quad-Ch, Bi-Dir (2/2)*
* Advanced Information
3
Schematic Diagrams
The ACSL-6xx0 series
optocouplers feature the GaAsP
LEDs with proprietary back
emission design. They offer the
designer a broad range of input
drive current, from 7 mA to
15 mA, thus providing greater
flexibility in designing the drive
circuit.
The output detector integrated
circuit (IC) in the optocoupler
consists of a photodiode at the
input of a two-stage amplifier
that provides both high gain and
high bandwidth. The secondary
amplifier stage of the detector IC
feeds into an open collector
Schottky-clamped transistor.
ACSL-6300 - Triple-Ch, All-in-One*
ACSL-6210 - Dual-Ch, Bi-Dir
Shield
1
GND1
CATHODE2
The entire output circuit is electrically shielded so that any commonmode transient capacitively
coupled from the LED side of the
optocoupler is diverted from the
photodiode to ground. With this
electric shield, the optocoupler can
withstand transients that slopes
up to 10,000V/µs, and amplitudes
up to 1,000V.
16
15
8
ANODE1
ANODE1
1
14
GND
VDD
Vo1
2
Vo1
3
CATHODE1
VDD1
2
7
VDD2
6
Shield
Vo2
ANODE2
3
13
4
ANODE2
5
Shield
GND2
CATHODE1
CATHODE2
Vo2
4
Shield
ANODE3
CATHODE3
5
12
6
10
9
Shield
ACSL-6310 - Triple-Ch, Bi-Dir (2/1)*
Shield
1
GND1
14
ANODE3
3
13
Vo3
CATHODE3
4
VDD1
12
ANODE1
CATHODE1
5
11
VDD2
Vo1
6
Shield
ANODE2
CATHODE2
7
10
8
9
Shield
* Advanced Information
4
Vo2
GND2
Vo3
VDD
GND
Schematic Diagrams, continued
ACSL-6400 - Quad-Ch, All-in-One
ACSL-6410 - Quad-Ch, Bi-Dir (3/1)*
16
15
ANODE1
1
14
GND
VDD
Shield
1
16
Vo1
2
2
CATHODE1
GND1
CATHODE1
15
Vo4
3
VDD1
14
Shield
3
ANODE2
13
13
Vo2
ANODE1
4
CATHODE2
12
CATHODE2
5
ANODE2
7
11
8
10
CATHODE3
7
11
Vo4
ANODE3
8
10
VDD
GND
Shield
9
Shield
ACSL-6420 - Quad-Ch, Bi-Dir (2/2)*
Shield
1
16
2
15
Vo4
ANODE4
CATHODE4
Shield
14
ANODE3
3
13
Vo3
VDD1
4
12
ANODE1
CATHODE1
5
11
CATHODE3
VDD2
Vo1
6
Shield
ANODE2
CATHODE2
7
10
9
5
Vo2
8
Shield
Vo2
Shield
9
GND1
Vo1
6
Shield
CATHODE4
12
Vo3
6
ANODE4
GND2
Shield
5
CATHODE3
ANODE4
4
Shield
ANODE3
CATHODE4
GND2
* Advanced Information
Vo3
VDD2
GND2
Package Outline Drawings
ACSL-6210 Small Outline SO-8 Package
0.189 (4.80)
0.197 (5.00)
8
7
6
5
0.228 (5.80)
0.244 (6.20)
0.150 (3.80)
0.157 (4.00)
1
2
3
4
0.013 (0.33)
0.020 (0.51)
0.010 (0.25)
0.020 (0.50)
x 45°
0.008 (0.19)
0.010 (0.25)
0.004 (0.10)
0.010 (0.25)
0.054 (1.37)
0.069 (1.75)
0°
8°
0.040 (1.016)
0.060 (1.524)
0.016 (0.40)
0.050 (1.27)
DIMENSIONS: INCHES (MILLIMETERS) MIN
MAX
ACSL-6300*, ACSL-6310*, ACSL-6400, ACSL-6410* and
ACSL-6420* Small Outline SO-16 Package
0.386 (9.802)
0.394 (9.999)
8
1
0.228 (5.791)
0.244 (6.197)
0.152 (3.861)
0.157 (3.988)
0.013 (0.330)
0.020 (0.508)
0.054 (1.372)
0.068 (1.727)
0.050 (1.270)
0.060 (1.524)
0.010 (0.245)
x 45°ß
0.020 (0.508)
0° – 8° TYP
0.040 (1.016)
0.060 (1.524)
DIMENSIONS: INCHES (MIL LIMETERS) MIN
MAX
6
0.008 (0.191)
0.010 (0.249)
0.004 (0.102)
0.010 (0.249)
0.016 (0.406)
0.050 (1.270)
Solder Reflow Temperature Profile
300
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
PEAK
TEMP.
240°C
PEAK
TEMP.
230°C
200
TEMPERATURE (°C)
PEAK
TEMP.
245°C
2.5°C ± 0.5°C/SEC.
SOLDERING
TIME
200°C
30
SEC.
160°C
150°C
140°C
30
SEC.
3°C + 1°C/–0.5°C
100
PREHEATING TIME
150°C, 90 ± 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
0
50
100
150
TIME (SECONDS)
Recommended Pb-free IR Profile
20– 40 SEC.
7
200
250
Regulatory Information
Insulation and Safety Related Specifications
Parameter
Symbol
Value
Units
Conditions
Minimum External Air Gap (Clearance)
L(I01)
4.9
mm
Measured from input terminals to output terminals,
shortest distance through air
Minimum Externa l Tracking(Creepage)
L(I02)
4.5
mm
Measured from input terminals to output terminals,
shortest distance path through body
Minimum Internal Plastic Gap (Internal Clearance)
0.08
mm
Insulation thickness between emitter and detector;
also known as distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI
175
Volts
DIN IEC 112/VDE0303 Part 1
Isolation Group
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics (Option X6X Only)
Description
Symbol
ACSL-6XX0-X6X
Installation Classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150V rms
for rated mains voltage ≤ 300V rms
I-IV
I-III
Climatic Classification
55/100/21
Pollution Degree (DIN VDE 0110/1.89)
2
Units
Maximum Working Insulation Voltage
VIORM
560
Vpeak
Input to Output Test Voltage, Method b *
VIORM x 1.875 = VPR, 100% Production
Test with tm = 1 sec, Partial Discharge < 5 pC
VPR
1050
Vpeak
Input to Output Test Voltage, Method a *
VIORM x 1.5 = VPR, Type and Sample Test,
Tm = 60 sec, Partial Discharge < 5 pC
VPR
840
Vpeak
Highest Allowable Overvoltage *
(Transient Overvoltage, tini = 10 sec)
VIOTM
4000
Vpeak
Safety Limiting Values
(Maximum values allowed in the event of a failure)
Case Temperature
Input Current
Output Power
TS
IS,INPUT
PS,OUTPUT
175
150
600
°C
mA
mW
Insulation Resistance at TS, VIO = 500V
RIO
109
Ω
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section, IEC/EN/DIN EN 60747-5-2,
for a detailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits in application.
8
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
Ts
-55
125
°C
Operating Temperature
TA
-40
100
°C
Supply Voltage (1 Minute Maximum)
VDD1 , VDD2
7
V
Reverse Input Voltage (Per Channel)
VR
5
V
Output Voltage (Per Channel)
VO
7
V
Average Forward Input Current [1] (Per Channel)
IF
15
mA
Output Current (Per Channel)
IO
50
mA
Input Power Dissipation[2] (Per Channel)
P1
24
mW
Output Power Dissipation [2] (Per Channel)
SO8 package
SO16 package
PO
60
40
mW
mW
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Operating Temperature
TA
-40
100
°C
Input Current, Low Level [3]
IFL
0
250
µA
Input Current, High Level [4]
IFH
7
15
mA
Supply Voltage
VDD1, VDD2
3.0
5.5
V
Fan Out (at RL = 1kΩ)
N
5
TTL Loads
Output Pull-up Resistor
RL
4k
Ω
Notes:
1. Peaking circuits may produce transient input
currents up to 50 mA, 50 ns max. pulse width,
provided average current does not exceed its
max. values.
2. Derate total package power dissipation, PT
linearly above +85°C free-air temperature at a
rate of 6.4 mW/°C for the SO8 package
mounted on low conductivity board per JESD
51-3. Derate total package power dissipation,
PT linearly above +78°C free-air temperature
700
Is (mA)
Ps (mW)
Output Power-Ps
Input Power-lp
600
500
400
300
200
100
0
0
25
50
75
100 125 150 175 200
Ts-Case Temperature,°C
9
330
at a rate of 7.98 mW/°C for the SO16 package
mounted on low conductivity board per JESD
51-3. PT= number of channels multiplied by
(PI+PO).
3. The off condition can be guaranteed by
ensuring that VFL ≤ 0.8V.
4. The initial switching threshold is 7 mA or
less. It is recommended that minimum 8 mA
be used for best performance and to permit
guardband for LED degradation.
Electrical Specifications
Over recommended operating range (3.0V ≤ VDD1 ≤ 3.6V, 3.0V ≤ VDD2 ≤ 3.6V, TA = -40°C to +100° C)
unless otherwise specified.
All typical specifications are at TA = +25°C , VDD1 = VDD2 = +3.3V.
Parameter
Symbol
Input Threshold Current
Min.
Typ.
Max.
Units
Test Conditions
ITH
2.7
7.0
mA
IOL(Sinking)=13 mA, VO = 0.6V
High Level Output Current
IOH
4.7
100.0
µA
IF = 250 µA, VO = 3.3V
Low Level Output Voltage
VOL
0.36
0.68
V
IOL(Sinking) = 13 mA, IF = 7mA
High Level Supply Current (per channel)
IDDH
3.2
5.0
mA
IF = 0 mA
Low Level Supply Current (per channel)
IDDL
4.6
7.5
mA
IF = 10 mA
Input Forward Voltage
VF
1.25
1.52
1.80
V
IF = 10 mA, TA = 25°C
Input Reverse Breakdown Voltage
BVR
5.0
V
IR = 10 µA
Input Diode Temperature Coefficient
∆VF / ∆TA
-1.8
mV/°C
IF = 10 mA
Input Capacitance
CIN
80
pF
f = 1 MHz, VF = 0V
Switching Specifications
Over recommended operating range (3.0V ≤ VDD1 ≤ 3.6V, 3.0V ≤ VDD2 ≤ 3.6V, IF = 8.0 mA, TA = -40° C to +100° C)
unless otherwise specified.
All typical specifications are at TA = +25°C , VDD1 = VDD2 = +3.3V.
Parameter
Symbol
Maximum Data Rate
Pulse Width
tPW
Propagation Delay Time to Logic High Output Level [5]
tPLH
Propagation Delay Time to Logic Low Output Level [6]
Pulse Width Distortion |tPHL – tPLH|
Propagation Delay Skew[7]
tPSK
Output Rise Time (10 – 90%)
tR
Output Fall Time (10 – 90%)
tF
Logic High Common Mode Transient Immunity [8]
|CMH|
Logic Low Common Mode Transient Immunity [8]
|CML|
Min.
Typ.
10
15
Max.
100
6. tPHL is measured from the 4.0 mA level on the
rising edge of the input pulse to the 1.5V level
on the falling edge of the output pulse.
7. tPSK is equal to the worst case difference in
tPHL and/or tPLH that will be seen between
units at any given temperature and specified
test conditions.
10
Test Conditions
MBd
RL = 350Ω, CL = 15 pF
ns
RL = 350Ω, CL = 15 pF
RL = 350Ω, CL = 15 pF
52
100
ns
tPHL
44
100
ns
RL = 350Ω, CL = 15 pF
|PWD|
8
35
ns
RL = 350Ω, CL = 15 pF
40
ns
RL = 350Ω, CL = 15 pF
35
ns
RL = 350Ω, CL = 15 pF
12
ns
RL = 350Ω, CL = 15 pF
10
kV/µs
Vcm = 1000V, IF = 0 mA,
VO = 2.0V, RL = 350Ω,
TA = 25°C
10
kV/µs
Vcm = 1000V, IF = 8 mA,
VO = 0.8V, RL = 350Ω,
TA = 25°C
Notes:
5. tPLH is measured from the 4.0 mA level on the
falling edge of the input pulse to the 1.5V
level on the rising edge of the output pulse.
Units
8. CMH is the maximum common mode voltage
slew rate that can be sustained while
maintaining VO > 2.0V. CML is the maximum
common mode voltage slew rate that can be
sustained while maintaining VO < 0.8V. The
common mode voltage slew rates apply to
both rising and falling common mode voltage
edges.
Electrical Specifications
Over recommended operating range (4.5V ≤ VDD1 ≤ 5.5V, 4.5V ≤ VDD2 ≤ 5.5V, TA = -40°C to +100° C)
unless otherwise specified.
All typical specifications are at TA = +25°C, VDD1 = VDD2 = +5.0V.
Parameter
Symbol
Input Threshold Current
Min.
Typ.
Max.
Units
Test Conditions
ITH
2.7
7.0
mA
IOL(Sinking)=13 mA, VO= 0.6V
High Level Output Current
IOH
3.8
100.0
µA
IF = 250 µA, VO= 5.5V
Low Level Output Voltage
VOL
0.36
0.6
V
IOL(Sinking)=13 mA, IF=7 mA
High Level Supply Current (per channel)
IDDH
4.3
7.5
mA
IF = 0 mA
Low Level Supply Current (per channel)
IDDL
5.8
10.5
mA
IF = 10 mA
Input Forward Voltage
VF
1.25
1.52
1.8
V
IF = 10 mA, TA = 25°C
Input Reverse Breakdown Voltage
BVR
5.0
V
IR = 10 µA
Input Diode Temperature Coefficient
∆VF / ∆TA
-1.8
mV/°C
IF = 10 mA
Input Capacitance
CIN
80
pF
f = 1 MHz, VF = 0 V
Switching Specifications
Over recommended operating range (4.5V ≤ VDD1 ≤ 5.5V, 4.5V ≤ VDD2 ≤ 5.5V, IF = 8.0 mA, TA = -40° C to +100° C)
unless otherwise specified.
All typical specifications are at TA=+25° C, VDD1 = VDD2 = +5.0V.
Parameter
Symbol
Maximum Data Rate
Pulse Width
tPW
Propagation Delay Time to Logic High Output Level[5]
tPLH
Propagation Delay Time to Logic Low Output Level[6]
Pulse Width Distortion |tPHL – tPLH|
Propagation Delay Skew[7]
tPSK
Output Rise Time (10 – 90%)
tR
Output Fall Time (10 – 90%)
tF
Logic High Common Mode Transient Immunity [8]
|CMH|
Logic Low Common Mode Transient Immunity [8]
|CML|
Min.
Typ.
10
15
Max.
100
6. tPHL is measured from the 4.0 mA level on the
rising edge of the input pulse to the 1.5V level
on the falling edge of the output pulse.
7. tPSK is equal to the worst case difference in
tPHL and/or tPLH that will be seen between
units at any given temperature and specified
test conditions.
11
Test Conditions
MBd
RL = 350Ω, CL =15 pF
ns
RL = 350Ω, CL =15 pF
RL = 350Ω, CL =15 pF
46
100
ns
tPHL
43
100
ns
RL = 350Ω, CL =15 pF
|PWD|
5
35
ns
RL = 350Ω, CL =15 pF
40
ns
RL = 350Ω, CL =15 pF
30
ns
RL = 350Ω, CL =15 pF
12
ns
RL = 350Ω, CL =15 pF
10
kV/µs
Vcm= 1000V, IF=0 mA,
VO = 2.0V, RL=350Ω,
TA = 25°C
10
kV/µs
Vcm= 1000V, IF= 8 mA,
VO = 0.8V, RL= 350Ω,
TA = 25°C
Notes:
5. tPLH is measured from the 4.0 mA level on the
falling edge of the input pulse to the 1.5V
level on the rising edge of the output pulse.
Units
8. CMH is the maximum common mode voltage
slew rate that can be sustained while
maintaining VO > 2.0V. CML is the maximum
common mode voltage slew rate that can be
sustained while maintaining VO < 0.8V. The
common mode voltage slew rates apply to
both rising and falling common mode voltage
edges.
Package Characteristics
All specifications are at TA=+25°C.
Parameter
Symbol
Min.
2500
2500
Typ.
Max.
Units
Test Conditions
VRMS
RH ≤ 50%, t = 1 min
RH ≤ 50%, t = 1 min
µA
45% RH, t=5 sec, VI-O= 3kV DC
45% RH, t=5 sec, VI-O =3kV DC
1011
1011
Ω
VI-O = 500V DC
VI-O = 500V DC
Input-Output Momentary
Withstand Voltage[9]
SO8
SO16
VISO
VISO
Input-Output Insulation [10] [11]
SO8
SO16
II-O
II-O
Input-Output Resistance[10]
SO8
SO16
RI-O
RI-O
Input-Output Capacitance[10]
SO8
SO16
CI-O
CI-O
0.7
0.7
pF
f = 1 MHz
f = 1 MHz
Input-Input Insulation
Leakage Current[12]
SO8
SO16
II-I
II-I
0.005
0.005
µA
RH ≤ 45%, t = 5 sec, VI-I = 500V
RH ≤ 45%, t = 5 sec, VI-I = 500V
Input-Input Resistance[12]
SO8
SO16
RI-I
RI-I
1011
1011
Ω
RH ≤ 45%, t= 5 sec, VI-I = 500V
RH ≤ 45%, t =5 sec, VI-I =500V
Input-Input Capacitance[12]
SO8
SO16
CI-I
CI-I
0.1
0.12
pF
f = 1 MHz
f = 1 MHz
Electrostatic Discharge Sensitivity
This product has been tested for
electrostatic sensitivity to the
limits stated in the specifications.
However, Avago recommends that
all integrated circuits be handled
with appropriate care to avoid
damage. Damage caused by
inappropriate handling or storage
could range from performance
degradation to complete failure.
12
5
5
109
109
Notes:
9. VISO is a dielectric voltage rating that should
not be interpreted as an input-output
continuous voltage rating. For continuous
voltage rating, refer to the IEC/EN/DIN EN
60747-5-2 Insulation Characteristics Table (if
applicable), the equipment level safety
specification or Avago Application Note 1074
entitled “Optocoupler Input-Output
Endurance Voltage.”
10. Measured between each input pair shorted
together and all output connections for that
channel shorted together.
11. In accordance to UL1577, each optocoupler
is proof tested by applying an insulation test
voltage ≥ 3000 Vrms for 1 sec (leakage
detection current limit, II-O ≤ 5 µA). This test
is performed before the 100% production test
for partial discharge (Method b) shown in the
IEC/EN/DIN EN 60747-5-2 Insulation
Characteristics Table, if applicable.
12. Measured between inputs with the LED
anode and cathode shorted together.
Typical Performance
70
6
VDD = 3.3V
VO = 0.6V
5
4
R L = 350Ω
3
R L = 1 KΩ
2
R L = 4 KΩ
1
VDD = 5.0V
VO = 0.6V
5
4
RL = 350Ω
3
RL = 1 KΩ
2
RL = 4 KΩ
1
-20
0
20
40
60
80
100
IF = 7.0 mA
40
30
20
-60
120
-40
-20
0
20
40
60
80
100
Figure 2. Typical input threshold current vs.
temperature for 5V operation.
70
15
IOH- HIGH LEVEL OUTPUT CURRENT -µA
VDD = 5.0V
VOL = 0.6V
60
IF = 10 mA
50
IF = 7.0 mA
40
30
20
-40
-20
0
20
40
60
80
100
VDD = 3.3V
VO = 3.3V
IF = 250 µA
0.5
0.4
IO = 13 mA
0.2
0.1
0
20
40
60
80
100 120
TA - TEMPERATURE -°C
Figure 7. Typical low level output voltage vs.
temperature for 3.3V operation.
VOL - LOW LEVEL OUTPUT VOLTAGE - V
0.6
20
40
60
80
100
120
10
5
VDD = 5.0V
VO = 5.0V
IF = 250 µA
10
5
0
0
20
40
60
80
-60
100 120
-40
-20
VDD = 5.0V
IF = 7 mA
0.6
0.5
0.4
IO = 13 mA
0.2
0.1
0.0
-60 -40 -20
20
40
60
80
100
Figure 6. Typical high level output current vs.
temperature for 5V operation.
10
0.7
0.3
0
T A - TEMPERATURE - °C
0.8
VDD = 3.3V
IF = 7 mA
0
Figure 3. Typical low level output current vs.
temperature for 3.3V operation.
Figure 5. Typical high level output current vs.
temperature for 3.3V operation.
0.8
0.3
-20
TA - TEMPERATURE - °C
Figure 4. Typical low level output current vs.
temperature for 5V operation.
0.7
-40
15
0
-60 -40 -20
120
T A - TEMPERATURE - °C
0.0
-60 -40 -20
-60
TA - TEMPERATURE - °C
Figure 1. Typical input threshold current vs.
temperature for 3.3V operation.
-60
120
TA - TEMPERATURE - °C
IOH- HIGH LEVEL OUTPUT CURRENT -µA
-40
T A - TEMPERATURE - °C
IOL- LOW LEVEL OUTPUT CURRENT - mA
50
0
20 40 60 80
TA - TEMPERATURE -°C
100 120
Figure 8. Typical low level output voltage vs.
temperature for 5V operation.
IDD- SUPPLY CURRENT PER CHANNEL - mA
-60
VOL- LOW LEVEL OUTPUT VOLTAGE - V
60
0
0
13
V DD = 3.3V
V OL = 0.6V
IOL - LOW LEVEL OUTPUT CURRENT - mA
ITH - INPUT THRESHOLD CURRENT - mA
ITH - INPUT THRESHOLD CURRENT - mA
6
VDD = 3.3V
9
8
7
6
IDDL
IF = 10 mA
5
4
3
2
IDDH
IF = 0 mA
1
0
-60 -40 -20
0
20
40
60
80
100 120
TA - TEMPERATURE -°C
Figure 9. Typical supply current per channel vs.
temperature for 3.3V operation.
120
Typical Performance, continued
TA = 25°C
7
IDDL
IF = 10 mA
6
5
4
IDDH
IF = 0 mA
3
2
10
IF
1
VF
+
–
0.1
0.01
VDD = 3.3V
IF = 8.0 mA
120
90
tPLH, RL = 350Ω
60
30
tPHL, RL = 350Ω
1
20
40
60
80
0.001
1.1
100 120
120
90
tPLH, RL = 350Ω
60
30
tPHL, RL = 350Ω
0
-60 -40 -20
0
20
40
60
80
100 120
TA - TEMPERATURE -°C
Figure 13. Typical propagation delay vs.
temperature for 5V operation.
PWD - PULSE WIDTH DISTORTION - ns
VDD = 5.0V
IF = 8.0 mA
0
-60 -40 -20
1.6
40
VDD = 3.3V
IF = 8.0 mA
30
20
10
0
-60 -40 -20
RL = 350Ω
0
20
40
0 20 40 60 80
TA - TEMPERATURE - °C
100 120
Figure 12. Typical propagation delay vs.
temperature for 3.3V operation.
Figure 11. Typical input diode
forward characteristics.
Figure 10. Typical supply current per channel vs.
temperature for 5V operation.
150
1.2
1.3
1.4
1.5
VF - FORWARD VOLTAGE - V
60
80
100 120
TA - TEMPERATURE -°C
Figure 14. Typical pulse width distortion vs.
temperature for 3.3V operation.
PWD - PULSE WIDTH DISTORTION - ns
0
TA - TEMPERATURE -°C
tP - PROPAGATION DELAY - ns
tP - PROPAGATION DELAY - ns
100
8
0
-60 -40 -20
14
150
1000
VDD = 5.0V
9
IF - FORWARD CURRENT - mA
IDD- SUPPLY CURRENT PER CHANNEL - mA
10
40
VDD = 5.0V
IF = 8.0 mA
30
20
10
0
-60 -40 -20
RL = 350Ω
0
20
40
60
80
100 120
TA - TEMPERATURE -°C
Figure 15. Typical pulse width distortion vs.
temperature for 5V operation.
Test Circuits
ACSL-6210
INPUT
MONITORING
NODE
PULSE GEN.
Zo = 50Ω
tf = tr = 5ns
3.3V or 5V
1
8
2
7
3
6
4
5
RL
0.1µF
BYPASS
C L*
OUTPUT Vo
MONITORING
NODE
IF
*C L IS APPROXIMATELY 15 pF WHICH
INCLUDES PROBE AND STRAY WIRING
CAPACITANCE
IF = 8.0 mA
INPUT
IF
IF = 4.0 mA
tPLH
tPHL
90%
90%
OUTPUT
Vo
1.5V
10%
10%
tF
tR
Figure 16. Test circuit for tPHL. tPLH, tF, and tR.
ACSL-6400
IF
3.3V or 5V
B
1
16
A
RL
OUTPUT Vo
MONITORING
NODE
0.1µF
BYPASS
V FF
8
9
_
+
PULSE GEN.
Zo = 50
Vcm (peak)
Vcm
0V
5V
SWITCH AT POSITION "A": IF = 0 mA
CM H
Vo
Vo (min.)
SWITCH AT POSITION "B": IF = 8 mA
Vo (max.)
Vo
0.5 V
CM L
Figure 17. Test circuit for common mode transient immunity and typical waveforms.
15
Application Information
ON and OFF Conditions
The ACSL-6xx0 series has the ON
condition defined by current, and
the OFF condition defined by
voltage. In order to guarantee that
the optocoupler is OFF, the
forward voltage across the LED
must be less than or equal to
0.8 volt for the entire operating
temperature range. This has direct
implications for the input drive
circuit. If the design uses a TTL
gate to drive the input LED, then
one has to ensure that the gate
output voltage is sufficient to
cause the forward voltage to be
less than 0.8 volt. The typical
threshold current for the
ACSL-6xx0 series optocouplers is
2.7 mA; however, this threshold
could increase over time due to
the aging effects of the LED. Drive
circuit arrangements must provide
for the ON state LED forward
current of at least 7 mA, or more
if faster operation is desired.
330Ω
Figure 18. TTL interface circuit for the ACSL-6xx0.
16
Maximum Input Current and
Reverse Voltage
The average forward input current
should not exceed the 15 mA
Absolute Maximum Rating as
stated; however, peaking circuits
with transient input currents up to
50 mA are allowed provided the
average current does not exceed
15 mA. If the input current maximum rating is exceeded, the local
temperature of the LED can rise,
which in turn may affect the longterm reliability of the device. When
designing the input circuit, one
must also ensure that the input
reverse voltage does not exceed 5 V.
If the optocoupler is subjected to
reverse voltage transients or
accidental situations that may
cause a reverse voltage to be
applied, thus an anti-parallel diode
across the LED is recommended.
Suggested Input Circuits for
Driving the LED
Figures 18, 19, and 20 show some
of the several techniques for
driving the ACSL-6xx0 LED.
Figure 18 shows the recommended circuit when using any
type of TTL gate. The buffer PNP
transistor allows the circuit to be
used with TTL or CMOS gates that
have low sinking current capability. One advantage of this circuit
is that there is very little variation
in power supply current due to
the switching of the optocoupler
LED. This can be important in
high-resolution analog-to-digital
(A/D) systems where ground loop
currents due to the switching of
the LEDs can cause distortion in
the A/D output.
With a CMOS gate to drive the
optocoupler, the circuit shown in
Figure 19 can be used. The diode
in parallel to the current limiting
resistor speeds the turn-off of the
optocoupler LED. Any HC or
HCT series CMOS gate can be
used in this circuit.
330Ω
Phase Relationship to Input
The output of the optocoupler is
inverted when compared to the
input. The input is defined to be
logic HIGH when the LED is ON.
If there is a design that requires
the optocoupler to behave as a
non-inverting gate, then the
series input drive circuit shown
in Figure 19 can be used. This
input drive circuit has an inverting function, and since the
optocoupler also behaves as an
inverter, the total circuit is noninverting. The shunt drive
circuits shown in Figures 18 and
20 will cause the optocoupler to
function as an inverter.
Figure 19. CMOS drive circuit for the
ACSL-6xx0.
For high common-mode rejection
applications, the drive circuit
shown in Figure 20 is recommended. In this circuit, only an
open-collector TTL, or an open
drain CMOS gate can be used.
This circuit drives the
optocoupler LED with a 220 ohm
current-limiting resistor to ensure
that an IF of 7 mA is applied
under worst case conditions and
thus guarantee the 10,000 V/µs
optocoupler common mode
rejection rating. The designer can
obtain even higher common-mode
rejection performance than
10,000 V/µs by driving the LED
harder than 7 mA.
Figure 21. High voltage switching with
ACSL-6xx0.
220Ω
Figure 20. High CMR drive circuit for the
ACSL-6xx0.
17
Figure 22. High voltage and high current
switching with ACSL-6xx0.
Current and Voltage Limitations
The absolute maximum voltage
allowable at the output supply
voltage pin and the output
voltage pin of the optocoupler is
7 volts. However, the recommended maximum voltage at
these two pins is 5.5 volts. The
output sinking current should not
exceed 13 mA in order to make
the Low Level Output Voltage be
less than 0.6 volt. If the output
voltage is not a consideration,
then the absolute maximum
current allowed through the
ACSL-6xx0 is 50 mA. If the
output requires switching either
higher currents or voltages,
output buffer stages as shown in
Figures 21 and 22 are suggested.
Propagation Delay, Pulse-Width
Distortion and Propagation Delay Skew
Propagation delay is a figure of
merit which describes how
quickly a logic signal propagates
through a system. The propagation delay from low to high
(tPLH) is the amount of time
required for an input signal to
propagate to the output,causing
the output to change from low to
high. Similarly,the propagation
delay from high to low (tPHL) is
the amount of time required for
the input signal to propagate to
the output causing the output to
change from high to low (see
Figure 16).
Pulse-width distortion (PWD)
results when tPLH and tPHL differ
in value. PWD is defined as the
difference between tPLH and tPHL
and often determines the maximum data rate capability of a
transmission system. PWD can be
expressed in percent by dividing
the PWD (in ns) by the minimum
pulse width (in ns) being transmitted. Typically, PWD on the order of
20-30% of the minimum pulse
width is tolerable; the exact figure
depends on the particular application (RS232, RS422, T-l, etc.).
Propagation delay skew,tPSK, is
an important parameter to
consider in parallel data applications where synchronization of
signals on parallel data lines is a
concern. If the parallel data is
Figure 23. Propagation delay skew – tPSK.
18
being sent through a group of
optocouplers, differences in
propagation delays will cause the
data to arrive at the outputs of
the optocouplers at different
times. If this difference in
propagation delays is large
enough, it will determine the
maximum rate at which parallel
data can be sent through the
optocouplers.
Propagation delay skew is
defined as the difference between the minimum and maximum propagation delays,either
tPLH or tPHL, for any given group
of optocouplers which are
operating under the same conditions (i.e., the same drive current, supply voltage, output load,
and operating temperature). As
illustrated in Figure 23, if the
inputs of a group of optocouplers
are switched either ON or OFF at
the same time, tPSK is the difference between the shortest
propagation delay,either tPLH or
tPHL, and the longest propagation delay,either tPLH or tPHL.
As mentioned earlier,tPSK can
determine the maximum parallel
data transmission rate. Figure 24
is the timing diagram of a typical
parallel data application with
both the clock and the data lines
being sent through optocouplers.
The figure shows data and clock
signals at the inputs and outputs
of the optocouplers. To obtain
the maximum data transmission
rate, both edges of the clock
signal are being used to clock the
data;if only one edge were used,
the clock signal would need to be
twice as fast.
Propagation delay skew represents the uncertainty of where
an edge might be after being sent
through an optocoupler.
Figure 24 shows that there will
be uncertainty in both the data
and the clock lines. It is important that these two areas of
uncertainty not overlap, otherwise the clock signal might arrive
before all of the data outputs
have settled,or some of the data
outputs may start to change
before the clock signal has
arrived. From these considerations, the absolute minimum
pulse width that can be sent
through optocouplers in a
parallel application is twice tPSK.
A cautious design should use a
slightly longer pulse width to
ensure that any additional
uncertainty in the rest of the
circuit does not cause a problem.
The tPSK specified optocouplers
offer the advantages of guaranteed specifications for propagation delays, pulsewidth distortion and propagation delay skew
over the recommended temperature, input current, and power
supply ranges.
Figure 24. Parallel data transmission example.
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Pte.
in the United States and other countries.
Data subject to change. Copyright © 2006 Avago Technologies Pte. All rights reserved.
Obsoletes 5989-1343EN
5989-2159EN January 16, 2006
