ADNS-3080

ADNS - 3080 High-Performance Optical Mouse Sensor Data Sheet Description The ADNS-3080 is a high performance addition to Avago Technologies’ popular ADNS family of optical mouse sensors. The ADNS-3080 is based on a new, faster architecture with improved navigation. The sensor is capable of sensing high speed mouse motion - up to 40 inches per second and acceleration up to 15g – for increased user precision and smoothness. The ADNS-3080 along with the ADNS-2120 (or ADNS-2120001) lens, ADNS-2220 (or ADNS-2220-001) assembly clip and HLMP-ED80-XX000 form a complete, compact optical mouse tracking system. There are no moving parts, which means high reliability and less maintenance for the end user. In addition, precision optical alignment is not required, facilitating high volume assembly. The sensor is programmed via registers through a four-wire serial port. It is packaged in a 20-pin staggered dual inline package (DIP). Features • High speed motion detection – up to 40 ips and 15g • New architecture for greatly improved optical navigation technology • Programmable frame rate over 6400 frames per second • SmartSpeed self-adjusting frame rate for optimum performance • Serial port burst mode for fast data transfer • 400 or 1600 cpi selectable resolution • Single 3.3 volt power supply • Four-wire serial port along with Chip Select, Power Down, and Reset pins Applications • Mice for game consoles and computer games • Mice for desktop PC’s, Workstations, and portable PC’s • Trackballs • Integrated input devices Theory of Operation The ADNS-3080 is based on Optical Navigation Technology, which measures changes in position by optically acquiring sequential surface images (frames) and mathematically determining the direction and magnitude of movement. It contains an Image Acquisition System (IAS), a Digital Signal Processor (DSP), and a four-wire serial port. The IAS acquires microscopic surface images via the lens and illumination system. These images are processed by the DSP to determine the direction and distance of motion. The DSP calculates the ∆x and ∆y relative displacement values. An external microcontroller reads the ∆x and ∆y information from the sensor serial port. The microcontroller then translates the data into PS2 or USB signals before sending them to the host PC or game console. Pinout Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name NCS MISO SCLK MOSI LED_CTRL RESET NPD OSC_OUT GUARD OSC_IN NC OPTP REFC REFB VDD3 GND VDD3 NC GND NC Description Chip select (active low input) Serial data output (Master In/Slave Out) Serial clock input Serial data input (Master Out/Slave In) LED control output Reset input Power down (active low input) Oscillator output Oscillator gnd for PCB guard (optional) Oscillator input No connect Connect to VDD3 Reference capacitor Reference capacitor Supply voltage Ground Supply voltage No connect Ground No connect NCS MISO SCLK MOSI LED_CTRL RESET NPD OSC_OUT GUARD OSC_IN 1 2 3 4 16 5 15 6 14 7 13 8 12 9 11 10 NC OPTP REFC REFB VDD3 GND TOP VIEW 20 NC GND NC VDD3 A3080 XYYWWZ 19 18 17 PINOUT Figure 1. Package outline drawing (top view) 2 Figure 2. Package outline drawing CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. 3 Overview of Optical Mouse Sensor Assembly 2D Assembly Drawing of ADNS-3080 Shown with ADNS-2120, ADNS-2220 and HLMP ED80XX000. Avago Technologies provides an IGES file drawing de scribing the base plate molding features for lens and PCB alignment. The components interlock as they are mounted onto defined features on the base plate. The ADNS-3080 sensor is designed for mounting on a through hole PCB, looking down. There is an aperture stop and features on the package that align to the lens. The ADNS-2120 lens provides optics for the imaging of the surface as well as illumination of the surface at the optimum angle. Features on the lens align it to the sensor, base plate, and clip with the LED. The lens also has a large round flange to provide a long creepage path for any ESD events that occur at the opening of the base plate. The ADNS-2220-001 clip holds the LED in relation to the lens. The LED must be inserted into the clip and the LED’s leads formed prior to loading on the PCB. The clip interlocks the sensor to the lens, and through the lens to the alignment features on the base plate. The HLMP-ED80-XX000 LED is recommended for illumination. If used with the bin table, sufficient illumination can Figure 3. Recommended PCB mechanical cutouts and spacing 4 Figure 4. 2D Assembly drawing of ADNS-3080 (top and side view) NOTE: These new Avago Technologies optical mouse sensors, lenses and clips have different physical configurations that require a different PCB mounting method to optimize the navigation performance. Refer Application Notes AN 5035 for further information. 5 PCB Assembly Considerations HLMP-ED80-XX000 (LED) ADNS-2220 (Clip) ADNS-3080 (Sensor) Customer supplied PCB ADNS-2120 (Lens) Customer supplied base plate with recommended alignment features per IGES drawing. Figure 5. Exploded view drawing 1. Insert the sensor and all other electrical components into PCB. 2. Insert the LED into the assembly clip and bend the leads 90 degrees. 3. Insert the LED/clip assembly into PCB. 4. Wave Solder the entire assembly in a no-wash solder process utilizing solder fixture. The solder fixture is needed to protect the sensor during the solder process. It also sets the correct sensor-to -PCB distance as the lead shoulders do not normally rest on the PCB surface. The fixture should be designed to expose the sensor leads to solder while shielding the optical aperture from direct solder contact. 5. Place the lens onto the base plate. 6. Remove the protective kapton tape from optical aperture of the sensor. Care must be taken to keep contaminants from entering the aperture. During mouse assembly process, it is recommended that the PCB is held vertically when kapton tapes are being removed. 7. Insert PCB assembly over the lens onto the base plate aligning post to retain PCB assembly. The sensor aperture ring should self-align to the lens. 8. The optical position reference for the PCB is set by the base plate and lens. Note that the PCB motion due to button presses must be minimized to maintain optical alignment. 9. Install mouse top case. There MUST be a feature in the top case to press down NCS SCLK MOSI MISO Serial Port OSC_IN OSCILLATOR OSC_OUT REFB REFC OPTP NPD VDD3 GND RESONATOR IMAGE PROCESSOR LED_CTRL RESET CTRL VOLTAGE REGULATOR AND POWER CONTROL REFERENCE VOLTAGE FILTER NODE 3.3 V POWER Figure 6. Block diagram of ADNS-3080 optical mouse sensor 6 Design considerations for improving ESD Performance The flange on the lens has been designed to increase the creepage and clearance distance for electrostatic discharge. The table below shows typical values assuming base plate construction per the Avago Technologies supplied IGES file and ADNS-2120 lens flange. For improved ESD performance, the lens flange can be sealed (i.e. glued) to the base plate. Note that the lens material is polycarbonate and therefore, cyanoacrylate based adhesives or other adhesives that may damage the lens should NOT be used. Typical Distance Creepage Clearance Millimeters 16.0 2.1 Clip Sensor LED PCB Lens/Light Pipe Base Plate Surface Figure 7. Cross section of PCB assembly 7 LP2950ACZ-3.3 3 Vin GND 0.1 uF 14 Vcc Vcc D+ D1.3 KΩ GND 10 16 15 Vpp D+ DP0.7* 21 P0.6 22 P0.5* 23 CYPRESS CY7C63743A-PC P0.4* 24 P0.2 3 P0.3 4 10 KΩ 10 KΩ 4.7uF + 0.1uF 2 0.1uF 0.1uF + 4.7uF 17 15 ADNS 2120 Lens Vcc Vo 1 V DD V DD Internal Image 16 GND Sensor 19 GND 3 2 4 1 6 7 SCLK MISO MOSI NCS RESET NPD ADNS-3080 5 HLMP-ED80 187Ω 1/8 W BS170 SURFACE 11 Vreg 17 P1.7 18 P1.5 LED_CTRL Vcc 3 Vcc SHLD REFC 13 + 14 10 9 8 24 MHz Ceramic Resonator Murata CSALS 24 M 0X 53 -B 0 TDK FCR 24. 0 M 2G Vo 3.3V 2.2 uF REFB OSC_IN GUARD OSC_OUT Scroll Wheel Encoder ALPS EC10E QA 1 QB 2 7 P1.4 P1.0 P1.2 P1.1 5 6 20KΩ L M Buttons 20KΩ NC NC R VSS 9 XTALOUT 13 XTALIN 12 11 18 20 6 MHz (Optional) 20kΩ 20kΩ NC 20 OPTP 12 Notes: - All capacitors close to chip - 24MHz and 6MHz oscillators close to chip - * Outputs configured as open drain Figure 8. Schematic Diagram for USB, PS/2 mouse application with ADNS-3080 Notes • Caps for pins 15 and 17 MUST have trace lengths LESS than 5 mm to nearest ground pin. • Pins 15 and 17 caps MUST use pin 16 GND. • Pin 9, if used, should not be connected to PCB GND to reduce potential RF emissions. • The 0.1 uF caps must be ceramic. • Caps should have less than 5 nH of self inductance. • Caps should have less than 0.2 Ω ESR. • NC pins should not be connected to any traces. • Surface mount parts are recommended. • Care must be taken when interfacing a 5V microcontroller to the ADNS-3080. Serial port inputs on the sensor should be connected to opendrain outputs from the microcontroller or use an active drive level shifter. NPD and RESET should be connected to 5V microcontroller outputs through a resistor divider or other level shifting technique. • VDD3 and GND should have low impedance connections to the power supply. • Capacitors connected to pin 15 and 17 should be connected to pin 16 and then to pin 19. 8 Enabling the SROM For best tracking performance,SROM is required to be loaded into ADNS-3080. This architecture enables immediate adoption of new features and improved performance algorithms. The external program is supplied by Avago Technologies as a file which may be burned into a programmable device. A micro-controller with sufficient memory may be used. On power-up and reset, the ADNS-3080 program is downloaded into volatile memory using the burst-mode procedure described in the Synchronous Serial Port section. The program size is 1986 x 8 bits. Regulatory Requirements • Passes FCC B and worldwide analogous emission limits when assembled into a mouse with shielded cable and following Avago Technologies’ recommendations. • Passes IEC-1000-4-3 radiated susceptibility level when assembled into a mouse with shielded cable and following Avago Technologies’ recommendations. • Passes EN61000-4-4/IEC801-4 EFT tests when assembled into a mouse with shielded cable and following Avago Technologies’ recommendations. • UL flammability level UL94 V-0. • Provides sufficient ESD creepage/clearance distance to avoid discharge up to 15kV when assembled into a mouse according to usage instructions above. Sensor Lens 2.40 0.094 Object Surface Figure 9. Distance from lens reference plane to surface 9 Absolute Maximum Ratings Parameter Storage Temperature Operating Temperature Lead Solder Temp Supply Voltage ESD Input Voltage Output current VIN Iout -0.5 VDD3 -0.5 Symbol TS TA Minimum Typical -40 -15 Maximum 85 55 260 3.7 2 VDD3+0.5 20 Units oC oC oC Notes For 10 seconds, 1.6mm below seating plane. V kV V mA All pins, human body model MIL 883 Method 3015 NPD, NCS, MOSI, SCLK, RESET, OSC_IN, OSC_OUT, REFC. LED_CTRL, MISO Recommended Operating Conditions Parameter Operating Temperature Power supply voltage Power supply rise time Supply noise (Sinusoidal) Oscillator capable Frequency Serial Port Clock Frequency Resonator Impedance Distance from lens reference plane to surface Speed Acceleration Light level onto IC Symbol TA VDD3B VRT VNB fCLK fSCLK Minimum Typical Maximum 0 3.10 1 30 80 23 24 25 2 500 55 2.3 2.4 2.5 3.30 40 3.60 Units °C Volts us mV p-p MHz MHz kHz W mm Notes 0 to 3.0V 10kHz- 300KHZ 300KHz-50MHz Set by ceramic resonator Active drive, 50% duty cycle Open drain drive with pull-ups on, 50 pF load XRES Z Results in ±0.2 mm DOF, See drawing below @ 6469fps @ 6469fps l = 639 nm, FR=1500 fps l = 875 nm, FR=1500 fps l = 639 nm, FR=6469 fps l = 875 nm, FR=6469 fps See Frame_Period register section HLMP-ED80-XX000, bin N and brighter. Maximum frame rate may not be maintained on dark surfaces at the minimum LED drive current S A IRRINC 0 40 15 in/sec g mW/m2 20 24 100 120 2000 10 6,000 7,200 6,000 7,200 6469 Frame Rate LED Drive Current FR ILED Frames/s mA 10 AC Electrical Specifications Electrical Characteristics over recommended operating conditions. Typical values at 25 °C, VDD3=3.3V, fclk=24MHz. Parameter VDD to RESET Data delay after RESET Input delay after reset Power Down Wake from NPD Symbol tOP tPU-RESET TIN-RST tPD tPUPD Min. Typical Max. 250 35 500 2.1 75 Units ms ms ms ms ms Notes From VDD = 3.0V to RESET sampled From RESET falling edge to valid motion data at 2000 fps and shutter bound 8290. From RESET falling edge to inputs active (NPD, MOSI, NCS, SCLK) From NPD falling edge to initiate the power down cycle at 500fps (tpd = 1 frame period + 100ms ) From NPD rising edge to valid motion data at 2000 fps and shutter bound 8290. Max assumes surface change while NPD is low. From NPD rising edge to all registers contain data from new images at 2000fps (see Figure 10) . CL = 50pF CL = 50pF From SCLK falling edge to MISO data valid, no load conditions Data held until next falling SCLK edge Amount of time data is valid after SCLK rising edge From data valid to SCLK rising edge From rising SCLK for last bit of the first data byte, to rising SCLK for last bit of the second data byte. From rising SCLK for last bit of the first data byte, to rising SCLK for last bit of the second address byte. From rising SCLK for last bit of the first data byte, to falling SCLK for first bit of the second address byte. From rising SCLK for last bit of the address byte, to falling SCLK for first bit of data being read. All registers except Motion & Motion_Burst From rising SCLK for last bit of the address byte, to falling SCLK for first bit of data being read. Applies to 0x02 Motion, and 0x50 Motion_Burst, registers From NCS falling edge to first SCLK rising edge From last SCLK falling edge to NCS rising edge, for valid MISO data transfer From NCS rising edge to MISO high-Z state (see Figure 23 and 24) Data delay after NPD RESET pulse width MISO rise time MISO fall time MISO delay afterSCLK MISO hold time MOSI hold time MOSI setup time SPI time between write commands SPI time between write and read commands tCOMPUTE tPW-RESET tr-MISO tf-MISO tDLY-MISO thold-MISO thold-MOSI tsetup-MOSI tSWW tSWR 250 200 120 50 50 10 40 40 3.1 ms ms 200 200 120 ns ns ns ns ns ns ms ms SPI time between tSRW read and subsequent tSRR commands SPI read address-data delay SPI motion read address-data delay NCS to SCLK active SCLK to NCS inactive NCS to MISO high-Z tSRAD 250 ns 50 ms tSRAD-MOT 75 ms tNCS-SCLK tSCLK-NCS tNCS-MISO 120 120 250 10 ns ns ns ms SROM download and tLOAD frame capture byte-to-byte delay NCS to burst mode exit Transient Supply Current tBEXIT 4 ms Time NCS must be held high to exit burst mode IDDT 85 mA Max supply current during a VDD3 ramp from 0 to 3.6V 11 DC Electrical Specifications Electrical Characteristics over recommended operating conditions. Typical values at 25 °C, VDD3=3.3V, fclk=24MHz. Parameter DC Supply Current Power Down Supply Current Input Low Voltage Input High Voltage Input hysteresis Input current, pull-up disabled Input current, CMOS inputs Output current, pulled-up inputs Output Low Voltage LED_CTRL Output High voltage, LED_CTRL Output Low Voltage, MISO Output High Voltage, MISO Input Capacitance Symbol Minimum Typical Maximum Units Notes IDD_AVG IDDPD VIL VIH VI_HYS IIH_DPU IIH IOH_PU VOL,LED 150 0.7 * VDD3 200 0 0 300 ±10 ±10 600 0.5 5 52 90 0.8 mA mA V V mV mA mA mA V DC average at 6469 fps. No DC load on LED_CTRL, MISO. NPD=GND; SCLK, MOSI, NCS=GND or VDD3; RESET=GND SCLK, MOSI, NPD, NCS, RESE SCLK, MOSI, NPD, NCS, RESET SCLK, MOSI, NPD, NCS, RESET Vin=0.8*VDD3, SCLK, MOSI, NCS NPD, RESET, Vin=0.8*VDD3 Vin=0.2V, SCLK, MOSI, NCS Iout=2mA, LED_CTRL VOH_LED 0.8*VDD3 V Iout=-2mA, LED_CTRL VOL VOH CIN 0.8*VDD3 14-22 0.5 V V pF Iout=2mA, MISO Iout=-2mA, MISO OSC_IN, OSC_OUT Detail of NPD rising edge timing NPD Reset Count Oscillator Start 250 us LED CURRENT (shutter mode) SCLK 590 us Optional SPI trans actions with old image data tCOMPUTE = 590us + 5 Frame Periods “Motion” bit set if motion was detected. First read dX = dY = 0 340 us Frame 1 Frame 2 Frame 3 Frame 4 Frame 5 Figure 10. NPD Rising Edge Timing Detail 12 Typical Performance Characteristics Mean Resolution vs. Z (White Paper) 2000 1800 1600 Resolution (counts/inch) 1400 1200 1000 800 600 400 200 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 -0. -0. -0. -0. -0. -0. -0. 0.8 8 7 6 5 4 3 2 1 White Paper Manila Burl Z DOF DOF Black Walnut Black Copy OPERATING REGION Distance from Nominal Focus (mm) Figure 11. Mean Resolution vs. Z (White Paper) Maximum Distance (Mouse Count) 50 45 40 35 30 25 20 15 10 5 0 1.6 Typical Path Deviation Largest Single Perpendicular Deviation From A Straight Line At 45 Degrees Path length = 4 inches; Speed = 6 ips; Resolution = 1600 cpi White Paper Manila Burl Black Walnut Black Copy 1.8 2.0 2.2 -0. 2.4 2.6 2.8 3.0 3.2 Distance From Lens Reference Plane To Navigation Surface (mm) Relationship of mouse count to distance = m (mouse count) / n (cpi) eg: Deviation of 7 mouse count = 7/1600 = 0.004375 inch ~ 0.004 inch where m = 7, n = 1600 Figure 12. Average error vs. Distance (mm) 13 1 0.9 0.8 Relative responsivity 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 400 500 600 700 wavelength (nm) 800 900 1000 Figure 13. Relative responsivity 120% 100% 80% 60% 40% 20% 0% 0 Average Supply Current vs Frame Rate VDD=3.6V 100% 88% 72% 51% 55% Relative Current 2000 4000 Frame Rate (Hz) 6000 8000 Figure 14. Idd vs. Frame Rate 14 Synchronous Serial Port The synchronous serial port is used to set and read parameters in the ADNS-3080, and to read out the motion information. The serial port is also used to load SROM data into the ADNS-3080. The port is a four-wire, serial port. The host micro-controller always initiates communication; the ADNS-3080 never initiates data transfers. The serial port cannot be activated while the chip is in power down mode (NPD low) or reset (RESET high). SCLK, MOSI, and NCS may be driven directly by a 3.3V output from a micro-controller, or they may be placed in an open drain configuration by enabling on-chip pull-up current sources. The open drain drive allows the use of a 5V micro-controller without any level shifting components. The port pins may be shared with other SPI slave devices. When the NCS pin is high, the inputs are ignored and the output is tri-stated. The lines which comprise the SPI port are: SCLK: Clock input. It is always generated by the master (the micro- controller). MOSI: Input data (Master Out/Slave In). MISO: Output data (Master In/Slave Out). NCS: Chip select input (active low). NCS needs to be low to activate the serial port; otherwise, MISO will be high-Z, and MOSI & SCLK will be ignored. NCS can also be used to reset the serial port in case of an error. Chip Select Operation The serial port is activated after NCS goes low. If NCS is raised during a transaction, the entire transaction is aborted and the serial port will be reset. This is true for all transactions including SROM download. After a transaction is aborted, the normal address-to-data or transaction-to-transaction delay is still required before beginning the next transaction. To improve communication reliability, all serial transactions should be framed by NCS. In other words, the port should not remain enabled during periods of non-use because ESD and EFT/B events could be interpreted as serial communication and put the chip into an unknown state. In addition, NCS must be raised after each burst-mode transaction is complete to terminate burst-mode. The port is not available for further use until burst-mode is terminated. 15 Write Operation Write operation, defined as data going from the microcontroller to the ADNS-3080, is always initiated by the micro-controller and consists of two bytes. The first byte contains the address (seven bits) and has a “1” as its MSB to indicate data direction. The second byte contains the data. The ADNS-3080 reads MOSI on rising edges of SCLK. Read Operation A read operation, defined as data going from the ADNS3080 to the micro-controller, is always initiated by the micro-controller and consists of two bytes. The first byte contains the address, is sent by the micro-controller over MOSI, and has a “0” as its MSB to indicate data direction. The second byte contains the data and is driven by the ADNS-3080 over MISO. The sensor outputs MISO bits on falling edges of SCLK and samples MOSI bits on every rising edge of SCLK. NOTE: The 250 ns minimum high state of SCLK is also the minimum MISO data hold time of the ADNS-3080. Since the falling edge of SCLK is actually the start of the next read or write command, the ADNS-3080 will hold the state of data on MISO until the falling edge of SCLK. SCLK MOSI tHold,MOSI tSetup, MOSI SCLK tDLY-MISO MISO D0 tHOLD-MISO Figure 15. MOSI setup and hold time NCS Figure 18. MISO delay and hold time 1 SCLK MOSI MISO 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 1 A 6 A 5 A 4 A 3 A 2 A 1 A 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 1 A 6 MOSI Driven by Micro-Controller Figure 16. Write Operation NCS SCLK Cycle # SCLK MOSI MISO 0 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Figure 17. Read operation tSRAD delay 16 Required timing between Read and Write Commands (tsxx) There are minimum timing requirements between read and write commands on the serial port. tSWW ≥ 50µs SCLK Address Write Operation Data Address Write Operation Data Figure 19. Timing between two write commands If the rising edge of the SCLK for the last data bit of the second write command occurs before the 50 microsecond required delay, then the first write command may not complete correctly. tSWR ≥ 50µs SCLK Address Write Operation Data Address Next Read Operation Figure 20. Timing between write and read commands If the rising edge of SCLK for the last address bit of the read command occurs before the 50 microsecond required delay, the write command may not complete correctly. tSRAD ≥ 50 µs for non-motion read tSRAD-MOT ≥ 75 µs for register 0x02 tSRW & tSRR > 250 ns SCLK Address Read Operation Data Address Next Read or Write Operation Figure 21. Timing between read and either write or subsequent read commands The falling edge of SCLK for the first address bit of either the read or write command must be at least 250 ns after the last SCLK rising edge of the last data bit of the previous read operation. In addition, during a read operation SCLK should be delayed after the last address bit to ensure that the ADNS-3080 has time to prepare the requested data. 17 Burst Mode Operation Burst mode is a special serial port operation mode which may be used to reduce the serial transaction time for three predefined operations: motion read and SROM download and frame capture. The speed improvement is achieved by continuous data clocking to or from multiple registers without the need to specify the register address, and by not requiring the normal delay period between data bytes. Motion Read This mode is activated by reading the Motion_Burst register. The ADNS-3080 will respond with the contents of the Motion, Delta_X, Delta_Y, SQUAL, Shutter_Upper, Shutter_Lower and Maximum_Pixel registers in that order. After sending the register address, the microcontroller must wait tSRAD-MOT and then begin reading data. All 56 data bits can be read with no delay between bytes by driving SCLK at the normal rate. The data are latched into the output buffer after the last address bit is received. After the burst transmission is complete, the micro-controller must raise the NCS line for at least tBEXIT to terminate burst mode. The serial port is not available for use until it is reset with NCS, even for a second burst transmission. tSRAD-MOT ≥ 75 µs SCLK Motion_Burst Register Address Read First Byte Read Second Byte Read Third Byte First Read Operation Figure 22. Motion burst timing 18 SROM Download This function is used to load the Avago Technologiessupplied firmware file contents into the ADNS-3080. The firmware file is an ASCII text file with each 2-character byte (hexadecimal representation) on a single line. This mode is activated by the following steps: 1. Perform hardware reset by toggling the RESET pin 2. Write 0x44 to register 0x20 3. Write 0x07 to register 0x23 4. Write 0x88 to register 0x24 5. Wait at least 1 frame period 6. Write 0x18 to register 0x14 (SROM_Enable register) 7. Begin burst mode write of data file to register 0x60 (SROM_Load register) After the first data byte is complete, the SROM or microcontroller must write subsequent bytes by presenting the data on the MOSI line and driving SCLK at the normal rate. A delay of at least tLOAD must exist between data bytes as shown. After the download is complete, the micro-controller must raise the NCS line for at least tBEXIT to terminate burst mode. The serial port is not available for use until it is reset with NCS, even for a second burst transmission. Avago Technologies recommends reading the SROM_ID register to verify that the download was successful. In addition, a self-test may be executed, which performs a CRC on the SROM contents and reports the results in a register. The test is initiated by writing a particular value to the SROM_Enable register; the result is placed in the Data_Out register. See those register descriptions for more details. Avago Technologies provides the data file for download; the file size is 1986 data bytes. The chip will ignore any additional bytes written to the SROM_Load register after the SROM file. SROM file is now available for download at Avago Technologies’ website. exit burst mode tBEXIT ≥4µs NCS 3 reg writes, see text MOSI ≥1 frame period SROM_Enable reg write address key data SROM_Load reg write address byte 0 enter burst mode byte 1 byte 1985 address SCLK tNCS-SCLK >120ns ≥40µs ≥10µs tLOAD tLOAD ≥10µs ≥10µs ≥100µs soonest to read SROM_ID Figure 23. SROM download burst mode 19 Frame Capture This is a fast way to download a full array of pixel values from a single frame. This mode disables navigation and overwrites any downloaded firmware. A hardware reset is required to restore navigation, and the firmware must be reloaded afterwards if required. To trigger the capture, write to the Frame_Capture register. The next available complete 1 2/3 frames (1536 values) will be stored to memory. The data are is retrieved by reading the Pixel_Burst register once using the normal read method, after which the remaining bytes are clocked out by driving SCLK at the normal rate. The byte time must be at least tLOAD. If the Pixel_ Burst register is read before the data is ready, it will return all zeros. To read a single frame, read a total of 900 bytes. The next 636 bytes will be approximately 2/3 of the next frame. The first pixel of the first frame (1st read) has bit 6 set to 1 as a start-of-frame marker. The first pixel of the second partial frame (901st read) will also have bit 6 set to 1. All other bytes have bit 6 set to zero. The MSB of all bytes is set to 1. If the Pixel_Burst register is read past the end of the data (1537 reads and on) , the data returned will be zeros. After the download is complete, the micro-controller must raise the NCS line for at least tBEXIT to terminate burst mode. The read may be aborted at any time by raising NCS. Alternatively, the frame data can also be read one byte at a time from the Frame_Capture register. See the register description for more information. exit burst mode tBEXIT ≥4µs NCS frame capture reg write MOSI address data pixel dump reg read address enter burst mode SCLK tNCS-SCLK >120ns MISO P0 bit 6 set to 1 tCAPTURE tSRAD ≥50µs ≥10µs frame capture reg address soonest to begin again ≥10µs tLOAD ≥10µs tLOAD P1 P0 P899 see note 2 all MSB = 1 Notes: 1. MSB = 1 for all bytes. Bit 6 = 0 for all bytes except pixel 0 of both frames which has bit 6 = 1 for use as a frame marker. 2. Reading beyond pixel 899 will return the first pixel of the second partial frame. 3. tCAPTURE = 10µs + 3 frame periods. 4. This figure illustrates reading a single co mplete frame of 900 pixels. An additional 636 pixels from the next frame are available. Figure 24. Frame capture burst mode timing 20 The pixel output order as related to the surface is shown below. Cable Top Xray View of Mouse Positive Y LB RB Positive X 1 A3080 20 10 11 expanded view of the surface as viewed through the lens last output 899 898 897 896 895 894 893 892 891 890 889 888 887 886 885 884 883 882 881 880 879 878 877 876 875 874 873 872 871 870 869 868 867 866 865 864 863 862 861 860 859 858 857 856 855 854 853 852 851 850 849 848 847 846 845 844 843 842 841 840 • • 839 838 • etc. 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 • 4 • 3 • 2 61 60 1 0 37 36 35 34 33 32 31 30 first output Figure 25. Pixel address map (surface referenced) Error detection and recovery 1. The ADNS-3080 and the micro-controller might get out of synchronization due to ESD events, power supply droops or micro-controller firmware flaws. In such a case, the micro-controller should pulse NCS high for at least 1 ms. The ADNS-3080 will reset the serial port (but not the control registers) and will be prepared for the beginning of a new transmission after the normal transaction delay. 2. Invalid addresses: Writing to an invalid address will have no effect. Reading from an invalid address will return all zeros. 3. Termination of a transmission by the micro-controller may sometimes be required (for example, due to a USB suspend interrupt during a read operation). To accomplish this the micro-controller should raise NCS. The ADNS-3080 will not write to any register and will reset the serial port (but not the control registers) and be prepared for the beginning of future transmissions after NCS goes low. The normal delays between reads or writes (tSWW, tswr, tSRAD, tSRAD-mot) are still required after aborted transmissions. 21 4. The micro-controller can verify success of write operations by issuing a read command to the same address and comparing written data to read data. 5. The micro-controller can verify the synchronization of the serial port by periodically reading the product ID and inverse product ID registers. 6. The microcontroller can read the SROM_ID register to verify that the sensor is running downloaded SROM code. ESD or similar noise events may cause the sensor to revert to native ROM execution. If this should happen, pulse RESET and reload the SROM instructions. Notes on Power-up and the serial port Reset Circuit The ADNS-3080 does not perform an internal power up self-reset. The reset pin must be raised and lowered to reset the chip. This should be done every time power is applied. During power-up there will be a period of time after the power supply is high but before any clocks are available. The table below shows the state of the various pins during power-up and reset when the RESET pin is driven high by a micro-controller. The chip is put into the power down (PD) mode by lowering the NPD input. When in PD mode, the oscillator is stopped but all register contents are retained. To achieve the lowest current state, all inputs must be held externally within 200mV of a rail, either ground or VDD3. The chip outputs are driven low or hi-Z during PD to prevent current consumption by an external load. LED Drive Mode The LED has 2 modes of operation: DC and Shutter. In DC mode it is on at all times the chip is powered except when in the power down mode via the NPD pin. In shutter mode the LED is on only during the portion of the frame that light is required. The LED_MODE bit in the Configuration_bits register sets the LED mode. Power Down Circuit The following table lists the pin states during power down. State of Signal Pins After VDD is Valid Pin SPI pullups NCS MISO SCLK MOSI LED_CTRL RESET NPD Before Reset Undefined Hi-Z control functional Driven or hi-Z (per NCS) Undefined Undefined Undefined Functional Undefined During Reset Off Hi-Z control functional Driven or hi-Z (per NCS) Ignored Ignored Low High (externally driven) Ignored After Reset On (default) Functional Low or hi-Z (per NCS) Functional Functional High Functional Functional State of Signal Pins During Power Down Pin SPI pullups NCS MISO SCLK MOSI LED_CTRL RESET NPD REFC OSC_IN OSC_OUT 22 NPD low off hi-Z control functional low or hi-Z (per NCS) ignored ignored low functional low (driven externally) VDD3 low high After wake from PD pre-PD state functional pre-PD state or hi-Z functional functional high functional functional REFC OSC_IN OSC_OUT Registers The ADNS-3080 registers are accessible via the serial port. The registers are used to read motion data and status as well as to set the device configuration. Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20-0x3c 0x3d 0x3e 0x3f 0x40 0x50 0x60 Register Product_ID Revision_ID Motion Delta_X Delta_Y SQUAL Pixel_Sum Maximum_Pixel Reserved Reserved Configuration_bits Extended_Config Data_Out_Lower Data_Out_Upper Shutter_Lower Shutter_Upper Frame_Period_Lower Frame_Period_Upper Motion_Clear Frame_Capture SROM_Enable Reserved Reserved Reserved Reserved Frame_Period_Max_Bound Lower Frame_Period_Max_Bound_Upper Frame_Period_Min_Bound_Lower Frame_Period_Min_Bound_Upper Shutter_Max_Bound_Lower Shutter_Max_Bound_Upper SROM_ID Reserved Observation Reserved Inverse Product ID Pixel_Burst Motion_Burst SROM_Load Read/Write R R R R R R R R SROM Default Value 0x17 0xNN 0x00 0x00 0x00 0x00 0x00 0x00 R/W R/W R R R R R R W R/W W 0x09 0x00 Any Any 0x85 0x00 Any Any Any 0x00 0x00 R/W R/W R/W R/W R/W R/W R R/W R R R W 0xE0 0x2E 0x7E 0x0E 0x00 0x20 0x00 0x00 0xF8 0x00 0x00 Any 23 Product_ID Access: Read Bit Field 7 PID7 6 PID6 Address: 0x00 Reset Value: 0x17 5 PID5 4 PID4 3 PID3 2 PID2 1 PID1 0 PID0 Data Type: 8-Bit unsigned integer USAGE: This register contains a unique identification assigned to the ADNS-3080. The value in this register does not change; it can be used to verify that the serial communications link is functional. Revision_ID Access: Read Bit Field 7 RID7 6 RID6 Address: 0x01 Reset Value: 0xNN 5 RID5 4 RID4 3 RID3 2 RID2 1 RID1 0 RID0 Data Type: 8-Bit unsigned integer. USAGE: This register contains the IC revision. It is subject to change when new IC versions are released. NOTE: The downloaded SROM firmware revision is a separate value and is available in the SROM_ID register. Motion Access: Read Bit Field 7 MOT 6 Reserved Address: 0x02 Reset Value: 0x00 5 Reserved 4 OVF 3 Reserved 2 Reserved 1 Reserved 0 RES Data Type: Bit field. USAGE: Register 0x02 allows the user to determine if motion has occurred since the last time it was read. If so, then the user should read registers 0x03 and 0x04 to get the accumulated motion. It also tells if the motion buffers have overflowed, and the current resolution setting. Field Name MOT Reserved Reserved OVF Description Motion since last report or PD 0 = No motion 1 = Motion occurred, data ready for reading in Delta_X and Delta_Y registers Reserved Reserved Motion overflow, Delta_Y and/or Delta_X buffer has overflowed since last report 0 = no overflow 1 = Overflow has occurred Reserved Reserved Reserved Resolution in counts per inch 0 = 400 1 = 1600 Reserved Reserved Reserved RES 24 Notes for Motion: 1. Reading this register freezes the Delta_X and Delta_Y register values. Read this register before reading the Delta_X and Delta_Y registers. If Delta_X and Delta_Y are not read before the motion register is read a second time, the data in Delta_X and Delta_Y will be lost. 2. Avago Technologies RECOMMENDS that registers 0x02, 0x03 and 0x04 be read sequentially. See Motion burst mode also. 3. Internal buffers can accumulate more than eight bits of motion for X or Y. If either one of the internal buffers overflows, then absolute path data is lost and the OVF bit is set. This bit is cleared once some motion has been read from the Delta_X and Delta_Y registers, and if the buffers are not at full scale. Since more data is present in the buffers, the cycle of reading the Motion, Delta_X and Delta_Y registers should be repeated until the motion bit (MOT) is cleared. Until MOT is cleared, either the Delta_X or Delta_Y registers will read either positive or negative full scale. Delta_X Access: Read Bit Field 7 X7 6 X6 Address: 0x03 Reset Value: 0x00 5 X5 4 X4 3 X3 2 X2 1 X1 0 X0 Data Type: Eight bit 2’s complement number. USAGE: X movement is counts since last report. Absolute value is determined by resolution. Reading clears the register. Motion -128 -127 -2 -1 0 +1 +2 +126 +127 Delta_X 80 81 FE FF 00 01 02 7E 7F Delta_Y Access: Read Bit Field 7 Y7 6 Y6 Address: 0x04 Reset Value: 0x00 5 Y5 4 Y4 3 Y3 2 Y2 1 Y1 0 Y0 Data Type: Eight bit 2’s complement number. USAGE: Y movement is counts since last report. Absolute value is determined by resolution. Reading clears the register. Motion -128 -127 -2 -1 0 +1 +2 +126 +127 Delta_Y 80 81 FE FF 00 01 02 7E 7F 25 SQUAL Access: Read Bit Field 7 SQ7 6 SQ6 Address: 0x05 Reset Value: 0x00 5 SQ5 4 SQ4 3 SQ3 2 SQ2 1 SQ1 0 SQ0 Data Type: Upper 8 bits of a 10-bit unsigned integer. USAGE: SQUAL (Surface Quality) is a measure of ¼ of the number of valid* features visible by the sensor in the current frame. Use the following formula to find the total number of valid features. Number of features = SQUAL register value *4 The maximum SQUAL register value is 169. Since small changes in the current frame can result in changes in SQUAL, variations in SQUAL when looking at a surface are expected. The graph below shows 250 sequentially acquired SQUAL values, while a sensor was moved slowly over white paper. SQUAL is nearly equal to zero, if there is no surface below the sensor. SQUAL is typically maximized when the navigation surface is at the optimum distance from the imaging lens (the nominal Z-height). Squal Values (White Paper) 85 80 SQUAL Value 75 70 65 60 0 25 50 75 100 125 150 175 200 225 250 Figure 26. Squal values (white paper) 26 90 80 70 60 SQUAL 50 40 30 20 10 0 -1.0 -0.8 -0.6 Mean SQUAL vs Z (White Paper) Avg Avg - 3sigma Avg + 3sigma -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 Delta from Nominal Focus (mm) Figure 27. Mean squal vs. Z (white paper) Pixel_Sum Access: Read Bit Field 7 AP7 6 AP6 Address: 0x06 Reset Value: 0x00 5 AP5 4 AP4 3 AP3 2 AP2 1 AP1 0 AP0 Data Type: High 8 bits of an unsigned 16-bit integer. USAGE: This register is used to find the average pixel value. It reports the upper byte of a 16-bit counter which sums all 900 pixels in the current frame. It may be described as the full sum divided by 256. To find the average pixel value, use the following formula: Average Pixel = Register Value * 256 / 900 = Register Value/3.51 The maximum register value is 221 (63 * 900/256 truncated to an integer). The minimum is 0. The pixel sum value can change on every frame. Maximum_Pixel Access: Read Bit Field 7 0 6 0 Address: 0x07 Reset Value: 0x00 5 MP5 4 MP4 3 MP3 2 MP2 1 MP1 0 MP0 Data Type: Six bit number. USAGE: Maximum Pixel value in current frame. Minimum value = 0, maximum value = 63. The maximum pixel value can vary with every frame. Reserved Reserved Address: 0x08 Address: 0x09 27 Configuration_bits Access: Read/Write Bit Field 7 0 6 LED_MODE Address: 0x0a Reset Value: 0x09 5 Sys Test 4 RES 3 Reserved 2 Reserved 1 Reserved 0 Reserved Data Type: Bit field USAGE: Register 0x0a allows the user to change the configuration of the sensor. Shown below are the bits, their default values, and optional values. Field Name BIT 7 LED_MODE Description Must always be zero LED Shutter Mode 0 = Shutter mode off (LED always on) 1 = Shutter mode on (LED only on when illumination is required) System Tests 0 = no tests 1 = perform all system tests, output 16 bit CRC via Data_Out_Upper and Data_Out_Lower registers. NOTE: The test will fail if SROM is loaded. Perform a hardware reset before executing this test. Reload SROM after the test is completed. NOTE: Since part of the system test is a RAM test, the RAM and SRAM will be overwritten with the default values when the test is done. If any configuration changes from the default are needed for operation, make the changes AFTER the system test is run. The system test takes 200ms (@24MHz) to complete. NOTE: Do not access the Synchronous Serial Port during system test. RES Resolution in counts per inch 0 = 400 1 = 1600 Reserved Reserved Reserved Reserved Sys Test Reserved Reserved Reserved Reserved 28 Extended_Config Access: Read/Write Bit Field 7 Busy 6 Reserved 5 Address: 0x0b Reset Value: 0x00 4 Reserved 3 Reserved 2 Serial_NPU 1 NAGC 0 Fixed_FR Reserved Data Type: Bit field USAGE: Register 0x0b allows the user to change the configuration of the sensor. Shown below are the bits, their default values, and optional values. Field Name Busy Description Read-only bit. Indicates if it is safe to write to one or more of the following registers: Frame_Period_Max_Bound_Upper and Lower Frame_Period_Min_Bound_Upper and Lower Shutter_Max_Bound_Upper and Lower After writing to the Frame_Period_Max_Bound_Upper register, at least two frames must pass before writing again to any of the above registers. This bit may be used in lieu of a timer since the actual frame rate may not be known when running in auto mode. 0 = writing to the registers is allowed 1 = do not write to the registers yet Reserved Reserved Reserved Reserved Disable serial port pull-up current sources 0 = no, current sources are on 1 = yes, current sources are off Disable AGC. Shutter will be set to the value in the Shutter_Max_Bound registers. 0 = no, AGC is active 1 = yes, AGC is disabled Fixed frame rate (disable automatic frame rate control). When this bit is set, the frame rate will be determined by the value in the Frame_Period_Max_Bound registers. 0 = automatic frame rate 1 = fixed frame rate Reserved Reserved Reserved Reserved Serial_NPU NAGC Fixed_FR 29 Data_Out_Lower Access: Read Bit Field 7 DO7 6 DO6 Address: 0x0c Reset Value: Undefined 5 DO5 4 DO4 3 DO3 2 DO2 1 DO1 0 DO0 Data_Out_Upper Access: Read Bit Field 7 DO15 6 DO14 Address: 0x0d Reset Value: Undefined 5 DO13 4 DO12 3 DO11 2 DO10 1 DO9 0 DO8 Data Type: Sixteen bit word. USAGE: Data in these registers come from the system self test or the SROM CRC test. The data can be read out 0x0d, or 0x0d first, then 0x0c. Data_Out_Upper System test results: SROM CRC Test Result: 0x1B 0xBE Data_Out_Lower 0xBF 0xEF System Test: This test is initiated via the Configuration_Bits register. It performs several tests to verify that the hardware is functioning correctly. Perform a hardware reset just prior to running the test. SROM contents and register settings will be lost. SROM CRC Test: Performs a CRC on the SROM contents. The test is initiated by writing a particular value to the SROM_Enable register. Shutter_Lower Access: Read Bit Field 7 S7 6 S6 Address: 0x0e Reset Value: 0x85 5 S5 4 S4 3 S3 2 S2 1 S1 0 S0 Shutter_Upper Access: Read Bit Field 7 S15 6 S14 5 Address: 0x0f Reset Value: 0x00 4 S12 3 S11 2 S10 1 S9 0 S8 S13 Data Type: Sixteen bit unsigned integer. USAGE: Units are clock cycles. Read Shutter_Upper first, then Shutter_Lower. They should be read consecutively. The shutter is adjusted to keep the average and maximum pixel values within normal operating ranges. The shutter value is checked and automatically adjusted to a new value if needed on every frame when operating in default mode. When the shutter adjusts, it changes by ± 1/16 of the current value. The shutter value can be set manually by setting the AGC mode to Disable using the Extended_Config register and writing to the Shutter_Maximum_Bound registers. Because the automatic frame rate feature is related to shutter value. It may also be appropriate to enable the Fixed Frame Rate mode using the Extended_Config register. Shown below is a graph of 250 sequentially acquired shutter values, while the sensor was moved slowly over white paper. 30 Mean Shutter vs Z (White Paper) 120 100 Shutter value (counts) 80 60 40 Avg 20 0 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 Distance from Nominal Focus (mm) Figure 28. Mean shutter vs. Z (white paper) Avg - 3sigma Avg + 3sigma The maximum value of the shutter is dependent upon the setting in the Shutter_Max_Bound_ Upper and Shutter_Max_Bound_Lower registers. 31 Frame_Period_Lower Access: Read Bit Field 7 FP7 6 FP6 5 Address: 0x10 Reset Value: Undefined 4 FP4 3 FP3 2 FP2 1 FP1 0 FP0 FP5 Frame_Period_Upper Access: Read Bit Field 7 FP15 6 FP14 Address: 0x11 Reset Value: Undefined 5 FP13 4 FP12 3 FP11 2 FP10 1 FP9 0 FP8 Data Type: Sixteen bit unsigned integer. USAGE: Read these registers to determine the current frame period and to calculate the frame rate. Units are clock cycles. The formula is Frame Rate = Clock Frequency/Register value To read from the registers, read Frame_Period_Upper first followed by Frame_Period Lower. To set the frame rate manually, disable automatic frame rate mode via the Extended_Config register and write the desired count value to the Frame_Period_Maximum_Bound registers. The following table lists some Frame_Period values for popular frame rates with a 24MHz clock. Frames/second 6469 5000 3000 2000 Counts Decimal 3,710 4,800 8,000 12,000 Hex OE7E 12C0 1F40 2EE0 Upper OE 12 1F 2E Frame_Period Lower 7E C0 40 E0 Motion_Clear Access: Write Data Type: Any. Address: 0x12 Reset Value: Undefined USAGE: Writing any value to this register will cause the Delta_X, Delta_Y, and internal motion registers to be cleared. Use this as a fast way to reset the motion counters to zero without resetting the entire chip. 32 Frame_Capture Access: Read/Write Bit Field 7 FC7 6 FC6 Address: 0x13 Reset Value: 0x00 5 FC5 4 FC4 3 FC3 2 FC2 1 FC1 0 FC0 Data Type: Bit field USAGE: Writing 0x83 to this register will cause the next available complete 1 2/3 frames of pixel values to be stored to SROM RAM. Writing to this register is required before using the Frame Capture burst mode to read the pixel values (see the Synchronous Serial Port section for more details). Writing to this register will stop navigation and cause any firmware loaded in the SROM to be overwritten. A hardware reset is required to restore navigation, and the firmware must be reloaded using the SROM Download burst method. This register can also be used to read the frame capture data. The same data available by reading the Pixel_Burst register using burst mode is available by reading this register in the normal fashion. The data pointer is automatically incremented after each read so all 1536 pixel values (1 and 2/3 frames) may be obtained by reading this register 1536 times in a row. Both methods share the same pointer such that reading pixel values from this register will increment the pointer causing subsequent reads from the Pixel_Burst register (without initiating a new frame dump) to start at the current pointer location. This register will return all zeros if read before the frame capture data is ready. See the Frame Capture description in the Synchronous Serial Port section for more information. This register will not retain the last value written. Reads will return zero or frame capture data. SROM_Enable Access: Write Bit Field 7 SE7 6 SE6 5 Address: 0x14 Reset Value: 0x00 4 SE4 3 SE3 2 SE2 1 SE1 0 SE0 SE5 Data Type: 8-bit number. USAGE: Write to this register to start either SROM download or SROM CRC test. Write 0x18 to this register before downloading SROM firmware to the SROM_Load register. The download will not be successful unless this register contains the correct value. Write 0xA1 to start the SROM CRC test. Wait 7ms plus one frame period , then read result from the Data_Out_Lower and Data_Out_Upper registers. Navigation is halted and the SPI port should not be used during this test. Reserved Address: 0x15 – 0x18 Frame_Period_Max_Bound_Lower Access: Read/Write Bit Field 7 FBm7 6 FBm6 Address: 0x19 Reset Value: 0xE0 5 FBm5 4 FBm4 3 FBm3 2 FBm2 1 FBm1 0 FBm0 Frame_Period_Max_Bound_Upper Access: Read/Write Bit Field 7 FBm15 6 FBm14 Address: 0x1A Reset Value: 0x2E 5 FBm13 4 FBm12 3 FBm11 2 FBm10 1 FBm9 0 FBm8 Data Type: 16-bit unsigned integer. USAGE: This value sets the maximum frame period (the MINIMUM frame rate) which may be selected by the automatic frame rate control, or sets the actual frame period when operating in manual mode. Units are clock cycles. The formula is Frame Rate = Clock Frequency / Register value To read from the registers, read Upper first followed by Lower. To write to the registers, write Lower first, followed by Upper. To set the frame rate manually, disable automatic frame rate mode via the Extended_Config register and write the desired count value to these registers. Writing to the Frame_Period_Max_Bound_Upper and Lower registers also activates any new values in the following registers: • Frame_Period_Max_Bound_Upper and Lower • Frame_Period_Min_Bound_Upper and Lower • Shutter_Max_Bound_Upper and Lower Any data written to these registers will be saved but will not take effect until the write to the Frame_Period_Max_ Bound_Upper and Lower is complete. After writing to this register, two complete frame times are required to implement the new settings. Writing to any of the above registers before the implementation is complete may put the chip into an undefined state requiring a reset. The “Busy” bit in the Extended_Config register may be used in lieu of a timer to determine when it is safe to write. See the Extended_Config register for more details. The following table lists some Frame_Period values for popular frame rates (clock rate = 24MHz). In addition, the three bound registers must also follow this rule when set to non-default values: Frame_Period_Max_Bound ≥ Frame_Period_Min_Bound + Shutter_Max_Bound. Frames/second 6469 5000 3000 2000 Counts Decimal 3,710 4,800 8,000 12,000 Hex OE7E 12C0 1F40 2EE0 Upper OE 12 1F 2E Frame_Period Lower 7E C0 40 E0 34 Frame_Period_Min_Bound_Lower Access: Read/Write Address: 0x1B Reset Value: 0xAC (before SROM download) 0x7E (after SROM download) Bit Field 7 FBm7 6 FBm6 5 FBm5 4 FBm4 3 FBm3 2 FBm2 1 FBm1 0 FBm0 Frame_Period_Min_Bound_Upper Access: Read/Write Bit Field 7 FBm15 6 FBm14 Address: 0x1C Reset Value: 0x0D (before SROM download) 0x0E (after SROM download) 5 FBm13 4 FBm12 3 FBm11 2 FBm10 1 FBm9 0 FBm8 Data Type: 16-bit unsigned integer. USAGE: This value sets the minimum frame period (the MAXIMUM frame rate) that may be selected by the automatic frame rate control. Units are clock cycles. The formula is Frame Rate = Clock Rate / Register value To read from the registers, read Upper first followed by Lower. To write to the registers, write Lower first, followed by Upper, then execute a write to the Frame_Period_Max_Bound_Upper and Lower registers. The minimum allowed write value is 0x7E0E; the maximum is 0xFFFF. Reading this register will return the most recent value that was written to it. However, the value will take effect only after a write to the Frame_Period_Max_Bound_Upper and Lower registers. After writing to Frame_Period_Max_ Bound_Upper, wait at least two frame times before writing to Frame_Period_Min_Bound_Upper or Lower again. The “Busy” bit in the Extended_Config register may be used in lieu of a timer to determine when it is safe to write. See the Extended_Config register for more details. In addition, the three bound registers must also follow this rule when set to non-default values: Frame_Period_Max_Bound ≥ Frame_Period_Min_Bound + Shutter_Max_Bound. Shutter_Max_Bound_Lower Access: Read/Write Bit Field 7 SB7 6 SB6 Address: 0x1D Reset Value: 0x8C (before SROM download) 0x00 (after SROM download) 5 SB5 4 SB4 3 SB3 2 SB2 1 SB1 0 SB0 Shutter_Max_Bound_Upper Access: Read/Write Bit Field 7 SB15 6 SB14 Address: 0x1E Reset Value: 0x20 5 SB13 4 SB12 3 SB11 2 SB10 1 SB9 0 SB8 Data Type: 16-bit unsigned integer. USAGE: This value sets the maximum allowable shutter value when operating in automatic mode. Units are clock cycles. Since the automatic frame rate function is based on shutter value, the value in these registers can limit the range of the frame rate control. To read from the registers, read Upper first followed by Lower. To write to the registers, write Lower first, followed by Upper, then execute a write to the Frame_Period_Max_Bound_Upper and Lower registers. To set the shutter manually, disable the AGC via the Extended_Config register and write the desired value to these registers. Reading this register will return the most recent value that was written to it. However, the value will take effect only after a write to the Frame_Period_Max_Bound_Upper and Lower registers. After writing to Frame_Period_Max_Bound_ Upper, wait at least two frame times before writing to Shutter_Max_Bound_Upper or Lower again. The “Busy” bit in the Extended_Config register may be used in lieu of a timer to determine when it is safe to write. See the Extended_Config register for more details. In addition, the three bound registers must also follow this rule when set to non-default values: Frame_Period_Max_Bound ≥ Frame_Period_Min_Bound + Shutter_Max_Bound. SROM_ID Access: Read Bit Field 7 SR7 6 SR6 Address: 0x1F Reset Value: 0x00 5 SR5 4 SR4 3 SR3 2 SR2 1 SR1 0 SR0 Data Type:8-Bit unsigned integer. USAGE: Contains the revision of the downloaded Shadow ROM firmware. If the firmware has been successfully downloaded and the chip is operating out of SROM, this register will contain the SROM firmware revision, otherwise it will contain 0x00. Note: The IC hardware revision is available by reading the Revision_ID register (register 0x01). Reserved Address: 0x20 – 0x3C 36 Observation Access: Read/Write Bit Field 7 OB7 6 Reserved 5 Address: 0x3D Reset Value: 0x00 4 Reserved 3 Reserved 2 Reserved 1 OB1 0 OB0 OB5 Data Type: Bit field USAGE: Each bit is set by some process or action at regular intervals, or when the event occurs. The user must clear the register by writing 0x00, wait an appropriate delay, and read the register. The active processes will have set their corresponding bit(s). This register may be used as part of a recovery scheme to detect a problem caused by EFT/B or ESD. Field Name OB7 Reserved OB5 Reserved Reserved Reserved OB1 OB0 Description If set, chip is running SROM code Reserved NPD pulse was detected Reserved Reserved Reserved Set once per frame Set once per frame Reserved Address: 0x3E Inverse_Product_ID Access: Read Bit Field 7 NPID7 6 NPID6 5 Address: 0x3F Reset Value: 0xF8 4 NPID4 3 NPID3 2 NPID2 1 NPID1 0 NPID0 NPID5 Data Type: Inverse 8-Bit unsigned integer USAGE: This value is the inverse of the Product_ID, located at the inverse address. It can be used to test the SPI port. Pixel_Burst Access: Read Data Type: Eight bit unsigned integer Bit Field 7 PB7 6 PB6 Address: 0x40 Reset Value: 0x00 5 PB5 4 PB4 3 PB3 2 PB2 1 PB1 0 PB0 USAGE: The Pixel_Burst register is used for high-speed access to all the pixel values from one and 2/3 complete frame. See the Synchronous Serial Port section for use details. Motion_Burst Access: Read Bit Field 7 MB7 6 MB6 Address: 0x50 Reset Value: 0x00 5 MB5 4 MB4 3 MB3 2 MB2 1 MB1 0 MB0 Data Type: Various, depending on data USAGE: The Motion_Burst register is used for high-speed access to the Motion, Delta_X, and Delta_Y, SQUAL, Shutter_ Upper, and Shutter_Lower and Maximum_Pixel registers. See the Synchronous Serial Port section for use details. SROM_Load Access: Write Data Type: Eight bit unsigned integer Address: 0x 60 Rset Value: N/A USAGE: The SROM_Load register is used for high-speed programming of the ADNS-3080 from an external SROM or microcontroller. See the Synchronous Serial Port section for use details. 38 Read Also ADNS-3080 Product Overview ADNK-3080 Sample Kit Ordering Information Specify part number as follows: ADNS-3080 = Sensor IC in a 20 pin plastic optical package, 20 per tube. ADNB-3081 = Sensor IC and ADNS-2120 round lens bundle kit, 1000 pc incremental ADNB-3082 = Sensor IC and ADNS-2120-001 trim lens bundle kit, 1000 pc incremental ADNS-2120 = Round Optical Mouse Lens ADNS-2120-001 = Trim Optical Mouse Lens ADNS-2220 = LED Assembly Clip (Clear) ADNS-2220-001 LED Assembly Clip (Black) HLMP-ED80-XX000 = LED Relevant Application Notes Application Note AN 5035* Application Note AN 5034* Application Note AN 5036* * The application notes content are applicable for ADNS-3080 as well. For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries. Data subject to change. Copyright © 2006 Avago Technologies Limited. All rights reserved. Obsoletes 5989-3422EN AV02-0366EN - April 24, 2007 39