ADNS-5020-EN

ADNS-5020-EN Optical Mouse Sensor Data Sheet Description The Avago Technologies ADNS-5020-EN is an entry-level, small form factor optical mouse sensor. It comes with many built-in features and optimized for LED-based corded products. The ADNS-5020-EN is capable of high-speed motion detection – up to 20 ips and 2G. In addition, it has an onchip oscillator and built-in LED driver to minimize external components. Frame rate is also adjusted internally. The ADNS-5020-EN along with the ADNS-5100/ADNS5100-001 lens, ADNS-5200 clip and HLMP-ED80 LED form a complete and compact mouse tracking system. There are no moving parts, which means high reliability and less maintenance for the end user. In addition, precision optical alignment is not required, facilitating high volume assembly. The sensor is programmed via registers through a threewire SPI interface. It is housed in an 8-pin staggered dual in-line package (DIP). Features • • • • • • • • • Small form factor Built-in LED driver for simpler circuitry High speed motion detection up to 20 ips and 2G Self-adjusting frame rate for optimum performance Internal oscillator – no clock input needed Selectable 500 and 1000 cpi resolution Operating voltage: 5 V nominal Three-wire serial interface Minimal number of passive components Applications • Optical mice • Optical trackballs • Integrated input devices Theory of Operation The ADNS-5020-EN is based on Optical Navigation Technology, which measures changes in position by optically acquiring sequential surface images (frames) and mathematically determining the direction and magnitude of movement. The ADNS-5020-EN contains an Image Acquisition System (IAS), a Digital Signal Processor (DSP), and a three wire serial port. The IAS acquires microscopic surface images via the lens and illumination system. These images are processed by the DSP to determine the direction and distance of motion. The DSP calculates the Dx and Dy relative displacement values. An external microcontroller reads the Dx and Dy information from the sensor serial port. The microcontroller then translates the data into PS2 or USB signals before sending them to the host PC. Pinout of ADNS-5020-EN Optical Mouse Sensor Pin 1 2 3 4 5 6 7 8 Name SDIO XY_LED NRESET NCS VDD5 GND REGO SCLK Description Serial Port Data Input and Output LED Control Reset Pin (active low input) Chip Select (active low input) Supply Voltage Ground Regulator Output Serial Clock Input A5020E XYYWWZ Figure 1. Package outline drawing (top view). A5020E XYYWWZ PIN 1 12.85 (AT SHOULDER) (0.506) 9.90 (0.390) 9.10 (0.358) 4.32 (0.170) 5.15 (0.203) 90° ± 3° 1.00 (0.039) LEAD OFFSET 0.25 (0.010) 12.85 ± 0.45 (AT LEAD TIP) (0.506 ± 0.018) 0.50 (0.020) LEAD WIDTH 2.00 (0.079) LEAD PITCH PIN 1 ∅ 5.60 (0.220) (AT BASE) 2.00 (0.079) ∅ 5.00 (0.197) PROTECTIVE KAPTON TAPE NOTES: 1. DIMENSIONS IN MILLIMETERS (INCHES). 2. DIMENSIONAL TOLERANCE: ± 0.1 mm. 3. COPLANARITY OF LEADS: 0.1 mm. 4. CUMULATIVE PITCH TOLERANCE: ± 0.15 mm. 5. LEAD PITCH TOLERANCE: ± 0.15 mm. 6. MAXIMUM FLASH: + 0.2 mm. 7. LEAD WIDTH: 0.5 mm. 8. ANGULAR TOLERANCE: ± 3.0°. 4.55 (0.179) ∅ 0.80 (0.031) CLEAR OPTICAL PATH 4.45 (0.175) Figure 2. Package outline drawing. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. 2 Overview of Optical Mouse Sensor Assembly Avago Technologies provides an IGES file drawing describing the base plate molding features for lens and PCB alignment. The ADNS-5020-EN sensor is designed for mounting on a through-hole PCB, looking down. There is an aperture stop and features on the package that align to the lens. The ADNS-5100/5100-001 lens provides optics for the imaging of the surface as well as illumination of the 12.85 (0.506) 10.35 (0.407) 7.56 (0.298) 6.29 (0.248) 5.02 (0.198) 2.25 (0.089) 0.25 (0.010) 26.67 (1.050) 3X ∅ 3.00 (0.118) OPTIONAL HOLE FOR ALIGNMENT POST, IF USED 31.50 (1.240) 24.15 (0.951) 14.94 CLEAR ZONE (0.588) 25.00 (0.984) surface at the optimum angle. Features on the lens align it to the sensor, base plate, and clip with the LED. The ADNS-5200 clip holds the LED in relation to the lens. The LED must be inserted into the clip and the LED’s leads formed prior to loading on the PCB. The HLMP-ED80 LED is recommended for illumination. 14.44 (0.569) 0 (0) 2X ∅ 0.80 (0.031) PIN #1 2.00 (0.079) HOLE PITCH DISTANCE 1.00 (0.039) 2.00 (0.079) 8X ∅ 0.80 (0.031) 13.06 (0.514) OPTICAL CENTER 0 (0) 1.37 (0.054) 6.30 (0.248) 11.22 (0.442) 12.60 (0.496) ALL DIMENSIONS IN MILLIMETERS (INCHES). Figure 3. Recommended PCB mechanical cutouts and spacing. 3 33.45 (1.317) TOP VIEW 13.10 (0.516) BASE PLATE DIMENSIONS IN mm (INCHES) CROSS SECTION SIDE VIEW LED CLIP 10.58 (0.417) 7.45 TOP PCB to SURFACE (0.293) SENSOR PCB LENS LED 2.40 BOTTOM of LENS FLANGE to SURFACE (0.094) NAVIGATION SURFACE BASE PLATE ALIGNMENT POST (OPTIONAL) Figure 4. 2D Assembly drawing of ADNS-5020-EN (top and side views). 4 HLMP-ED80 (LED) ADNS-5200 (LED CLIP) SENSOR CUSTOMER SUPPLIED PCB ADNS-5100 (LENS) CUSTOMER SUPPLIED BASE PLATE WITH RECOMMENDED ALIGNMENT FEATURES PER IGES DRAWING Figure 5. Exploded view drawing. PCB Assembly Considerations 1. Insert the sensor and all other electrical components into PCB. 2. Insert the LED into the assembly clip and bend the leads 90 degrees. 3. Insert the LED clip assembly into PCB. 4. Wave solder the entire assembly in a no-wash solder process utilizing solder fixture. The solder fixture is needed to protect the sensor during the solder process. It also sets the correct sensor-to-PCB distance as the lead shoulders do not normally rest on the PCB surface. The fixture should be designed to expose the sensor leads to solder while shielding the optical aperture from direct solder contact. 5. Place the lens onto the base plate. 6. Remove the protective kapton tape from optical aperture of the sensor. Care must be taken to keep contaminants from entering the aperture. Recommend not to place the PCB facing up during the entire mouse assembly process. Recommend to hold the PCB first vertically for the kapton removal process. 7. Insert PCB assembly over the lens onto the base plate aligning post to retain PCB assembly. The sensor aperture ring should self-align to the lens. GND 8. The optical position reference for the PCB is s et by the base plate and lens. Note that the P CB motion due to button presses must be minimized to maintain optical alignment. 9. I n s t a l l m o u s e to p c a s e. Th e re M U S T b e a f eature in the top case to press down onto the PCB assembly to ensure all components are interlocked to the correct vertical height. ADNS-5020-EN SERIAL PORT AND REGISTERS NCS SCLK SDIO NRESET VDD5 POWER AND CONTROL IMAGE ARRAY DSP OSCILLATOR LED DRIVE REGO XY_LED Figure 6. Block diagram of ADNS-5020-EN optical mouse sensor. 5 Design Considerations for Improved ESD Performance For improved electrostatic discharge performance, typical creepage and clearance distance are shown in the table below. Assumption: base plate construction as per the Avago Technologies supplied IGES file and ADNS-5100/5100-001 lens. Typical Distance Creepage Clearance Millimeters 16.0 2.1 Note that the lens material is polycarbonate or polystyrene HH30, therefore, cyanoacrylate based adhesives or other adhesives that may damage the lens should NOT be used. CLIP SENSOR LED PCB LENS/LIGHT PIPE BASE PLATE SURFACE Figure 7. Sectional view of PCB assembly highlighting optical mouse components. 6 SW2 MIDDLE SW1 RIGHT SW3 LEFT VCC C7 0.1 5 VDD P1.0 P1.1 P1.2 P1.3 P1.6 P1.7 VCC 8 P0.7 P0.6 P0.5 P0.4 P0.2 P0.3 P1.4 P1.5 XOUT VREG XIN/P2.1 GND P0.0 P0.1 VPP Q1 2V CC 1 QA 3 QB Z-ENCODER R3 27K RECOMMENDED LED BIN: BIN P AND ABOVE (P, Q, R, S....) SCLK 1 SDIO 4 3 GND C2 4.7 6 C4 3.3 C3 0.1 C1 0.1 D1 HLMP-ED80 +5V VCC J1 VBUS GND D+ D– 1 2 3 4 POWER R13 1.30K MCU with USB Features ADNS-5020-EN 7 U1 REG0 NCS NRESET XY_LED 2 XY_LED D+/SCLK D–/SDAT VCC R2 240 D2 Z-LED R4 27K Figure 8. Schematic diagram for interface between ADNS-5020-EN and microcontroller. 7 Regulatory Requirements • Passes FCC B and worldwide analogous emission limits when assembled into a mouse with shielded cable and following Avago Technologies recommendations. • Passes IEC-1000-4-3 radiated susceptibility level when assembled into a mouse with shielded cable and following Avago Technologies recommendations. • Passes EN61000-4-4/IEC801-4 EFT tests when assembled into a mouse with shielded cable and following Avago Technologies recommendations. • UL flammability level UL94 V-0. • Provides sufficient ESD creepage/clearance distance to avoid discharge up to 15 kV when assembled into a mouse using ADNS-5100 round lens according to usage instructions above. Absolute Maximum Ratings Parameter Storage Temperature Lead Solder Temp Supply Voltage ESD 3015 Input Voltage Output Current VIN Iout -0.5 VDD -0.5 Symbol TS Minimum -40 Maximum 85 260 5.5 2 VDD+0.5 7 Units °C °C Notes V kV V mA All pins, human body model MIL 883 Method All I/O pins SDIO pin Recommended Operating Conditions Parameter Symbol Operating Temperature Power Supply Power Supply Rise Time Supply Noise (Sinusoidal) TA VDD VRT VNA Minimum 0 4.0 0.005 Typical 5.0 Maximum 40 5.25 100 100 1 Units °C V ms mV p-p MHz 2.5 ips G pF Notes 0 to VDD 10 kHz-50 MHz 50% duty cycle. mm Serial Port Clock Frequency fSCLK Distance from Lens Reference Plane to Tracking Surface (Z) Speed Acceleration Load Capacitance S a Cout Z 2.3 16 2.4 20 2 100 SDIO LENS SENSOR Z = 2.40 (0.094) OBJECT SURFACE LENS REFERENCE PLANE Figure 9. Distance from lens reference plane to tracking surface (Z). 8 AC Electrical Specifications Electrical Characteristics over recommended operating conditions. Typical values at 25 °C, VDD = 3.3 V. Parameter Symbol Minimum Typical Maximum Units Notes Power Down Wake from Power Down tPD tWAKEUP 50 50 55 ms ms From PD (when bit 1 of register 0x0d is set) to low current From PD inactive (when NRESET pin is asserted high or write 0x5a to register 0x3a) to valid motion Active low. From NRESET pull high to valid mo tion, assuming VDD and motion is present. CL = 100pF CL = 100pF From SCLK falling edge to SDIO data valid, no load conditions. Data held until next falling SCLK edge. From data valid to SCLK rising edge. From rising SCLK for last bit of the first data byte, to rising SCLK for last bit of the second data byte. From rising SCLK for last bit of the first data byte, to rising SCLK for last bit of the second address byte. From rising SCLK for last bit of the first data byte, to falling SCLK for the first bit of the next address. From rising SCLK for last bit of the address byte, to falling SCLK for first bit of data being read. Minimum NCS inactive time after motion burst before next SPI usage. From NCS falling edge to first SCLK rising edge. From last SCLK rising edge to NCS rising edge, for valid SDIO data transfer. From last SCLK rising edge to NCS rising edge, for valid SDIO data transfer. From NCS rising edge to SDIO high-Z state. Max supply current during a VDD ramp from 0 to VDD. Reset Pulse Width Motion Delay after Reset tRESET tMOT-RST 250 50 ns ms SDIO Rise Time SDIO Fall Time SDIO delay after SCLK SDIO Hold Time SDIO Setup Time SPI Time between Write Commands SPI Time between Write and Read Commands SPI Time between Read and Subsequent Commands SPI Read Address-Data Delay tr-SDIO tf-SDIO tDLY-SDIO thold-SDIO tsetup-SDIO tSWW 0.5 120 30 150 150 300 300 120 1/fSCLK ns ns ns us ns µs tSWR 20 µs tSRW tSRR tSRAD 500 ns 4 µs NCS Inactive after Motion Burst NCS to SCLK Active SCLK to NCS Inactive (for read operation) SCLK to NCS Inactive (for write operation) NCS to SDIO High-Z Transient Supply Current tBEXIT tNCS-SCLK tSCLK-NCS 250 120 120 ns ns ns tSCLK-NCS tNCS-SDIO IDDT 20 500 60 us ns mA 9 DC Electrical Specifications Electrical Characteristics over recommended operating conditions. Typical values at 25 °C, VDD = 3.3 V. Parameter Symbol Minimum Typical Maximum Units Notes DC Supply Current Idle Supply Current Input Low Voltage Input High Voltage Input Hysteresis Input Leakage Current XY_LED Current VIL VIH VI_HYS Ileak IXY_LED VDD – 0.5 200 ±1 20 ±10 50 IDD_AVG 6 2 0.5 10 mA mA V V mV µA mA SCLK, SDIO, NCS, NRESET SCLK, SDIO, NCS, NRESET SCLK, SDIO, NCS, NRESET Vin = VDD-0.6 V, SCLK, SDIO, NCS, NRESET Average current at maximum frame rate. XY_LED pin voltage range should be greater than 0.8 V. Iout = 1 mA, SDIO Iout = -1 mA, SDIO NCS, SCLK, SDIO, NRESET Average sensor current, at max frame rate. No load on SDIO. Output Low Voltage Output High Voltage Input Capacitance VOL VOH Cin VDD-0.7 50 0.7 V V pF Typical Performance Characteristics Figure 10. Mean resolution vs. distance from lens reference plane to surface. 1.0 0.9 0.8 Normalized Response 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 400 500 600 700 800 900 1000 Wavelength (nm) Figure 11. Average error vs. distance (mm). Figure 12. Relative wavelength responsivity. 10 LED Mode For power savings, the LED will not be continuously on. ADNS-5020-EN will pulse the LED only when needed. Chip Select Operation The serial port is activated after NCS goes low. If NCS is raised during a transaction, the entire transaction is aborted and the serial port will be reset. This is true for all transactions. After a transaction is aborted, the normal address-to-data or transaction-to-transaction delay is still required before beginning the next transaction. To improve communication reliability, all serial transactions should be framed by NCS. In other words, the port should not remain enabled during periods of non-use because ESD and EFT/B events could be interpreted as serial communication and put the chip into an unknown state. In addition, NCS must be raised after each burst-mode transaction is complete to terminate burst-mode. The port is not available for further use until burst-mode is terminated. Synchronous Serial Port The synchronous serial port is used to set and read parameters in the ADNS-5020-EN, and to read out the motion information. The port is a three wire serial port. The host micro-controller always initiates communication; the ADNS-5020-EN never initiates data transfers. SCLK, SDIO, and NCS may be driven directly by a micro-controller. The port pins may be shared with other SPI slave devices. When the NCS pin is high, the inputs are ignored and the output is tri-stated. The lines that comprise the SPI port: SCLK: SDIO: NCS: Clock input. It is always generated by the master (the micro-controller). Input and Output data. Chip select input (active low). NCS needs to be low to activate the serial port; otherwise, SDIO will be high Z, and SDIO & SCLK will be ignored. NCS can also be used to reset the serial port in case of an error. Write Operation Write operation, defined as data going from the microcontroller to the ADNS-5020-EN, is always initiated by the micro-controller and consists of two bytes. The first byte contains the address (seven bits) and has a “1” as its MSB to indicate data direction. The second byte contains the data. The ADNS-5020-EN reads SDIO on rising edges of SCLK. NCS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 SCLK SDIO 1 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 1 A6 SDIO DRIVEN BY MICRO-CONTROLLER Write Operation 1/f SCLK 1/f SCLK SCLK SDIO thold tsetup SDIO Setup and Hold Time 11 Read Operation A read operation, defined as data going from the ADNS5020-EN to the micro-controller, is always initiated by the micro-controller and consists of two bytes. The first byte contains the address, is sent by the micro- controller over SDIO, and has a “0” as its MSB to indicate data direction. The second byte contains the data and is driven by the ADNS-5020-EN over SDIO. The sensor outputs SDIO bits on falling edges of SCLK and samples SDIO bits on every rising edge of SCLK. SCLK CYCLE # SCLK SDIO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDIO DRIVEN BY MICRO-CONTROLLER DETAIL "A" SDIO DRIVEN BY ADNS-5020-EN DETAIL "B" Read Operation tSRAD tDLY SCLK MICROCONTROLLER TO ADNS-5020-EN SDIO HANDOFF SDIO tSETUP A1 A0 tHOLD 0 ns, MIN. Hi-Z D7 D6 tDLY DETAIL "A" 0 ns, MIN. Microcontroller to ADNS-5020-EN Handoff DETAIL "B" SCLK ADNS-5020-EN TO MICROCONTROLLER SDIO HANDOFF SDIO tDLY tHOLD D0 R/W BIT OF NEXT ADDRESS RELEASED BY 5020 DRIVEN BY MICRO ADNS-5020-EN to Microcontroller Handoff NOTE: The 0.5/fSCLK minimum high state of SCLK is also the minimum SDIO data hold time of the ADNS-5020-EN. Since the falling edge of SCLK is actually the start of the next read or write command, the ADNS-5020-EN will hold the state of data on SDIO until the falling edge of SCLK. 12 Required Timing between Read and Write Commands There are minimum timing requirements between read and write commands on the serial port. tSWW SCLK ADDRESS DATA ADDRESS DATA WRITE OPERATION WRITE OPERATION Timing between Two Write Commands If the rising edge of the SCLK for the last data bit of the second write command occurs before the required delay (tSWW ), then the first write command may not complete correctly. tSWR ••• SCLK ADDRESS DATA ADDRESS ••• WRITE OPERATION NEXT READ OPERATION Timing between Write and Read Commands If the rising edge of SCLK for the last address bit of the read command occurs before the required delay (tSWR), the write command may not complete correctly. tSRAD tSRW & tSRR ••• SCLK ADDRESS READ OPERATION DATA ADDRESS ••• NEXT READ or WRITE OPERATION Timing between Read and Either Write or Subsequent Read Commands During a read operation SCLK should be delayed at least tSRAD after the last address data bit to ensure that the ADNS-5020-EN has time to prepare the requested data. The falling edge of SCLK for the first address bit of either the read or write command must be at least tSRR or tSRW after the last SCLK rising edge of the last data bit of the previous read operation. 13 Motion Burst Timing tSRAD ••• SCLK MOTION_BURST REGISTER ADDRESS READ FIRST BYTE ••• FIRST READ OPERATION READ SECOND BYTE READ THIRD BYTE Burst Mode Operation Burst mode is a special serial port operation mode that may be used to reduce the serial transaction time for a motion read. The speed improvement is achieved by continuous data clocking to or from multiple registers without the need to specify the register address, and by not requiring the normal delay period between data bytes. Burst mode is activated by reading the Motion_Burst register. The ADNS-5020-EN will respond with the contents of the Delta_X, Delta_Y, SQUAL, Shutter_ Upper, Shutter_Lower, Maximum_Pixel and Pixel_Sum r egisters in that order. The burst transaction can be terminated anywhere in the sequence after the Delta_X value by bringing the NCS pin high. After sending the register address, the micro-controller must wait tSRAD and then begin reading data. All data bits can be read with no delay between bytes by driving SCLK at the normal rate. The data are latched into the output buffer after the last address bit is received. After the burst transmission is complete, the micro-controller must raise the NCS line for at least tBEXITto terminate burst mode. The serial port is not available for use until it is reset with NCS, even for a second burst transmission. Avago Technologies highly recommends the usage of burst mode operation in optical mouse sensor design applications. During power-up there will be a period of time after the power supply is high but before any clocks are available. The table below shows the state of the various pins during power-up and reset. State of Signal Pins After VDD is Valid Pin During Reset NCS Ignored SDIO Ignored SCLK Ignored XY_LED Hi-Z After Reset Functional Depends on NCS Depends on NCS Functional Notes on Power Down The ADNS-5020-EN can be set in Power Down mode by setting bit 1 of register 0x0d. In addition, the SPI port should not be accessed during power down. (Other ICs on the same SPI bus can be accessed, as long as the sensor’s NCS pin is not asserted.) The table below shows the state of various pins during power down. There are 2 ways to exit power down, either assert low NRESET pin or by writing 0x5a to Register 0x3a. A full reset will thus be executed. Wait tWAKEUP before accessing the SPI port. Any register settings must then be reloaded. Pin NRESET NCS SDIO SCLK XY_LED * Power Down Active Functional Functional* Functional* Functional* Low current Notes on Power-up and Reset The ADNS-5020-EN does not perform an internal power up self-reset; the NRESET pin must be asserted low every time power is applied. There are two ways to reset the chip, either assert low NRESET pin or by writing 0x5a to register 0x3a. A full reset will thus be executed. Any register settings must then be reloaded. NCS pin must be held to 1(high) if SPI bus is shared with other devices. It can be in either state if the sensor is the only device in addition to the controller microprocessor. Note: There is long wakeup time from power down. The feature should not be used for power management during normal mouse motion. 14 Registers The ADNS-5020-EN registers are accessible via the serial port. The registers are used to read motion data and status as well as to set the device configuration. Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e – 0x39 0x3a 0x3b – 0x3e 0x3f 0x40 – 0x62 0x63 Register Product_ID Revision_ID Motion Delta_X Delta_Y SQUAL Shutter_Upper Shutter_Lower Maximum_Pixel Pixel_Sum Minimum_Pixel Pixel_Grab Reserved Mouse Control Reserved Chip_Reset Reserved Inv_Rev_ID Reserved Motion_Burst Read/Write R R R R R R R R R R R R/W R/W W R R Default Value 0x12 0x01 0x00 Any Any Any Any Any Any Any Any Any 0x00 N/A 0xfe 0x00 15 Product_ID Access: Read Bit Field Data Type: USAGE: Address: 0x00 Reset Value: 0x12 7 PID7 6 PID6 5 PID5 4 PID4 3 PID3 2 PID2 1 PID1 0 PID0 8-Bit unsigned integer This register contains a unique identification assigned to the ADNS-5020-EN. The value in this register does not change; it can be used to verify that the serial communications link is functional. Revision_ID Access: Read Bit Field Data Type: USAGE: Address: 0x01 Reset Value: 0x01 7 RID7 6 RID6 5 RID5 4 RID4 3 RID3 2 RID2 1 RID1 0 RID0 8-Bit unsigned integer This register contains the IC revision. It is subject to change when new IC versions are released. Motion Access: Read/Write Bit Field Data Type: USAGE: Bit field. Address: 0x02 Reset Value: 0x00 7 MOT 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register 0x02 allows the user to determine if motion has occurred since the last time it was read. If the MOT bit is set, then the user should read registers 0x03 and 0x04 to get the accumulated motion. Read this register before reading the Delta_X and Delta_Y registers. Writing anything to this register clears the MOT bit, Delta_X and Delta_Y registers. The written data byte is not saved. Field Name Description MOT Motion since last report 0 = No motion 1 = Motion occurred, data ready for reading in Delta_X and Delta_Y registers Reserved Reserved 16 Delta_X Access: Read Bit Field Data Type: USAGE: Address: 0x03 Reset Value: 0x00 7 X7 6 X6 5 X5 4 X4 3 X3 2 X2 1 X1 0 X0 Eight bit 2’s complement number. X movement is counts since last report. Absolute value is determined by resolution. Reading clears the register. MOTION -128 -127 -2 -1 0 +1 +2 +126 +127 DELTA_X 80 81 FE FF 00 01 02 7E 7F NOTE: Avago Technologies RECOMMENDS that registers 0x03 and 0x04 be read sequentially. Delta_Y Access: Read Bit Field Data Type: USAGE: Address: 0x04 Reset Value: 0x00 7 Y7 6 Y6 5 Y5 4 Y4 3 Y3 2 Y2 1 Y1 0 Y0 Eight bit 2’s complement number. Y movement is counts since last report. Absolute value is determined by resolution. Reading clears the register. MOTION -128 -127 -2 -1 0 +1 +2 +126 +127 DELTA_Y 80 81 FE FF 00 01 02 7E 7F NOTE: Avago Technologies RECOMMENDS that registers 0x03 and 0x04 be read sequentially. 17 SQUAL Access: Read Bit Field Data Type: USAGE: Address: 0x05 Reset Value: 0x00 7 SQ7 6 SQ6 5 SQ5 4 SQ4 3 SQ3 2 SQ2 1 SQ1 0 SQ0 Upper 8 bits of a 9-bit unsigned integer. SQUAL (Surface Quality) is a measure of the number of valid features visible by the sensor in the current frame. The maximum SQUAL register value is 144. Since small changes in the current frame can result in changes in SQUAL, variations in SQUAL when looking at a surface are expected. The graph below shows 250 sequentially acquired SQUAL values, while a sensor was moved slowly over white paper. SQUAL is nearly equal to zero, if there is no surface below the sensor. SQUAL is typically maximized when the navigation surface is at the optimum distance from the imaging lens (the nominal Zheight). Figure 13. Squal values (white paper). Figure 14. Mean squal vs. Z (white paper). 18 Shutter_Upper Access: Read Bit Field Address: 0x06 Reset Value: 0x00 7 S15 6 S14 5 S13 4 S12 3 S11 2 S10 1 S9 0 S8 Shutter_Lower Access: Read Bit Field Address: 0x07 Reset Value: 0x00 7 S7 6 S6 5 S5 4 S4 3 S3 2 S2 1 S1 0 S0 Data Type: USAGE: Sixteen bit unsigned integer. Units are clock cycles. Read Shutter_Upper first, then Shutter_Lower. They should be read consecutively. The shutter is adjusted to keep the average and maximum pixel values within normal operating ranges. The shutter value is automatically adjusted. Figure 15. Shutter (white paper). Figure 16. Mean shutter vs. Z (white paper). 19 Maximum_Pixel Access: Read Bit Field Address: 0x08 Reset Value: 0x00 7 MP0 6 MP6 5 MP5 4 MP4 3 MP3 2 MP2 1 MP1 0 MP0 Data Type: USAGE: Eight-bit number. Maximum Pixel value in current frame. Minimum value = 0, maximum value = 127. The maximum pixel value can vary with every frame. Pixel_Sum Access: Read Bit Field Data Type: USAGE: Address: 0x09 Reset Value: 0x00 7 AP7 6 AP6 5 AP5 4 AP4 3 AP3 2 AP2 1 AP1 0 AP0 High 8 bits of an unsigned 15-bit integer. This register is the accumulated pixel value from the last image taken. The maximum accumulator value is 28,575, but only bits [14:7] are reported. It may be described as the full sum divided by 1.76. The maximum register value is 223. The minimum is 0. The pixel sum value can change on every frame. 20 Minimum_Pixel Access: Read Bit Field Address: 0x0a Reset Value: 0x00 7 MP0 6 MP6 5 MP5 4 MP4 3 MP3 2 MP2 1 MP1 0 MP0 Data Type: USAGE: Eight-bit number. Minimum Pixel value in current frame. Minimum value = 0, maximum value = 127. The minimum pixel value can vary with every frame. Address: 0x0b Reset Value: 0x00 7 Valid 6 PD6 5 PD5 4 PD4 3 PD3 2 PD2 1 PD1 0 PD0 Pixel_Grab Access: Read/Write Bit Field Data Type: USAGE: Eight-bit word. The pixel grabber captures 1 pixel per frame. If there is a valid pixel in the grabber when this register is read, the MSB will be set, an internal counter will incremented to capture the next pixel and the grabber will be armed to capture the next pixel. It will take 225 reads to upload the complete image. Any write to this register will reset and arm the grabber to grab pixel 0 on the next image. 21 Physical Pixel Address Map – readout order of the array (looking through the sensor aperture at the bottom of the package) LAST PIXEL 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIRST PIXEL 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 89 104 119 134 149 164 179 194 209 224 88 103 118 133 148 163 178 193 208 223 87 102 117 132 147 162 177 192 207 222 86 101 116 131 146 161 176 191 206 221 85 100 115 130 145 160 175 190 205 220 84 83 82 81 80 79 78 77 76 75 99 114 129 144 159 174 189 204 219 BOTTOM VIEW OF MOUSE TOP X-RAY VIEW OF MOUSE LB RB POSITIVE Y POSITIVE Y 98 113 128 143 158 173 188 203 218 97 112 127 142 157 172 187 202 217 96 111 126 141 156 171 186 201 216 95 110 125 140 155 170 185 200 215 94 109 124 139 154 169 184 199 214 93 108 123 138 153 168 183 198 213 92 107 122 137 152 167 182 197 212 91 106 121 136 151 166 181 196 211 90 105 120 135 150 165 180 195 210 4 NCS VDD5 5 GND 6 REG0 7 SCLK 8 A5020 XYYWWZ 3 NRESET 2 XY_LED 1 SDIO POSITIVE X HOLE AT MOUSE BOTTOM COVER FOR LENS POSITIVE X 22 Reserved Mouse_control Access: Read/Write Address: 0x0c Address: 0x0d Reset Value: 0x00 Bit Field Data Type: USAGE: 7 6 5 4 3 2 1 0 RES Reserved Reserved Reserved Reserved Reserved Reserved PD Eight bit number Mouse sensor resolution and power down settings can be accessed or to be edited by this register. Field Name PD Description Power Down 0 = Normal 1 = Power Down Set resolution 0 = 500 cpi 1 = 1000 cpi Reserved RES Reserved Reserved Chip_Reset Access: Write Bit Field Address: 0x0e-0x39 Address: 0x3a Reset Value: 0x00 7 CR7 6 CR 6 5 CR 5 4 CR 4 3 CR 3 2 CR 2 1 CR 1 0 CR 0 Data Type: USAGE: 8-Bit unsigned integer Write 0x5a to initiate chip RESET. Reserved Inv_Rev_ID Access: Read Address: 0x3b – 0x3e Address: 0x3f Reset Value: 0xfe Bit Field Data Type: USAGE: 7 RRID7 6 RRID6 5 RRID5 4 RRID4 3 RRID3 2 RRID2 1 RRID1 0 RRID0 8-Bit unsigned integer This register contains the inverse of the revision ID which is located at register 0x01. Reserved Motion_Burst Access: Read Address: 0x40-0x62 Address: 0x63 Reset Value: 0x00 Bit Field Data Type: USAGE: Various. 7 MB7 6 MB6 5 MB5 4 MB4 3 MB3 2 MB2 1 MB1 0 MB0 Read from this register to activate burst mode. The sensor will return the data in the Delta_X, Delta_Y, Squal, Shutter_Upper, Shutter_Lower, Maximum_Pixel and Pixel_Sum. If the burst is not terminated at this point, the internal address counter stops incrementing and Pixel Sum register’s value will be continuously returned. Bursts are terminated when NCS is raised. For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0327EN AV02-0365EN - August 8, 2007