ADNS-7050
Laser Mouse Sensor
Data Sheet
Description
Features
The Avago Technologies ADNS-7050 sensor along with
the ADNS-6120 or ADNS-6130-001 lens, ADNS-6130-001
clip and ADNV-6340 VCSEL form a complete and laser
mouse tracking system. It is the laser illuminated system enabled for cordless application. Powered by Avago
Technologies LaserStreamTM technology, it can operate
on many surface that proved difficult for traditional LEDbased optical navigation. It’s low power architecture is
capable of sensing mouse motion while prolonging battery life, two performance areas essential in demanding
cordless applications.
x Low power architecture
There is no moving part, in the complete assembly for
ADNS-7050 laser mouse system, thus it is high reliability
and less maintenance for the end user. In addition, precision optical alignment is not required, facilitating high
volume assembly.
x Selectable 400 and 800 cpi resolution
Theory of Operation
x New LaserStream™ technology
x Self-adjusting power-saving modes for longest
battery life
x Speed motion detection up to 20 ips and 8g
x Enhanced SmartSpeed self-adjusting frame rate for
optimum performance
x Motion detect pin output
x Internal oscillator – no clock input needed
x Wide operating voltage: 2.7 V-3.6 V nominal
x Four wire serial port
x Minimal number of passive components
x Laser fault detect circuitry on-chip for Eye Safety
Compliance
The ADNS-7050 is based on LaserStream™ Technology,
which measures changes in position by optically acquiring sequential surface images (frames) and mathematically determining the direction and magnitude of movement.
Applications
The ADNS-7050 contains an Image Acquisition System
(IAS), a Digital Signal Processor (DSP), and a four wire
serial port. The IAS acquires microscopic surface images
via the lens and illumination system. These images are
processed by the DSP to determine the direction and distance of motion. The DSP calculates the ∆x and ∆y relative displacement values. An external microcontroller
reads the ∆x and ∆y information from the sensor serial
port. The microcontroller then translates the data into
PS2, USB, or RF signals before sending them to the host
PC or game console.
x Battery-powered input devices
x Laser mice
x Optical trackballs
x Integrated input devices
Pinout of ADNS-7050 Optical Mouse Sensor
Pin
Name
Description
1
NCS
Chip Select (Active Low Input)
2
MISO
Serial Data Output (Master In/Slave Out)
3
SCLK
Serial Clock Input
4
MOSI
Serial Data Input (Master Out/Slave In)
5
MOTION
Motion Detect (Active Low Output)
6
LASER_NEN
LASER Enable (Active LOW)
7
GND
Ground
8
XY_LASER
LASER Control
9
AGND
Analog Ground
10
AVDD
Analog Supply Voltage
11
AGND
Analog Ground
12
GND
Ground
13
GND
14
NC
No Connection
15
GND
Ground
16
VDD
Supply Voltage
17
NC
No Connection
18
NC
No Connection
2
Ground
18 NC
1 NCS
17 NC
2 MISO
3 SCLK
A7050
XYYWWZ
16 VDD
15 GND
4 MOSI
14 NC
5 MOTION
13 GND
6 LASER_NEN
12 GND
7 GND
11 AGND
8 XY_LASER
10 AVDD
9 AGND
Figure 1. Package outline drawing (top view).
A70 50
Figure 2. Package outline drawing.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
3
Overview of Laser Mouse Sensor Assembly
31.17
(1.227)
A7050
XYYWWZ
16.00
(0.630)
BASE PLATE
TOP OF PCB TO
BOTTOM OF SENSOR
3.20
(0.126)
VCSEL PCB
CLIP
SENSOR
3.75
(0.148)
TOP OF PCB TO TOP
OF LENS FLANGE
2.40
(0.094)
BOTTOM OF LENS
FLANGE TO SURFACE
PCB
20.49
(0.807)
SURFACE
Figure 3. 2D Assembly drawing of ADNS-7050 (top and cross-sectional view).
4
15.37
(0.605)
SURFACE TO
VCSEL BODY
2D Assembly Drawing of ADNS-7050, PCBs and Base Plate
ADNS-7050 (SENSOR)
CUSTOMER SUPPLIED VCSEL PCB
ADNV-6340 (VCSEL)
USTOMER SUPPLIED PCB
ADNS-6230-001 (CLIP)
ADNS-6130-001 (LENS)*
R SUPPLIED BASE PLATE
OMMENDED FEATURES
DRAWING
S-6120 FOR ROUND LENS
Figure 4. Exploded view drawing.
Shown with ADNS-6130-001 Laser Mouse Lens, ADNS6230-001 VCSEL Assembly Clip and ADNV-6340 VCSEL.
The components interlock as they are mounted onto defined features on the base plate.
The ADNS-7050 laser mouse sensor is designed for
mounting on a through hole PCB, looking down. There is
an aperture stop and features on the package that align
to the lens.
The ADNV-6340 VCSEL is recommended for illumination,
provides a laser diode with a single longitudinal and a
single transverse mode. It is particularly suited as lower
power consumption and highly coherent replacement
of LEDs. It also provides wider operation range while still
remaining within single-mode, reliable operating conditions.
The ADNS-6120 or ADNS-6130-001 Laser Mouse Lens is
designed for use with ADNS-7050 sensor and the illumination subsystem provided by the assembly clip and
5
the VCSEL. Together with the VCSEL, the lens provides
the directed illumination and optical imaging necessary
for proper operation of the Laser Mouse Sensor. ADNS6120 and ADNS-6130-001 are precision molded optical
components and should be handled with care to avoid
scratching of the optical surfaces. ADNS-6120 also has a
large round flange to provide a long creepage path for
any ESD events that occur at the opening of the base
plate.
The ADNS-6230-001 VCSEL Assembly Clip is designed to
provide mechanical coupling of the ADNV-6340 VCSEL
to the ADNS-6120 or ADNS-6130-001 lens. This coupling
is essential to achieve the proper illumination alignment
required for the sensor to operate on a wide variety of
surfaces.
Avago Technologies provides an IGES file drawing describing the base plate molding features for lens and PCB
alignment.
0.89
(0.035)
18X ∅ 0.75 RECOMMENDED
(0.030)
0.2
(0.008)
6X R 0.75 MAX.
(0.030)
OPTICAL NAVIGATION CENTER
22.6
(0.890)
12.6
(0.496)
11.0
(0.433)
12.6
(0.496)
6.3
(0.248)
0
(0.000)
0
10.0
(0.394)
1.6
(0.063)
PIN 1 HOLE
0
1.78
(0.070)
14.84
(0.584)
15.15
(0.596)
2 mm MAX. COMPONENT
HEIGHT CLEAR ZONE
2 mm MAX. COMPONENT
HEIGHT RECOMMENDED FINGER
CLEARANCE ZONE (BOTH SIDES)
25.0
(0.984)
36.0
(1.417)
DIMENSIONS IN MILLIMETERS (INCHES).
Figure 5. Recommended PCB mechanical cutouts and spacing.
Assembly Recommendation
x Insert the sensor and all other electrical components
into the application PCB (main PCB board and VCSEL
PCB board).
x Wave-solder the entire assembly in a no-wash
solder process utilizing a solder fixture. The solder
fixture is needed to protect the sensor during the
solder process. It also sets the correct sensor-to -PCB
distance, as the lead shoulders do not normally rest
on the PCB surface. The fixture should be designed to
expose the sensor leads to solder while shielding the
optical aperture from direct solder contact.
x Place the lens onto the base plate.
x Remove the protective kapton tape from the optical
aperture of the sensor. Care must be taken to keep
contaminants from entering the aperture.
x Insert the PCB assembly over the lens onto the base
plate. The sensor aperture ring should self-align to the
lens. The optical position reference for the PCB is set
by the base plate and lens. Note that the PCB motion
due to button presses must be minimized to maintain
optical alignment.
x Remove the protective cap from the VCSEL.
x Insert the VCSEL assembly into the lens.
6
x Slide the clip in place until it latches. This locks the
VCSEL and lens together.
x Tune the laser output power from the VCSEL to meet
the Eye Safe Class I Standard as detailed in the LASER
Power Adjustment Procedure.
x Install the mouse top case. There must be a feature
in the top case (or other area) to press down onto the
sensor to ensure the sensor and lens are interlocked
to the correct vertical height.
Design Considerations for Improving ESD Performance
For improved electrostatic discharge performance, typical creepage and clearance distance are shown in the
table below. Assumption: base plate construction as per
the Avago Technologies supplied IGES file and ADNS6130-001 trim lens (or ADNS-6120 round lens).
Typical Distance
Millimeters
Creepage
12.0
Clearance
2.1
Note that the lens material is polycarbonate and therefore,
cyanoacrylate based adhesives or other adhesives that may damage
the lens should NOT be used.
VCSEL PCB
VCSEL
SENSOR
CLIP
LENS
BASE PLATE
PCB
SURFACE
Figure 6. Sectional view of PCB assembly highlighting optical mouse components.
Key Mode Selection
VCC
R1
LD2
CPI_LED
R1
100K
5 Key
Not Mounted
Mounted
3 Key
V3.3
CPI
1
R9
10K
VCC
Z1
Z Encoder
U1
2
3
1
XT1
Z Axis
2
6MHz
3
4
ZA
5
ZB
6
NCS
7
MISO
8
SCLK
9
MOSI
R2
100K
R3
10ohm
10
VDD
VC
XI
DP_CK
XO
DM_DA
VSS
PC0
PA6
PA0
PA7
PA1
PB0
PA2
PB1
PA3
PB2
PA4
PB3
PA5
LD2 Flash Freq
2Hz
600 CPI
R8
330 ohm
C2
10uF
Buttons
Not Mounted
CPI-LED
VCC
C1
0.1uF
R2
Mounted
V3.3
VCC
800 CPI
6Hz
1200 CPI
12Hz
20
JP1
19
GND
VCC
GND
18
17
16
KEY_EPROMCS
15
LB
* C4
VCC
*C5
100pF
S1 SWL
1
2
3
4
5
+
C3
4.7uF
C6
0.1uF
100pF
USB/PS2 Connector
S2 SWR
14
RB
13
MB
12
B4_UP
S3 SWM
11
S4
B4
S5
B5
B5_DN
SPCP825A-20 Pin OTP
4th/5th Buttons by
Straps Optional
SPCP18A-016A Mask
VCC
S6
V3.3
LB
RB
Laser PWR
ISS-BT
1
V3.3
Dig ital PWR
ISS-SW (Optional)
Analog PWR
C8
0.1uF
3
C7
4.7uF
2
2N3 906
Q1
+
SPY0029A TO-89
3
Vout
1
+
C15
0.1uF
4
1
5
3.3V Regulator Optional
16
AGND
AGND
MISO
MOSI
NCS
MOTION
Optional unused --> R3 Mounted; U3; C14; C15 Not Mounted
U4
KEY_EPROMCS
SCLK
MOSI
MISO
1
2
3
4
CS
SK
DI
DO
18
VCC
NC
ORG
GND
8
7
6
5
17
C16
0.1uF
93C46
16
9
R7
2K
GND
GND
GND
NC
XY_ LASER
NC
LASER_NEN
NC
LASER_GND
12
13
15
8
6
7
Sunplus
Title
7
C13
470pF
11
EEPROM for Laser Eye Safety
for Sun+ ALPC
Figure 7a. Schematic diagram for 3-button scroll wheel corded mouse.
C11
1uF
SCLK
V3.3
Optional used --> R3 Not Mounted. U3; C14; C15 Mounted
LD1
VCSEL
+
C losed to Sens or D GN D
ADNS-7050
3
2
C14
4.7uF
+ 1uF
REGULATOR
Vin
Vss
U3
C losed to Sens or AGN DC12
2
V3.3
2
C9
0.1uF
C10
0.1uF
10
U2
VDD
R6
22K
AVDD
VCC
R5
22K
1
C losed to Sens or
R4
22K
MCUVCC
SW1
LB
C41
0.1 uF
HEADER_8X2
RFVCC
NCS
1
MISO
2
SCLK
3
**
MOSI
4
**
C26
C25
0.0 1uF
16
10
SCLK
MOSI
5
MOTION
D3
1N5819
14
R27
10
U5
3
XC6383A-301PR
Lx
1
C48
47uF
+
17
MCUVCC
C50
0.1 uF
1
C49
0.1 uF
BT1
+3V
RFVCC
3.0 V
2
Vout
Vss
L5
100uH
DVDD
C51
0.1 uF
R29
10
LVDD
R30
10
AVDD
1
C47
470pF
11
AGND
MISO
0.0 1uF
2
C45
1uF
2
AGND
**Not Mounted if good signal quality
1
LD1
VCSEL
+
9
NCS
3
SW6
Z Encoder
C46
+ 1uF
VDD
AVDD
U4
2
1%
2
3
MCUVCC
1
3
5
7
9
11
13
15
18
R26
4.7 K
ADNS-7050
2
4
6
8
10
12
14
16
1
C52
2200pF
C42 Q1
1uF
C43
0.1 uF
C44
0.1 uF
J2
SW3
MB
R28
120K
2N3906
+
AVDD
SW2
RB
SW7
BIND
1
LVDD
DVDD
15
GND
12
GND
13
GND
NC
XY_LASER
NC
LASER_NEN
8
6
NC
7
LASER_GND
2
5%
Sunplus
Title
A7050 Sensor Board
ENG. AP:
Drawn:
Size
B
D ate:
Check By:
D.C.
Rev
PA1
Document Number 2.4 GHZ-1W-MSE-MC02A-A7050-TX
Thursday, December 22 , 200 5
Sheet
2
of
2
MCUVCC
MCUVCC
MCUVCC
**
CS
SK
DI
DO
8
7
6
5
VCC
DC
NC
GND
R13
10
= Not mounted if 3 pin resonator
U3
EEPROM_CS 1
SCLK
2
MOSI
3
MISO
4
**
C34
0.1uF
U2
C33
20pF
C35
0.1uF
24
XT1
8MHz
93C46
**
VDD
23
Clo sed to MCU
R18
2M
4
OSCO
5
OSCI
C36
20pF
EEPROM_CS
RF_CS
NCS
NTEST
RF_PWR
RF_CE
MOTION
ALPC E/D
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
GND
13
16
2
27
14
15
1
28
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
21
20
19
18
10
9
8
7
LB
RB
MB
WAKE_UP
ZA
ZB
SCLK
MOSI
11
25
26
3
6
22
12
17
MISO
DIR1
BAT
DIR2
CPI_LE D
BIND
B4_UP
B5_DN
R31
1M
R14
2M
LD2
BAT_LOW
R8
330 ohm
R5
R6
0
10K
C15
0.22uF (TBD) (TBD)
R10
1M
SW4
SW5
B4_UP
B5_DN
R20
1K
LD3
CPI-LED
Battery
Low LED
SPMC0 2A-066A
R7
10K
(TBD)
R32
10K
VCC
R3
0ohm
SW6
MCUVCC
J22
R21 R22 R23 R24
330 330 330 330
1
3
5
7
9
11
13
15
RFVCC
R11
10
RFVCC
R2
22K
C6
0.01uF
C16
4.7uF
+
CE
2
13
14
15
VSS
ANT2
NRF2402
CLK
ANT1
XC1
VSS
XC2
7
6
5
ISS-SW (Optional)
Power Down SW
(Optional)
ALPC EN/DISABLE
ALPC
Enab le
Disable
C3
22pF
12
C8
TX1
Antenna
Clo sed to IC
C32
1.2pF
L4
2.7~4.7nH
C10
0.5pF
SCLK
1
Sensor Orientation
J6
Sensor Orientatio n
0 degree
90 degree
180 degre e
270 degre e
NCS
1
J7
C5
1000 pF
X1
LD3 Flash Freq
2Hz
6Hz
12Hz
J5
ANT length 32mm
width 0.5mm
(20mil)
Value
C9
1.0pF
Clo sed to IC
CPI
400 CPI
600 CPI
800 CPI
MISO
1
L3
Value
Clo sed to IC
MOSI
1
J4
1.0pF
L1
3.6nH
9
CPI-LED
J3
11
10
R3
Not Mounted
Mounted
L2
22nH
VDD
VSS_PA
DIN
8
4
2
4
6
8
10
12
14
16
HEADER_8X2
C4
2200 pF
VDD_PA
CS
3
C40 22pF
ISS-BT
PD_SW
Clo sed to IC
VDD
1
C39 22pF
IREF
U1
PWR_UP
C38 22pF
16
C37 22pF
LB
RB
SW8
EEPROM_CS
1
DIR1(R5 )
Not Mounted
Mounted
Not Mounted
Mount ed
DIR2(R6 )
Not Mounted
Mounted
Mounted
Not Mounted
DIR2(R7 )
Mounted
Not Mounted
Not Mounted
M ount ed
J8
NTEST
1
16MHZ
Sunplus
ALPC Connection
R1
Title
1M
C1
22pF
C2
22pF
2.4GHz RF ISS Optical Mouse Tx MCU Board
ENG. AP:
3.3 Regulator Circuit Optional
Drawn:
Check By:
D.C.
D.C.
2.4GHZ-1W-ISS-MSE-MC02A-0 66A-A603 0-TX Rev
Docu men t Number
PA2
of
Friday, Feb ruary 24, 20 06
Shee t
1
2
Size
B
D ate:
R2
22K
+V3.3
VCCMCU
U4
VO
VI
3
+V3.3
GND
2
C15
0.1uF
C16
0.1uF
C6
0.01uF
C5
1000p F
C10
4.7uF
+
19
VSS
20
22
23
21
VDD
VSS
VDD
IREF
ANT2
ANT1
18
1pF
17
16
L1
3.6nH
15
ANT length 63mm
width 0.5mm
14
13
C8
1pF
XC1
VDD_PA
L2
22nH
C4
2200p F
12
XC2
DR1
7
R12 22K
VSS_PA
CS
11
6
VSS
5
RF_DR
nRF2401
DOUT2
10
R10 22K
RF_CS
VDD
CLK2
Rx
Antenna
C9
VSS
DR2
CL K1
4
CE
DV DD
3
DA TA
2
8
1
RF_CE
9
3.3 Regulator Circuit Not used : U4; C15; C16 Not Moun ted; R19 Mounted
R9 22K
PWR_UP
U1
24
1
SPY0029
C3
22pF
C17
Value
RF_CLK
X1
RF_DATA
R13 22K
R14
33K
R15
33K
R17
33K
R18
33K
16MHZ
C7
0.033uF
20ppm
R1
1M
C2
22pF
C1
22pF
RF Band Side
+V3.3
VCCMCU
VCCMCU
R19
10 ohm
U2
VCCMCU
*
12
11
10
9
RF_DATA
RF_CLK
RF_CS
RF_CE
RF_DR
R4
100K
RFDATA
RFCLK
RFCS
RFCE
*
R5
100K
1
2
5
6
7
8
MSE Connecto r
1
470
LD1
RF_Data
13
SW1
BIND
RFDR
10uF
+
C13
4.7uF
2
OSCI
3
OSCO
SPCP18A-011A
C12
0.1uF
C11
4
GND
KEY
BIND/RF
SCL
SDA
XT1
6MHz
16Pin
VCCMCU
ID Button
3 / 5 Bu ttons
3Button s
5 Buttons
R4
Not Mou nted
Mounted
R5
Mounted
Not Mou nted
Notes:
The supply and ground paths should be laid out using a star methodology. Level shifting is required to
interface a 5V micro-controller to the ADNS-7050. If a
3V micro-controller is used, the 74VHC125 component shown may be omitted.
C14
0.1uF
Title
U3
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
VSS
1
2
3
4
24C01
Figure 7b. Schematic diagram for 3-button scroll wheel cordless mouse.
8
1
2
3
4
16
VC
R6
MSE_CLK/D+
MSE_DATA/D-
14
DM_DA
VDD
VCCMCU
J1
15
DP_CK
ENG. AP:
Size
B
Date:
Sunplus
2.4GHz 1way RF Mouse Receiver
Drawn:
FrankLin
Check By:
D.C.
Document Number 2.4GHZ-1W-MSE -RX-CP18 A-nRF2401-CR
of
Thu rsday, December 29, 2005
Sheet
1
2
Rev
PA4
LASER Drive Mode
LASER Power Adjustment Procedure
The laser is driven in pulsed mode during normal operation. A calibration mode is provided which drives the laser in continuous (CW) operation.
x The ambient temperature should be 25°C ±5°C.
Eye Safety
x Set the Range_C complement bit (bit 7 of register
0x1f ) to 1.
The ADNS-7050 and the associated components in the
schematic of Figure 7 are intended to comply with Class
1 Eye Safety Requirements of IEC 60825-1. Avago Technologies suggests that manufacturers perform testing to
verify eye safety on each mouse. It is also recommended
to review possible single fault mechanisms beyond those
described below in the section “Single Fault Detection”.
Under normal conditions, the ADNS-7050 generates the
drive current for the laser diode (ADNV-6340).
In order to stay below the Class 1 power requirements,
LASER_CTRL0 (register 0x1a), LASER_CTRL1 (register
0x1f ), LSRPWR_CFG0 (register 0x1c) and LSRPWR_CFG1
(register 0x1d) must be programmed to appropriate values. The system comprised of the ADNS-7050 and ADNV6340, is designed to maintain the output beam power
within Class 1 requirements over components manufacturing tolerances and the recommended temperature range when adjusted per the procedure below and
implemented as shown in the recommended application
circuit of Figure 7. For more information, please refer to
Eye Safety Application Note AN 5230.
AGND
IMAGE ARRAY
DSP
SERIAL PORT AND REGISTERS
GND
POWER AND CONTROL
AVDD
OSCILLATOR
XY_LASER
x Set the Range bit (bit 7 of register 0x1a) to 0.
x Set the Match_bit (bit 5 of register 0x1a) to the correct
value for the bin designation of the laser being used.
x Set the Match_C_bit (bit 5 of register 0x1f ) to the
complement of the Match_bit.
x Enable the Calibration mode by writing to bits [3,2,1]
of register 0x1A so the laser will be driven with 100%
duty cycle.
x Write the Calibration mode complement bits to
register 0x1f.
x Set the laser current to the minimum value by writing
0x00 to register 0x1c, and the complementary value
0xFF to register 0x1d.
x Program registers 0x1c and 0x1d with increasing
values to achieve an output power as close to 506uW
as possible without exceeding it. If this power is
obtained, the calibration is complete, skip to step 14.
x If it was not possible to achieve the power target, set
the laser current to the minimum value by writing
0x00 to register 0x1c, and the complementary value
0xff to register 0x1d.
x Set the Range and Range_C bits in registers 0x1a and
0x1f, respectively, to choose to the higher laser current
range.
ADNS-7050
VDD
x Set VDD to its permanent value.
LAZER DRIVE
Figure 8. Block diagram of ADNS-7050 optical mouse sensor.
NCS
SCLK
MOSI
MISO
MOTION
LASER_NEN
x Program registers 0x1c and 0x1d with increasing
values to achieve an output power as close to 506uW
as possible without exceeding it.
x Save the value of registers 0x1a, 0x1c, 0x1d, and 0x1f
in non-volatile memory in the mouse. These registers
must be restored to these values every time the ADNS7050 is reset.
x Reset the mouse, reload the register values from
non-volatile memory, enable Calibration mode, and
measure the laser power to verify that the calibration
is correct.
Good engineering practices such as regular power meter
calibration, random quality assurance retest of calibrated
mice, etc. should be used to guarantee performance, reliability and safety for the product design.
9
LASER Output Power
The laser beam output power as measured at the navigation surface plane is specified below. The following conditions apply:
1. The system is adjusted according to the above
procedure.
2. The system is operated within the recommended
operating temperature range.
3. The VDD value is no greater than 300mV above its
value at the time of adjustment.
4. No allowance for optical power meter accuracy is
assumed.
Disabling the LASER
LASER_NEN is connected to the gate of a P-channel
MOSFET transistor which when ON connects VDD to the
LASER. In normal operation, LASER_NEN is low. In the
case of a fault condition (ground or VDD3 at XY_LASER),
LASER_NEN goes high to turn the transistor off and disconnect VDD3 from the LASER.
Single Fault Detection
ADNS-7050 is able to detect a short circuit or fault condition at the XY_LASER pin, which could lead to excessive laser power output. A path to ground on this pin will
trigger the fault detection circuit, which will turn off the
laser drive current source and set the LASER_NEN output
Parameter
Symbol
Laser output power
LOP
Minimum
716
high. When used in combination with external components as shown in the block diagram below, the system
will prevent excess laser power for a resistive path to
ground at XY_LASER by shutting off the laser. In addition
to the ground path fault detection described above, the
fault detection circuit is continuously checked for proper
operation by internally generating a path to ground with
the laser turned off via LASER_NEN. If the XY_LASER pin
is shorted to VDD3, this test will fail and will be reported
as a fault.
Regulatory Requirements
x Passes FCC B and worldwide analogous emission
limits when assembled into a mouse with
shielded cable and following Avago Technologies
recommendations.
x Passes IEC-1000-4-3 radiated susceptibility level when
assembled into a mouse with shielded cable and
following Avago Technologies recommendations.
x Passes EN61000-4-4/IEC801-4 EFT tests when
assembled into a mouse with shielded cable and
following Avago Technologies recommendations.
x UL flammability level UL94 V-0.
x Provides sufficient ESD creepage/clearance distance
to avoid discharge up to 15 kV when assembled into a
mouse according to usage instructions above.
Maximum
Units
Notes
μW
Class 1 limit with recommended VCSEL and lens.
VDD
MICROCONTROLLER
ADNS-7050
LASER_NEN
VDD
FAULT CONTROL
BLOCK
VCSEL
SERIAL PORT
XY_LASER
VOLTAGE SENSE
CURRENT SET
GND
Figure 9. Single fault detection and eye safety feature block diagram.
10
Absolute Maximum Ratings
Parameter
Symbol
Minimum
Storage Temperature
TS
-40
Lead Solder Temp
Supply Voltage
VDD
-0.5
ESD
Input Voltage
VIN
Latchup Current
Iout
-0.5
Maximum
Units
Notes
85
ºC
260
ºC
3.7
V
2
kV
All pins, human body model MIL 883
Method 3015
VDD + 0.5
V
All Pins
20
mA
All Pins
For 10 seconds, 1.6 mm below seating
plane.
Recommended Operating Conditions
Parameter
Symbol
Minimum
Operating Temperature
TA
0
Power Supply Voltage
VDD
2.7
Power Supply Rise Time
VRT
1
Supply Noise (Sinusoidal)
VNA
Serial Port Clock Frequency
fSCLK
Distance from Lens Reference Z
Plane to Surface
Typical
2.8
2.18
2.40
Maximum
Units
40
ºC
3.6
V
Including noise
100
ms
0 to 2.8 V
100
mVp-p
10 kHz - 50 MHz
1
MHz
Active drive, 50% duty cycle
2.62
mm
Results in ±0.2 mm minimum
DOF. See Figure 10.
Speed
S
20
in/sec
Acceleration
A
8
g
Load Capacitance
Cout
100
pF
Voltage at XY_LASER
Vxy_laser
VDD
V
0.3
VCSEL PCB
SENSOR
SENSOR PCB
2.40
(0.094)
LENS
SURFACE
Figure 10. Distance from lens reference plane to surface, Z.
11
CLIP
Notes
MOTION, MISO
AC Electrical Specifications
Electrical Characteristics over recommended operating conditions. Typical values at 25 °C, VDD=2.8V.
Parameter
Symbol
Maximum
Units
Notes
Motion Delay
suming
after Reset
tMOT-RST
23
ms
From SW_RESET register write to valid motion, as-
Shutdown
tSTDWN
50
ms
From Shutdown mode active to low current
Typical
ms
From Shutdown mode inactive to valid motion.
Notes: A RESET must be asserted after a shutdown.
Refer to section “Notes on Shutdown and Forced
Rest”, also note tMOT-RST
s
From RESTEN bits set to low current
motion is present
Wake from Shutdown tWAKEUP
Forced Rest Enable
Minimum
23
tREST-EN
1
Wake from Forced Rest tREST-DIS
1
s
From RESTEN bits cleared to valid motion
MISO Rise Time
tr-MISO
150
300
ns
CL = 100 pF
MISO Fall Time
tf-MISO
150
300
ns
CL = 100 pF
MISO Delay after SCLK tDLY-MISO
120
ns
From SCLK falling edge to MISO data valid, no
load conditions
MISO Hold Time
thold-MISO 0.5
1/fSCLK
μs
Data held until next falling SCLK edge
MOSI Hold Time
thold-MOSI 200
ns
Amount of time data is valid after SCLK rising edge
MOSI Setup Time
tsetup-MOSI 120
ns
From data valid to SCLK rising edge
SPI Time between
Write Commands
tSWW
30
μs
From rising SCLK for last bit of the first data byte,
to rising SCLK for last bit of the second data byte.
SPI Time between Write tSWR
and Read Commands
20
μs
From rising SCLK for last bit of the first data byte,
to rising SCLK for last bit of the second addressbyte.
SPI Time between Read tSRW
and Subsequent tSRR
Commands
500
ns
From rising SCLK for last bit of the first data byte,
to falling SCLK for the first bit of the address byte
of the next command.
SPI Read Address-Data tSRAD
Delay
4
μs
From rising SCLK for last bit of the address byte, to
falling SCLK for first bit of data being read.
NCS Inactive after
Motion Burst
tBEXIT
500
ns
Minimum NCS inactive time after motion burst
before next SPI usage
NCS to SCLK Active
tNCS-SCLK
120
ns
From NCS falling edge to first SCLK rising edge
SCLK to NCS Inactive
(for Read Operation)
tSCLK-NCS
120
ns
From last SCLK rising edge to NCS rising edge, for
valid MISO data transfer
SCLK to NCS Inactive
(for Write Operation)
tSCLK-NCS
20
μs
From last SCLK rising edge to NCS rising edge, for
valid MOSI data transfer
NCS to MISO High-Z
tNCS-MISO
500
ns
From NCS rising edge to MISO high-Z state
MOTION Rise Time
tr-MOTION
150
300
ns
CL = 100 pF
MOTION Fall Time
tf-MOTION
150
300
ns
CL = 100 pF
Transient Supply
Current
IDDT
45
mA
Max supply current during a VDD ramp from 0 to 2.8 V
12
DC Electrical Specifications
Electrical Characteristics over recommended operating conditions. Typical values at 25 °C, VDD=2.8 V.
Parameter
Symbol
DC Supply Current in
Various Modes
IDD_RUN
IDD_REST1
IDD_REST2
IDD_REST3
Minimum
Typical
Maximum
Units
Notes
4
0.5
0.15
0.05
10
1.8
0.4
0.15
mA
Average current, including LASER current.
No load on MISO, MOTION.
40
mA
12
μA
NCS, SCLK = VDD
MOSI = GND
MISO = Hi-Z
0.5
V
SCLK, MOSI, NCS
Peak Supply Current
Shutdown Supply
Current
IDDSTDWN
Input Low Voltage
VIL
1
Input High Voltage
VIH
Input Hysteresis
VI_HYS
100
Input Leakage Current
Ileak
±1
XY_LASER Current
ILAS
0.8
LASER Current
(Fault Mode)
ILAS_FAULT
Output Low Voltage,
MISO, LASER_NEN
VOL
Output High Voltage,
MISO, LASER_NEN
VOH
Input Capacitance
Cin
13
VDD – 0.5
V
SCLK, MOSI, NCS
mV
SCLK, MOSI, NCS
μA
Vin = VDD -0.6 V, SCLK, MOSI, NCS
mA
Vxy_laser ≥ 0.3 V
LASER_CTRL0 = 0X80
LASER CTRL1 = 0X20
LP_CFG0 = 0xFF
LP_CFG1 = 0x00
300
uA
XY_LASER Rleakage < 75 kOhms to GND
0.7
V
Iout = 1 mA, MISO, MOTION
Iout = 1 mA, LASER_NEN
V
Iout = -1 mA, MISO, MOTION
Iout = -0.5 mA, LASER_NEN
pF
MOSI, NCS, SCLK
±10
VDD – 0.7
10
Typical Performance Characteristics
Typical Resolution vs. Z
1000
Resolution (counts/inches)
900
800
700
600
500
400
1.6 1.7
1.8 1.9
2
2.1
2.2 2.3 2.4 2.5
2.6 2.7 2.8 2.9
3
3.1 3.2 3.3 3.4
Distance from Lens Reference Plane to Surface, Z (mm)
Photo Paper
White Melamine Bookshelf
Manila
Black Formica
White Paper
Figure 11. Mean resolution vs. Z at 800 cpi.
Maximum Distance (mouse count)
Typical Path Deviation Largest Single Perpendicular Deviation From A Straight Line At 45
Degrees Path Length = 4 inches; Speed = 6 ips ; Resolution = 800 cpi
50
45
40
35
30
25
20
15
10
5
0
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
Distance From Lens Reference Plane To Surface, Z (mm)
Photo Paper
White Melamine Bookshelf
Figure 12. Average error vs. distance at 800 cpi .
RELATIVE RESPONSIVITY for ADNS-7050
1.0
RELATIVE RESPONSIVITY
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
400
500
600
700
800
WAVELENGTH (nm)
Figure 13. Wavelength responsivity.
14
900
1000
Manila
Black Formica
White Paper
Power Management Modes
The ADNS-7050 has three power-saving modes. Each
mode has a different motion detection period, affecting
response time to mouse motion (Response Time). The
sensor automatically changes to the appropriate mode,
depending on the time since the last reported motion
(Downshift Time). The parameters of each mode are
shown in the following table.
Mode
Response Time (nominal)
Downshift Time (nominal)
Rest 1
16.5 ms
237 ms
Rest 2
82 ms
8.4 s
Rest 3
410 ms
504 s
Motion Pin Timing
The motion pin is a level-sensitive output that signals the
micro-controller when motion has occurred. The motion
pin is lowered whenever the motion bit is set; in other
words, whenever there is data in the Delta_X or Delta_Y
registers. Clearing the motion bit (by reading Delta_X
and Delta_Y, or writing to the Motion register) will put
the motion pin high.
LASER Mode
For power savings, the VCSEL will not be continuously
on. ADNS-7050 will flash the VCSEL only when needed.
Synchronous Serial Port
The synchronous serial port is used to set and read parameters in the ADNS-7050, and to read out the motion
information.
The port is a four-wire port. The host micro-controller
always initiates communication; the ADNS-7050 never
initiates data transfers. SCLK, MOSI, and NCS may be driven directly by a micro-controller. The port pins may be
shared with other SPI slave devices. When the NCS pin is
high, the inputs are ignored and the output is tri-stated.
The lines that comprise the SPI port:
SCLK:
Clock input. It is always generated by the
master (the microcontroller).
MOSI:
Input data. (Master Out/Slave In)
MISO:
Output data. (Master In/Slave Out)
NCS:
Chip select input (active low). NCS needs to be
low to activate the serial port; otherwise, MISO
will be high Z, and MOSI & SCLK will be ignored.
NCS can also be used to reset the serial port in
case of an error.
Chip Select Operation
The serial port is activated after NCS goes low. If NCS
is raised during a transaction, the entire transaction is
aborted and the serial port will be reset. This is true for
all transactions. After a transaction is aborted, the normal address-to-data or transaction-to-transaction delay
is still required before beginning the next transaction.
To improve communication reliability, all serial transactions should be framed by NCS. In other words, the port
should not remain enabled during periods of non-use
because ESD and EFT/B events could be interpreted as
NCS
1
2
3
4
5
6
7
8
9
10
11
12
13
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
14
15
16
1
2
SCLK
MOSI
1
MISO
MOSI DRIVEN BY MICRO-CONTROLLER
Figure14. Write operation.
SCLK
MOSI
thold, MOSI
tsetup, MOSI
Figure 15. MOSI setup and hold time.
15
D2
D1
D0
1
A6
Read Operation
serial communication and put the chip into an unknown
state. In addition, NCS must be raised after each burstmode transaction is complete to terminate burst-mode.
The port is not available for further use until burst-mode
is terminated.
A read operation, defined as data going from the ADNS7050 to the micro-controller, is always initiated by the
micro-controller and consists of two bytes. The first byte
contains the address, is sent by the micro-controller over
MOSI, and has a “0” as its MSB to indicate data direction.
The second byte contains the data and is driven by the
ADNS-7050 over MISO. The sensor outputs MISO bits on
falling edges of SCLK and samples MOSI bits on every rising edge of SCLK.
Write Operation
Write operation, defined as data going from the microcontroller to the ADNS-7050, is always initiated by the
micro-controller and consists of two bytes. The first byte
contains the address (seven bits) and has a “1” as its MSB
to indicate data direction. The second byte contains
the data. The ADNS-7050 reads MOSI on rising edges of
SCLK.
NCS
SCLK
CYCLE #
1
2
3
4
5
6
7
A6
A5
A4
A3
A2
A1
8
9
10
11
12
13
14
15
16
SCLK
1
MOSI
A0
D7
MISO
D6
D5
D4
D3
D2
D1
D0
tSRAD DELAY
Figure 16. Read operation.
SCLK
tHOLD-MISO
tDLY-MISO
MISO
D0
Figure 17. MISO delay and hold time.
Note:
The 0.5/fSCLK minimums high state of SCLK is also the minimum MISO
data hold time of the ADNS-7050. Since the falling edge of SCLK is actually the start of the next read or write command, the ADNS-7050 will
hold the state of data on MISO until the falling edge of SCLK.
Required Timing Between Read and Write Commands
There are minimum timing requirements between read
and write commands on the serial port.
tSWW
SCLK
ADDRESS
DATA
WRITE OPERATION
Figure 18. Timing between two write commands.
16
ADDRESS
DATA
WRITE OPERATION
If the rising edge of the SCLK for the last data bit of the
second write command occurs before the required delay
(tSWW ), then the first write command may not complete
correctly.
If the rising edge of SCLK for the last address bit of the
read command occurs before the required delay (tSWR),
the write command may not complete correctly.
tSWR
SCLK
ADDRESS
DATA
ADDRESS
WRITE OPERATION
NEXT READ OPERATION
Figure 19. Timing between write and read commands.
tSRW & tSRR
tSRAD
SCLK
ADDRESS
DATA
ADDRESS
READ OPERATION
NEXT READ
or WRITE OPERATION
Figure 20. Timing between read and either write or subsequent read commands.
During a read operation SCLK should be delayed at least
tSRAD after the last address data bit to ensure that the
ADNS-7050 has time to prepare the requested data. The
falling edge of SCLK for the first address bit of either the
read or write command must be at least tSRR or tSRW after
the last SCLK rising edge of the last data bit of the previous read operation.
Burst Mode Operation
Burst mode is a special serial port operation mode that
may be used to reduce the serial transaction time for a
motion read. The speed improvement is achieved by continuous data clocking to or from multiple registers without the need to specify the register address, and by not
requiring the normal delay period between data bytes.
Burst mode is activated by reading the Motion_Burst
register. The ADNS-7050 will respond with the contents
of the Motion, Delta_X, Delta_Y, SQUAL, Shutter_Upper,
Shutter_Lower, and Maximum_Pixel registers in that order. The burst transaction can be terminated anywhere
in the sequence after the Delta_X value by bringing the
NCS pin high. After sending the register address, the micro-controller must wait tSRAD and then begin reading
data. All data bits can be read with no delay between
bytes by driving SCLK at the normal rate. The data are
latched into the output buffer after the last address bit
is received. After the burst transmission is complete, the
micro-controller must raise the NCS line for at least tBEXIT
to terminate burst mode. The serial port is not available
for use until it is reset with NCS, even for a second burst
transmission.
tSRAD
SCLK
MOTION_BURST REGISTER ADDRESS
READ FIRST BYTE
FIRST READ OPERATION
Figure 21. Motion burst timing.
17
READ SECOND BYTE
READ THIRD BYTE
Notes on Power-up
Notes on Shutdown and Forced Rest
The ADNS-7050 does not perform an internal power up
self-reset; the POWER_UP_RESET register must be written
every time power is applied. The appropriate sequence is
as follows:
The ADNS-7050 can be set in Rest mode through the
Configuration_Bits register (0x11). This is to allow for
further power savings in applications where the sensor
does not need to operate all the time.
1. Apply power
The ADNS-7050 can be set in Shutdown mode by writing
0xe7 to register 0x3b. The SPI port should not be accessed
when Shutdown mode is asserted, except the power-up
command (writing 0x5a to register 0x3a). (Other ICs on
the same SPI bus can be accessed, as long as the sensor’s
NCS pin is not asserted.) The table below shows the state
of various pins during shutdown. To deassert Shutdown
mode:
2. Drive NCS high, then low to reset the SPI port
3. Write 0x5a to register 0x3a
4. Wait for tWAKEUP
5. Write 0xFE to register 0x28
6. Read from registers 0x02, 0x03, and 0x04 (or read
these same 3 bytes from burst motion register 0x42)
one time regardless of the motion pin state.
During power-up there will be a period of time after the
power supply is high but before any clocks are available.
The table below shows the state of the various pins during power-up and reset.
1. Write 0x5a to register 0x3a.
2. Wait for tWAKEUP.
3. Write 0xFE to register 0x28.
4. Any register settings must then be reloaded.
State of Signal Pins after VDD is Valid
Pin
On Power-Up
NCS High before Reset
NCS Low before Reset
After Reset
NCS
Functional
Hi
Low
MISO
Undefined
Undefined
Functional
Depends on NCS
SCLK
Ignored
Ignored
Functional
Depends on NCS
MOSI
Ignored
Ignored
Functional
Depends on NCS
XY_LASER
Undefined
Undefined
Undefined
Functional
MOTION
Undefined
Undefined
Undefined
Functional
LASER_NEN
Undefined
Undefined
Undefined
Functional
Functional
Pin
Status when Shutdown Mode
NCS
Functional*1
MISO
Undefined*2
*1 NCS pin must be held to 1 (high) if SPI bus is shared with other
devices. It is recommended to hold to 1 (high) during Power Down
unless powering up the Sensor. It must be held to 0 (low) if the
sensor is to be re-powered up from shutdown (writing 0x5a to
register 0x3a).
SCLK
Ignore if NCS = 1*3
*2 Depend on last state.
MOSI
Ignore if NCS = 1*4
*3 SCLK is ignore if NCS is 1 (high). It is functional if NCS is 0 (low).
XYLASER
High(Off )
LASER_NEN
High(Off )
MOTION
Undefined *2
*4 MOSI is ignore if NCS is 1 (high). If NCS is 0 (low), any command
present on the MOSI pin will be ignored except power-up command
(writing 0x5a to register 0x3a).
Note:
There are long wakeup times from shutdown and forced Rest. These
features should not be used for power management during normal
mouse motion.
18
Registers
The ADNS-7050 registers are accessible via the serial port. The registers are used to read motion data and status as
well as to set the device configuration.
Address
Register
Read/Write
Default Value
0x00
Product_ID
R
0x23
0x01
Revision_ID
R
0x03
0x02
Motion
R/W
0x00
0x03
Delta_X
R
0x00
0x04
Delta_Y
R
0x00
0x05
SQUAL
R
0x00
0x06
Shutter_Upper
R
0x00
0x07
Shutter_Lower
R
0x64
0x08
Maximum_Pixel
R
0xd0
0x09
Pixel_Sum
R
0x80
0x0a
Minimum_Pixel
R
0x00
0x0b
Pixel_Grab
R/W
0x00
0x0c
CRC0
R
0x00
0x0d
CRC1
R
0x00
0x0e
CRC2
R
Undefined
0x0f
CRC3
R
Undefined
0x10
Self_Test
W
NA
0x11
Configuration_Bits
R/W
0x03
0x12-0x19
Reserved
0x1a
LASER_CTRL0
R/W
0x00
0x1b
Reserved
0x1c
LSRPWR_CFG0
R/W
0x00
0x1d
LSRPWR_CFG1
R/W
0x00
0x1e
Reserved
0x1f
LASER_CTRL1
R/W
0x01
0x20-0x2d
Reserved
0x2e
Observation
R/W
Undefined
0x2f-0x39
Reserved
0x3a
POWER_UP_RESET
W
NA
0x3b
Shutdown
W
NA
0x3c-0x3d
Reserved
0x3e
Inverse_Revision_ID
R
0xfc
0x3f
Inverse_Product_ID
R
0xdc
0x42
Motion_Burst
R
0x00
19
Product_ID
Address: 0x00
Access: Read
Reset Value: 0x23
Bit
Field
7
PID7
6
PID6
5
PID5
4
PID4
3
PID3
2
PID2
1
PID1
0
PID0
Data Type: 8-Bit unsigned integer
USAGE: This register contains a unique identification assigned to the ADNS-7050. The value in this register does not
change; it can be used to verify that the serial communications link is functional.
Revision_ID
Address: 0x01
Access: Read
Reset Value: 0x03
Bit
Field
7
RID7
6
RID6
5
RID5
4
RID4
3
RID3
2
RID2
1
RID1
Data Type: 8-Bit unsigned integer
USAGE: This register contains the IC revision. It is subject to change when new IC versions are released.
20
0
RID0
Motion
Address: 0x02
Access: Read/Write
Bit
Field
served
Reset Value: 0x00
7
MOT
6
PIXRDY
5
PIXFIRST
4
OVF
3
2
LP_VALID FAULT
1
0
Reserved Re-
Data Type: Bit field
USAGE: Register 0x02 allows the user to determine if motion has occurred since the last time it was read. If the MOT
bit is set, then the user should read registers 0x03 and 0x04 to get the accumulated motion. Read this register before
reading the Delta_X and Delta_Y registers.
Writing anything to this register clears the MOT and OVF bits, Delta_X and Delta_Y registers. The written data byte is
not saved.
Internal buffers can accumulate more than eight bits of motion for X or Y. If either one of the internal buffers overflows, then absolute path data is lost and the OVF bit is set. To clear the overflow, write anything to this register.
Check the OVR bit if more than 4” of motion is accumulated without reading it. If bit set, discard the motion as erroneous. Write anything to this register to clear the overflow condition.
The PIXRDY bit will be set whenever a valid pixel data byte is available in the Pixel_Dump register. Check that this
bit is set before reading from Pixel_Dump. To ensure that the Pixel_Grab pointer has been reset to pixel 0,0 on the
initial write to Pixel_Grab, check to see if PIXFIRST is set to high.
Field Name
Description
MOT
Motion since last report
0 = No motion
1 = Motion occurred, data ready for reading in Delta_X and Delta_Y registers
PIXRDY
Pixel Dump data byte is available in Pixel_Dump register.
0 = Data not available
1 = Data available
PIXFIRST
This bit is set when the Pixel_Grab register is written to or when a complete pixel array has been read, initiating an
increment to pixel 0,0.
0 = Pixel_Grab data not from pixel 0,0
1 = Pixel_Grab data is from pixel 0,0
OVF
Motion overflow, ∆Y and/or ∆X buffer has overflowed since last report.
0 = No overflow
1 = Overflow has occurred
LP_VALID
Laser Power Settings
0 = Register 0x1a and register 0x1f or register 0x1c and register 0x1d do not have complementary values.
1 = Laser power is valid
FAULT
Indicates that XY_LASER is shorted to GND or VDD
0 = No fault detected
1 = Fault detected.
NOTE: Avago Technologies recommends that registers 0x02, 0x03, and 0x04 be read sequentially.
21
Delta X
Address: 0x03
Access: Read
Reset Value: 0x00
Bit
Field
7
X7
6
X6
5
X5
4
X4
3
X3
2
X2
1
X1
0
X0
Data Type: Eight bit 2’s complement number
USAGE: X movement is counts since last report. Absolute value is determined by resolution. Reading clears the register.
MOTION
-128
-127
-2
-1
0
+1
+2
+126
+127
DELTA_X
80
81
FE
FF
00
01
02
7E
7F
NOTE: Avago Technologies recommends that registers 0x02, 0x03, and 0x04 be read sequentially.
Delta Y
Address: 0x04
Access: Read
Reset Value: 0x00
Bit
Field
7
Y7
6
Y6
5
Y5
4
Y4
3
Y3
2
Y2
1
Y1
0
Y0
Data Type: Eight bit 2’s complement number
USAGE: Y movement is counts since last report. Absolute value is determined by resolution. Reading clears the register.
MOTION
-128
-127
-2
-1
0
+1
+2
+126
+127
DELTA_Y
80
81
FE
FF
00
01
02
7E
7F
NOTE: Avago Technologies recommends that registers 0x02, 0x03, and 0x04 be read sequentially.
22
Squal
Address: 0x05
Access: Read
Reset Value: 0x00
Bit
Field
7
SQ7
6
SQ6
5
SQ5
4
SQ4
3
SQ3
2
SQ2
1
SQ1
0
SQ0
Data Type: Upper 8 bits of a 9-bit unsigned integer
USAGE: SQUAL (Surface Quality) is a measure of the number of valid features visible by the sensor in the current
frame.
The maximum SQUAL register value is 162. Since small changes in the current frame can result in changes in SQUAL,
variations in SQUAL when looking at a surface are expected. The graph below shows 250 sequentially acquired SQUAL
values, while a sensor was moved slowly over white paper. SQUAL is nearly equal to zero, if there is no surface below
the sensor. SQUAL is typically maximized when the navigation surface is at the optimum distance from the imaging
lens (the nominal Z-height).
SQUAL Value (White Paper)
At Z = 0 mm, Circle@7.5" diameter, Speed-6ips
Squal Value
160
140
120
100
1
45
89 133 177 221 265 309 353 397 441 485 529 573 617 661 705 749 793 837 881
Count
Figure 22. SQUAL values at 800cpi (white paper).
Mean SQUAL vs. Z (White Paper)
800dpi, Circle@7.5" diameter, Speed-6ips
Squal count
160
140
Avg-3sigma
Avg-3sigma
Avg
Avg
Avg+3sigma
Avg+3sigma
120
100
80
1.6
1.8
2
2.2
2.4
2.6
2.8
Distance of Lens Reference Plane to Surface,
Z (mm)
Figure 23. Mean SQUAL vs. Z (white paper).
23
3
3.2
Shutter_Upper
Address: 0x06
Access: Read
Reset Value: 0x00
Bit
Field
7
S15
Shutter_Lower
Address: 0x07
Access: Read
Reset Value: 0x64
Bit
Field
7
S7
6
S14
5
S13
4
S12
3
S11
2
S10
1
S9
0
S8
6
S6
5
S5
4
S4
3
S3
2
S2
1
S1
0
S0
Data Type: Sixteen bit unsigned integer
USAGE: Units are clock cycles. Read Shutter_Upper first, then Shutter_Lower. They should be read consecutively. The
shutter is adjusted to keep the average and maximum pixel values within normal operating ranges. The shutter value
is automatically adjusted.
Shutter Value (White Paper)
At Z = 0 mm, Circle@7.5" diameter, Speed-6ips
Shutter Value
160
140
120
100
1
42
83 124 165 206 247 288 329 370 411 452 493 534 575 616 657 698 739 780 821 862
Count
Figure 24. Shutter values at 800cpi (white paper).
Mean Shutter vs. Z (White paper)
800dpi, Circle@7.5" diameter, Speed-6ips
Shutter value (Count)
160
150
140
Avg-3sigma
130
Avg
120
Avg+3sigma
110
100
1.6
1.8
2
2.2
2.4
2.6
2.8
3
Distance of Lens Reference Plane to Surface, Z
(mm)
Figure 25. Mean shutter vs. Z (white paper).
24
3.2
Maximum_Pixel
Address: 0x08
Access: Read
Reset Value: 0xd0
Bit
Field
7
MP7
6
MP6
5
MP5
4
MP4
3
MP3
2
MP2
1
MP1
0
MP0
Data Type: Eight-bit number
USAGE: Maximum Pixel value in current frame. Minimum value = 0, maximum value = 254. The maximum pixel value
can vary with every frame.
Pixel_Sum
Address: 0x09
Access: Read
Reset Value: 0x80
Bit
Field
7
AP7
6
AP6
5
AP5
4
AP4
3
AP3
2
AP2
1
AP1
0
AP0
Data Type: High 8 bits of an unsigned 17-bit integer
USAGE: This register is used to find the average pixel value. It reports the upper eight bits of a 17-bit counter, which
sums all pixels in the current frame. It may be described as the full sum divided by 512. To find the average pixel value,
use the following formula:
Average Pixel = Register Value * 512/484 = Register Value * 1.058
The maximum register value is 241. The minimum is 0. The pixel sum value can change on every frame.
25
Minimum_Pixel
Address: 0x0a
Access: Read
Reset Value: 0x00
Bit
Field
7
MP7
6
MP6
5
MP5
4
MP4
3
MP3
2
MP2
1
MP1
0
MP0
Data Type:Eight-bit number
USAGE: Minimum Pixel value in current frame. Minimum value = 0, maximum value = 254. The minimum pixel value
can vary with every frame.
Pixel_Grab
Address: 0x0b
Access: Read
Reset Value: 0x00
Bit
Field
Data Type:
7
PD7
6
PD6
5
PD5
4
PD4
3
PD3
2
PD2
1
PD1
0
PD0
Eight-bit word
USAGE: For test purposes, the sensor will read out the contents of the pixel array, one pixel per frame. To start a pixel
grab, write anything to this register to reset the pointer to pixel 0,0. Then read the PIXRDY bit in the Motion register.
When the PIXRDY bit is set, there is valid data in this register to read out. After the data in this register is read, the
pointer will automatically increment to the next pixel. Reading may continue indefinitely; once a complete frame’s
worth of pixels has been read, PIXFIRST will be set to high to indicate the start of the first pixel and the address pointer
will start at the beginning location again.
26
0
22
44
66
1
23
45
67
89 111 133 155 177 199 221 243 265 287 309 331 353 375 397 419 441 463
2
24
46
68
90 112 134 156 178 200 222 244 266 288 310 332 354 376 398 420 442 464
3
25
47
69
91 113 135 157 179 201 223 245 267 289 311 333 355 377 399 421 443 465
4
26
48
70
92 114 136 158 180 202 224 246 268 290 312 334 356 378 400 422 444 466
5
27
49
71
93 115 137 159 181 203 225 247 269 291 313 335 357 379 401 423 445 467
6
28
50
72
94 116 138 160 182 204 226 248 270 292 314 336 358 380 402 424 446 468
7
29
51
73
95 117 139 161 183 205 227 249 271 293 315 337 359 381 403 425 447 469
8
30
52
74
96 118 140 162 184 206 228 250 272 294 316 338 360 382 404 426 448 470
9
31
53
75
97 119 141 163 185 207 229 251 273 295 317 339 361 383 405 427 449 471
98 120 142 164 186 208 230 252 274 296 318 340 362 384 406 428 450 472
10
32
54
76
11
33
55
77
99 121 143 165 187 209 231 253 275 297 319 341 363 385 407 429 451 473
12
34
56
78
100 122 144 166 188 210 232 254 276 298 320 342 364 386 408 430 452 474
13
35
57
79
101 123 145 167 189 211 233 255 277 299 321 343 365 387 409 431 453 475
14
36
58
80
102 124 146 168 190 212 234 256 278 300 322 344 366 388 410 432 454 476
15
37
59
81 103 125 147 169 191 213 235 257 279 301 323 345 367 389 411 433 455 477
16
38
60
82 104 126 148 170 192 214 236 258 280 302 324 346 368 390 412 434 456 478
17
39
61
83 105 127 149 171 193 215 237 259 281 303 325 347 369 391 413 435 457 479
18
40
62
84 106 128 150 172 194 216 238 260 282 304 326 348 370 392 414 436 458 480
19
41
63
85 107 129 151 173 195 217 239 261 283 305 327 349 371 393 415 437 459 481
20
42
64
86 108 130 152 174 196 218 240 262 284 306 328 350 372 394 416 438 460 482
21
43
65
87 109 131 153 175 197 219 241 263 285 307 329 351 373 395 417 439 461 483
LAST PIXEL
Figure 26. Pixel address map (looking through the ADNS-6130-001 or ADNS-6120 lens).
27
TOP X-RAY VIEW OF MOUSE
88 110 132 154 176 198 220 242 264 286 308 330 352 374 396 418 440 462
LB
POSITIVE Y
FIRST PIXEL
RB
A7050
XYYWWZ
POSITIVE X
CRC0
Address: 0x0c
Access: Read
Reset Value: 0x00
Bit
Field
7
CRC07
6
CRC06
5
CRC05
4
CRC04
3
CRC03
2
CRC02
1
CRC01
0
CRC00
Data Type: Eight-bit number
USAGE: Register 0x0c reports the first byte of the system self test results. Value = 05. See Self Test register 0x10.
CRC1
Address: 0x0d
Access: Read
Reset Value: 0x00
Bit
Field
7
CRC17
6
CRC16
5
CRC15
4
CRC14
3
CRC13
2
CRC12
1
CRC11
0
CRC10
Data Type: Eight-bit number
USAGE: Register 0x0c reports the second byte of the system self test results. Value = 9A. See Self Test register 0x10.
CRC2
Address: 0x0e
Access: Read
Reset Value: 0x00
Bit
Field
7
CRC27
6
CRC26
5
CRC25
4
CRC24
3
CRC23
2
CRC22
1
CRC21
0
CRC20
Data Type: Eight-bit number
USAGE: Register 0x0e reports the third byte of the system self test results. Value = CA. See Self Test register 0x10.
CRC3
Address: 0x0f
Access: Read
Reset Value: 0x00
Bit
Field
7
CRC37
6
CRC36
5
CRC35
4
CRC34
3
CRC33
2
CRC32
1
CRC31
0
CRC30
Data Type: Eight-bit number
USAGE: Register 0x0f reports the fourth byte of the system self test results. Value = 0B. See Self Test register 0x10.
28
Self_Test
Address: 0x10
Access: Write
Reset Value: NA
Bit
Field
7
6
5
4
3
2
1
0
Reserved Reserved Reserved Reserved Reserved Reserved Reserved TESTEN
Data Type: Bit field
USAGE: Set the TESTEN bit in register 0x10 to start the system self-test. The test takes 250ms. During this time, do not
write or read through the SPI port. Results are available in the CRC0-3 registers. After self-test, reset the chip to start
normal operation.
Field Name
Description
TESTEN
Enable System Self Test
0 = Disabled
1 = Enable
Configuration_bits
Address: 0x11
Access: Read/Write
Reset Value: 0x03
Bit
Field
7
RES
6
Reserved
5
RESTEN1
4
RESTEN0
3
2
Reserved Reserved
1
Reserved
0
Reserved
Data Type: Bit field
USAGE: Register 0x11 allows the user to change the configuration of the sensor. Setting the RESTEN1-0 bits forces
the sensor into Rest mode, as described in the power modes section above. The RES bit allows selection between 400
and 800 cpi resolution.
Note: Forced Rest has a long wakeup time and should not be used for power management during normal mouse motion.
29
Field Name
Description
RESTEN1-0
Puts chip into Rest mode
00 = normal operation
01 = force Rest1
11 = force Rest3
RES
Sets resolution
0 = 400
1 = 800
Reserved
Address: 0x12-0x19
LASER_CTRL0
Address: 0x1a
Access: Read/Write
Reset Value: 0x00
Bit
Field
7
Range
6
Reserved
5
Match_bit
4
Reserved
3
CAL2
2
CAL1
1
CAL0
0
Force_Disable
Data Type: Bit field
USAGE: This register is used to control the laser drive. Bits 5 and 7 require complement values in register 0x1F. If the
registers do not contain complementary values for these bits, the laser is turned off and the LP_VALID bit in the MOTION register is set to 0. The registers may be written in any order after the power ON reset.
Field Name
Description
Range
Rbin Settings
0 = Laser current range from approximately 2 mA to 7 mA
1 = Laser current range from approximately 5 mA to 13 mA
Match_bit
Match the sensor to the laser characteristics. Set per the bin table specification for the laser in use based
on the bin letter.
CAL2-0
VCSEL Bin Number
Match_bit
2A
0
3A
0
Laser calibration mode
- Write 101b to bits [3,2,1] to set the laser to continuous ON (CW) mode.
- Write 000b to exit laser calibration mode, all other values are not recommended.
Reading the Motion register (0x03 or 0x42) will reset the value to 000b and exit calibration mode.
Force_Disable LASER force disabled
0 = LASER_NEN functions as normal
1 = LASER_NEN output is high.
Reserved
30
Address: 0x1b
LSRPWR_CFG0
Access: Read and Write
Bit
Field
Data Type:
Address: 0x1c
Reset Value: 0x00
7
LP7
6
LP6
5
LP5
4
LP4
3
LP3
2
LP2
1
LP1
0
LP0
8 Bit unsigned
USAGE: This register is used to set the laser current. It is to be used together with register 0x1D, where register 0x1D
contains the complement of register 0x1C. If the registers do not contain complementary values, the laser is
turned off and the LP_VALID bit in the MOTION register is set to 0. The registers may be written in any order
after the power ON reset.
Field Name
Description
LP7 – LP0
Controls the 8-bit DAC for adjusting laser current.
One step is equivalent to (1/384)*100% = 0.26% drop of relative laser current.
Refer to the table below for examples of relative laser current settings.
LP7 - LP3
LP 2
LP 1
LP 0
Relative Laser Current
00000
0
0
0
33.59%
00000
0
0
1
33.85%
00000
0
1
0
34.11%
: :
:
:
:
: :
11111
1
0
1
99.48%
11111
1
1
0
99.74%
11111
1
1
1
100%
LSRPWR_CFG1
Access: Read and Write
Bit
Field
Data Type:
Address: 0x1d
Reset Value: 0x00
7
LPC7
6
LPC6
5
LPC5
4
LPC4
3
LPC3
2
LPC2
1
LPC1
0
LPC0
8 Bit unsigned
USAGE: The value in this register must be a complement of register 0x1C for laser current to be as programmed,
otherwise the laser is turned off and the LP_VALID bit in the MOTION register is set to 0. Registers 0x1C and
0x1D may be written in any order after power ON reset.
Reserved
31
Address: 0x1e
LASER_CTRL1
Access: Read and Write
Bit
Field
Data Type:
Address: 0x1f
Reset Value: 0x01
7
Range_C
6
Reserved
5
4
3
Match_bit_C Reserved Reserved
2
Reserved
1
Reserved
0
Reserved
8 Bit unsigned
USAGE: Bits 5 and 7 of this register must be the complement of the corresponding bits in register 0x1A for the VCSEL control to be as progrmmed, otherwise the laser turned is off and the LP_VALID bit in the MOTION register is set
to 0. Registers 0x1A and 0x1F may be written in any order after power ON reset.
Reserved
Address: 0x20-0x2d
Observation
Access: Read/Write
Address: 0x2e
Reset Value: 0x00
Bit
Field
Data Type:
7
MODE1
6
MODE0
5
4
Reserved OBS4
3
OBS3
2
OBS2
1
OBS1
0
OBS0
Bit field
USAGE: Register 0x2e provides bits that are set every frame. It can be used during EFT/B testing to check that the
chip is running correctly. Writing anything to this register will clear the bits.
Field Name
Description
MODE1-0
Mode Status: Reports which mode the sensor is in.
00 = Run
01 = Rest 1
10 = Rest 2
11 = Rest 3
OBS4-0
Updated on every frame
Reserved
32
Address: 0x2f-0x39
POWER_UP_RESET
Access: Write
Address: 0x3a
Reset Value: NA
Bit
Field
Data Type:
7
RST7
6
RST6
5
RST5
4
RST4
3
RST3
2
RST2
1
RST1
0
RST0
8-bit integer
USAGE: Write 0x5a to this register to reset the chip. All settings will revert to default values. Reset is required after
recovering from shutdown mode.
SHUTDOWN
Access: Write Only
Bit
Field
Data Type:
Address: 0x3b
Reset Value: NA
7
SD7
6
SD 6
5
SD 5
4
SD 4
3
SD 3
2
SD 2
1
SD 1
0
SD 0
8-bit integer
USAGE: Write 0xe7 to set the chip to shutdown mode, use POWER_UP_RESET register (address 0x3b) to power up
the chip.
Reserved
Address: 0x3c-0x3d
Inverse_Revision_ID
Access: Read
Address: 0x3e
Reset Value: 0xfc
Bit
Field
7
NRID7
6
NRID6
5
NRID5
4
NRID4
3
NRID3
2
NRID2
1
NRID1
Data Type: Inverse 8-Bit unsigned integer
USAGE:
33
This value is the inverse of the Revision_ID. It can be used to test the SPI port.
0
NRID0
Inverse_Product_ID
Access: Read
Bit
Field
Address: 0x3f
Reset Value: 0xdc
7
NPID7
6
NPID6
5
NPID5
4
NPID4
3
NPID3
2
NPID2
1
NPID1
0
NPID0
1
MB1
0
MB0
Data Type: Inverse 8-Bit unsigned integer
USAGE: This value is the inverse of the Product_ID. It can be used to test the SPI port.
Motion_Burst
Access: Read
Address: 0x42
Reset Value: 0x00
Bit
Field
7
MB7
6
MB6
5
MB5
4
MB4
3
MB3
2
MB2
Data Type: Various
USAGE: Read from this register to activate burst mode. The sensor will return the data in the Motion register,
Delta_X, Delta_Y, Squal, Shutter_Upper, Shutter_Lower, and Maximum_Pixel. Reading the first 3 bytes clears
the motion data. The read may be terminated anytime after Delta_X is read.
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved.
AV02-1411EN - December 4, 2009