AEAT-86AD-LASF0

AEAT-86AD 14/12 Bit Multi-turn Encoder Module with Built-in Controller Data Sheet Description Features The AEAT-86AD provides all functions as an optoelectronic mechanical unit in order to implement, with single turn absolute encoder, an absolute multi-turn encoder with a combined capacity of up to 30 bits at extended temperature. • 16384 (14bits) and 4096 (12bits) revolution count versions The unit consists of an LED circuit board, a phototransistor (PT) circuit board, and gear train arranged in between the PCBs. The built-in controller combined positional information from single turn absolute encoder and multiturn absolute encoder. It provides control inputs and signal outputs to application end. The integrated RS-422 differential line driver output and line receiver are for noise immunity in transmission line. Specifications The multi-turn unit is available in the following versions: • 12-bit solid shaft with Binary output code • 14-bit solid shaft with Binary output code • 12-bit solid shaft with Gray output code • 14-bit solid shaft with Gray output code • Optical, absolute multi-turn assembly with max. Ø55 mm and typical height 13.3 mm. • Operating temperatures of -40°C to +125°C • Mechanical coupling by means of gear wheels with module of 0.3 • Operating speeds up to 12,000 rpm • A 2x4-pole pin strip for power supply and signal • Integrated RS422 line driver and receiver Applications • Major component of Multi-turn housed encoder • Cost effective solution for direct integration into OEM systems • Revolution detection Benefits • No battery or capacitor required for number of revolution counting during power failure • Immediate position detection on power up Package Dimensions Notes: 1. 3rd angle Projection 2. Dimensions are in millimeters 3. General tolerance: ±0.05, unless specified otherwise Figure 1. Package dimensions 1 2 3 5 S21 S1 S22 S2 1, S20 - A0N 2, S17 - A0P 3, S18 - A09N 4, S15 - A09P 5, S5 - STCAL M1 - GND M2 - DATA M3 - DATA+ M4 - VCC M5 - MSBINV M6 - STROBE M7 - SRCLKM8 - SRCLK+ Figure 2. Pin Configuration  Block Diagram and Detailed Description Figure 3. Block Diagram GENERAL MSBINV AEAT-86AD Multiturn Encoder Module is integrated with a controller. The controller provides data synchronization between Single Turn Absolute Encoder Module (i.e. AEAS7X00) and basic multiturn encoder module. Its combines the serial data from both modules into combined (nMT + nST ) bit resolution to application end. The MSB can be inverted (counting direction) by using MSBINV. The most significant bit (MSB) will always be sent first to DATA+. With integrated RS422 line driver and receiver, the differential data transmission is compatible with EIA standard RS-422. SRCLK+ and SRCLK SRCLK input pins are used to clocked out the serial outputs data through the DATA pins. Lapse time between words or subsequent data frame must be 40 µs or longer for proper data transmission. DATA+ and DATA DATA output pins provides positional information via synchronous serial interface, which consists of nMT bit of serial data from multiturn module and nST bit of serial data from single turn module.  STROBE STROBE output pin can be used to determine whether the data is locked or changing. It is high when date is locked, but low when data is changing. CONNECTION TO AEAS-7X00 Besides VDDA, VDD and GND of AEAS-7x00 need to be connected to the Multiturn Encoder Module, data and control i/o pins also need to be connected and soldered, i.e. NSDOUT, N2SCL, N2NSL and N2DIN NOTE: nMT = resolution of multiturn module nST = resolution of single turn module Device Selection Guide 1 Part Number Resolution Operating Temperature (°C) Output Code DC Supply Voltage (V) AEAT-86AD-LASC0 12 bit -40 to 125 Binary +5.0 to +5.5 AEAT-86AD-LASF0 14 bit -40 to 125 Binary +5.0 to +5.5 AEAT-86AD-LCSC0 12 bit -40 to 125 Gray +5.0 to +5.5 AEAT-86AD-LCSF0 14 bit -40 to 125 Gray +5.0 to +5.5 Notes: 1. For other options of Multiturn Encoder Module, please refer to factory. Absolute Maximum Ratings 1, 2 Parameter Symbol Limits Units DC Supply Voltage VCC -0.3 to + 6.0 V Input Voltage Vi -0.5 to +5.5 V Output Voltage Vo -0.5 to +VCC +0.5 V Relative Air Humidity (Non-Condensing) %RH 85 % Encoder Shaft Speed SRPM Max 12000 rpm Storage Temperature Tstg -40 to 125 °C Notes: 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3. This device meets the ESD ratings of the IEC61000-4-2 Level 1 (2KV). Recommended Operating Condition Parameter Symbol Values Units DC Supply Voltage VCC +5.0 / +5.5 V Ambient Temperature Tamb - 40 to +125 °C Hardware Clock fHCLK 16 MHz SSI Serial Clock fSRCLK 0.5 to 4 MHz Encoder Shaft Speed SRPM 10000 or below rpm Notes 1 2 Notes: 1. Internal hardware clock that is built into the module 2. As unique coded gear-wheels techniques are implemented to generate unambiguous positional information, the interactions between these high wear resistant gear wheels are subjected to mechanical wear and tear.  DC Characteristics DC Characteristics over Recommended Operating Range, typical at 25 °C Values Parameter Symbol Condition Min Output High Voltage IOH IOH = -8mA 2.4 Output Low Voltage IOL IOH = 8mA Input High Voltage VIH Input Low Voltage VIL VCC Supply Current ICC Typ. Max Units Notes V 1 V 1 V 2 0.8 V 2 110 mA Max Units Notes 10 ns 1 4 MHz 2 0.4 2 Notes: 1. Only applicable for STROBE output. 2. Only applicable for MSBINV input. 3. RS-422 differential line driver for DATA output. 4. RS-422 differential line receiver for SRCLK input. Timing Characteristics Timing Characteristics over Recommended Operating Range, typical at 25 °C Values Parameter Symbol Condition Min Typ. Input Transition Rise/Fall Time tR /tF 0.8V/2.0V SRCLK Frequency fSRCLK 0.5 SRCLK Low-time tLSRCLK 110 ns SRCLK High-time tHSRCLK 70 ns Data Latch time tLATCH Lapse time between words tLT 35 40 ms 3 ms 3, 4 Notes: 1. Only applicable for MSBINV input. 2. SRCLK low-time = 0.50/fSRCLK; high-time = 0.50/fSRCLK. 3. Refer to Figure 4 for timing description. 4. Valid data on falling edges of SRCLK with STROBE is high. SSI Frame End SSI Frame Start 1  nMT -1 nMT (nMT +1) 3 (nMT + nST) (nMT + nST)-1 tLT SRCLK + tLATCH DATA + MSB MT MSB-1 MT LSB+1 MT nMT bit Multiturn STROBE Figure 4. Timing Characteristics of STROBE, SRCLK and DATA  LSB MT MSB ST MSB-1 ST LSB+1 ST nST bit Single turn LSB ST Pin Description No. Pin Name Description Function Notes Pin out for test 1 A0N Analog Output A0 negative (- True dif ) 1 2 A0P Analog Output A0 positive (+True diff.) 1 3 A09N Analog output A09 negative (-True diff.) 1 4 A09P Analog output A09 positive (+True diff.) 1 5 STCAL Digital Input Do not use unnecessarily 1 Pin out between ST and MT S1 NC S2 KORR Digital-input Do not connect Do not connect S3 PROBE_ON Digital-Input Do not connect S4 PCL Digital Input Positive edge Do not connect S5 STCAL Digital Input Do not connect S6 MSBINV Digital-Input Do not connect S7 N2DIN Digital Input To be connect to AEAS-7000 DIN 2 S8 N2NSL Digital-Input To be connect to AEAS-7000 NSL 2 S9 N2SCL Digital-Input Positive Edge Shift-register Clock To be connect to AEAS-7000 SCL 2 S10 N2DOUT Digital Output Shift-Register Data Out To be connect to AEAS-7000 DOUT 2 S11 DO Digital Output Do not connect S12 DPROBE Digital Output Do not connect S13 VDD Supply Voltage +5V Supply Digital to AEAS-7000 2, 3 S14 GND Ground for supply voltage GND for 5V supply analog/digital 2, 3 S15 A09P Analog output Do not connect S16 GND Ground for supply voltage GND for 5V supply analog/digital S17 A0P Analog Output Do not connect S18 A09N Analog output Do not connect S19 VDDA Supply Voltage +5V Supply Analog to AEAS-7000 S20 A0N Analog Output Do not connect S21 LERR Digital Output Do not connect S22 LEDR Analog Output Do not connect Pin out between MT and External M1 GND Ground for supply voltage GND for 5V supply analog/digital M2 DATA - Digital Output SSI Data - M3 DATA + Digital Output SSI Data + M4 VCC Supply Voltage +5V Supply analog/digital M5 MSBINV Digital Input 0= Counting without inversion 1= Counting with inversion M6 STROBE Digital Output Data latching M7 SRCLK - Digital Input Shift-register Clock - M8 SRCLK + Digital Input Shift-register Clock + Notes: 1. Only use for test purposes. 2. Refer to AEAS-7000 datasheet for detailed pin description. 3. Power supply and ground from Multi-turn module to Single turn module.  2, 3 2, 3 Application Note The encoder is mechanically fixed by means of holes in adapters, which accommodate M3 threads. The encoder has 2 adapters for attaching in a 3 x 120° and 4 x 90° arrangement. For details, please refer to the mechanical drawings in Figure 5. The mechanical coupling of the encoder shaft is realised by means of gear opinion with a module of 0.3, 14 teeth. The zero positions of the coupling wheels are locked with a plastic plug for alignment to the single turn absolute encoder, with the coupling wheel being able to compensate for an angle error of about +/-7°. The electrical connection is realized by means of a 2x4 pin strip (1.27mm pitch), which is plugged into a corresponding female connector. The encoder is attached with a plastic plug that locks the absolute zero position. During the mating of the gear wheel and the encoder coupling wheel it may be necessary to align the teeth of the gears for proper matching. The plastic plug can be removed upon integration with the gear wheel. Plastic plug is removed upon integration with gearwheel. Zero position of coupling wheel Plastic plug Pinion, module 0.3, 14 teeth Figure 5. Mechanical coupling with Multiturn Encoder Module  Ordering Information A E A T - 8  A D - L S C - 1-bit resolution F - 1-bit resolution A - Binary output code C - Gray output code  - No cover, integrated with MUIC, Solid Shaft T - Extended temperature, -0 to +15 C Available options: AEAT-86AD-LASC0 AEAT-86AD-LASF0 AEAT-86AD-LCSC0 AEAT-86AD-LCSF0 For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Pte. in the United States and other countries. Data subject to change. Copyright © 2006 Avago Technologies Pte. All rights reserved.. Obsoletes 5989-3439EN. AV01-0254EN - July 14, 2006