AFBR-5103Z, AFBR-5103TZ, AFBR-5103AZ, AFBR-5103ATZ,
AFBR-5103PZ and AFBR-5103PEZ
FDDI, 100 Mbps ATM, and Fast Ethernet Transceivers
in Low Cost 1x9 Package Style
Data Sheet
Description
Features
The AFBR-5100Z family of transceivers from Avago Technologies provide the system designer with products to
implement a range of FDDI and ATM (Asynchronous
Transfer Mode) designs at the 100 Mbps/125 MBd rate.
Full Compliance with the Optical Performance Requirements of the FDDI PMD Standard
The transceivers are all supplied in the new industry standard 1x9 SIP package style with either a duplex SC or a
duplex ST* connector interface.
Full Compliance with the FDDI LCF-PMD Standard
Full Compliance with the Optical Performance Requirements of the ATM 100 Mbps Physical Layer
Full Compliance with the Optical Performance Requirements of 100 Base-FX Version of IEEE 802.3u
FDDI PMD, ATM and Fast Ethernet 2000 m Backbone
Links
Multisourced 1x9 Package Style with Choice of Duplex
SC or Duplex ST* Receptacle
The AFBR-5103Z/-5103TZare 1300 nm products with
optical performance compliant with the FDDI PMD
standard. The FDDI PMD standard is ISO/IEC 9314-3:
1990 and ANSI X3.166 - 1990.
Wave Solder and Aqueous Wash Process Compatible
These transceivers for 2000 meter multimode fiber
backbones are supplied in the small 1x9 duplex SC or
ST package style for those designers who want to avoid
the larger MIC/R (Media Interface Connector/Receptacle)
defined in the FDDI PMD standard.
Multimode Fiber Backbone Links
Avago Technologies also provides several other FDDI
products compliant with the PMD and SM-PMD standards. These products are available with MIC/R, ST© and
FC connector styles. They are available in the 1x13 and
2x11 transceiver and 16 pin transmitter/receiver package
styles for those designs that require these alternate configurations.
The AFBR-5103Z/-5103TZ is also useful for both ATM 100
Mbps interfaces and Fast Ethernet 100 Base-FX interfaces. The ATM Forum User-Network Interface (UNI) Standard, Version 3.0, defines the Physical Layer for 100 Mbps
Multimode Fiber Interface for ATM in Section 2.3 to be
the FDDI PMD Standard. Likewise, the Fast Ethernet Alliance defines the Physical Layer for 100 Base-FX for Fast
Ethernet to be the FDDI PMD Standard.
*ST is a registered trademark of AT&T Lightguide Cable Connectors.
RoHS Compliance
Applications
Multimode Fiber Wiring Closet to Desktop Links
Multimode Fiber Media Converter
Note: The “T” in the product numbers indicates a transceiver with a
duplex ST connector receptacle. Product numbers without a “T” indicate
transceivers with a duplex SC connector receptacle.
ATM applications for physical layers other than 100 Mbps
Multimode Fiber Interface are supported by Avago Technologies. Products are available for both the single mode
and the multimode fiber SONET-OC-3C (STS-3C) ATM interface and the 155 Mbps ATM 94 MBd multimode fiber
ATM interface as specified in the ATM Forum UNI.
Transmitter Sections
The transmitter sections of the AFBR-5103Z series utilize
1300 nm Surface Emitting InGaAsP LEDs. These LEDs
are packaged in the optical subassembly portion of the
transmitter section. They are driven by a custom silicon
IC which converts differential PECL logic signals, ECL referenced (shifted) to a +5 Volt supply, into an analog LED
drive current.
Receiver Sections
The receiver sections of the AFBR-5103Z series utilize
InGaAs PIN photodiodes coupled to a custom silicon
transimpedance preamplifier IC. These are packaged in
the optical subassembly portion of the receiver.
These PIN/preamplifier combinations are coupled to
a custom quantizer IC which provides the final pulse
shaping for the logic output and the Signal Detect function. The data output is differential. The signal detect
output is single-ended. Both data and signal detect
outputs are PECL compatible, ECL referenced (shifted) to
a +5 Volt power supply.
Package
The overall package concept for the Avago Technologies
transceivers consists of the following basic elements; two
optical subassemblies, an electrical subassembly and the
housing as illustrated in Figure 1 and Figure 1a.
ELECTRICAL SUBASSEMBLY
Figure 2b shows the outline drawing for options that
include mezzanine height with extended shield.
The package outline drawing and pin out are shown in
Figures 2, 2a and 3. The details of this package outline
and pin out are compliant with the multisource definition of the 1x9 SIP. The low profile of the Avago Technologies transceiver design complies with the maximum
height allowed for the duplex SC connector over the
entire length of the package.
The optical subassemblies utilize a high volume assembly process together with low cost lens elements which
result in a cost effective building block.
The electrical subassembly consists of a high volume
multilayer printed circuit board on which the IC chips
and various surface-mounted passive circuit elements
are attached.
The package includes internal shields for the electrical
and optical subassemblies to ensure low EMI emissions
and high immunity to external EMI fields.
The outer housing including the duplex SC connector receptacle or the duplex ST ports is molded of filled
non-conductive plastic to provide mechanical strength
and electrical isolation. The solder posts of the Avago
Technologies’ design are isolated from the circuit design
of the transceiver and do not require connection to a
ground plane on the circuit board.
The transceiver is attached to a printed circuit board with
the nine signal pins and the two solder posts which exit
the bottom of the housing. The two solder posts provide
the primary mechanical strength to withstand the loads
imposed on the transceiver by mating with duplex or
simplex SC or ST connectored fiber cables.
DUPLEX SC
RECEPTACLE
DIFFERENTIAL
DATA OUT
PIN PHOTODIODE
SINGLE-ENDED
SIGNAL
DETECT OUT
QUANTIZER IC
PREAMP IC
OPTICAL
SUBASSEMBLIES
DIFFERENTIAL
LED
DATA IN
DRIVER IC
TOP VIEW
Figure 1. SC Block Diagram
2
ELECTRICAL SUBASSEMBLY
DUPLEX ST
RECEPTACLE
DIFFERENTIAL
DATA OUT
PIN PHOTODIODE
SINGLE-ENDED
SIGNAL
DETECT OUT
QUANTIZER IC
PREAMP IC
OPTICAL
SUBASSEMBLIES
DIFFERENTIAL
LED
DATA IN
DRIVER IC
TOP VIEW
Figure 1a. ST Block Diagram.
39.12
MAX.
(1.540)
25.40
MAX.
(1.000)
A
12.70
(0.500)
6.35
(0.250)
AREA
RESERVED
FOR
PROCESS
PLUG
12.70
(0.500)
AFBR-5XXXZ
DATE CODE (YYWW)
SINGAPORE
5.93 ± 0.1
(0.233 ± 0.004)
+ 0.08
- 0.05
+ 0.003
)
(0.030
- 0.002
0.75
3.30 ± 0.38
(0.130 ± 0.015)
10.35
MAX.
(0.407)
2.92
(0.115)
∅
23.55
(0.927)
0.46
(9x)
(0.018)
NOTE 1
20.32
[8x(2.54/.100)]
(0.800)
4.14
(0.163)
16.70
(0.657)
0.87
(0.034)
Figure 2. Package Outline Drawing with Standard Height.
3
18.52
(0.729)
+ 0.25
- 0.05
+ 0.010
)
(0.050
- 0.002
NOTE 1
1.27
17.32
20.32
23.32
(0.682) (0.800) (0.918)
23.24
(0.915)
15.88
(0.625)
42 MAX.
(1.654)
5.99
(0.236)
24.8
(0.976)
12.7
(0.500)
25.4
MAX.
(1.000)
AFBR-5103TZ
DATE CODE (YYWW)
SINGAPORE
+ 0.08
0.5
- 0.05
(0.020) + 0.003
- 0.002
(
12.0
MAX.
(0.471)
2.6 ± 0.4
(0.102 ± 0.016)
∅ 0.46
(0.018)
NOTE 1
3.3 ± 0.38
(0.130) (± 0.015)
20.32 ± 0.38
(± 0.015)
∅ 2.6
+ 0.25
- 0.05
+ 0.010
0.050
- 0.002
1.27
(0.102)
(
20.32
17.4
[(8x (2.54/0.100)]
(0.800)
(0.685)
22.86
21.4
(0.900)
(0.843)
3.6
(0.142)
(
(
20.32
(0.800)
1.3
(0.051)
23.38
(0.921)
18.62
(0.733)
NOTE 1: PHOSPHOR BRONZE IS THE BASE MATERIAL FOR THE POSTS AND PINS. FOR LEAD-FREE SOLDERING,
THE SOLDER POSTS HAVE TIN COPPER OVER NICKEL PLATING AND THE ELECTRICAL PINS HAVE PURE TIN
OVER NICKEL PLATING.
DIMENSIONS IN MILLIMETERS (INCHES).
Figure 2a. ST Package Outline Drawing with Standard Height.
4
29.6 UNCOMPRESSED
(1.16)
39.6
(1.56) MAX.
4.7
(0.185)
AREA
RESERVED
FOR
PROCESS
PLUG
A
25.4
(1.00) MAX.
12.70
(0.50)
12.7
(0.50)
0.51
SLOT DEPTH (0.02)
(
+0.1
0.25 -0.05
+0.004
0.010 -0.002
)
9.8 MAX.
(0.386)
SLOT WIDTH
2.09 UNCOMPRESSED
(0.08)
10.2 MAX.
(0.40)
1.3
(0.05)
3.3 ± 0.38
(0.130 ± 0.015)
+0.25
0.46 -0.05
9X ∅
+0.010
0.018 -0.002
(
23.8
(0.937)
20.32
(0.800)
2X ∅
20.32
(0.80)
15.8 ± 0.15
(0.622 ± 0.006)
)
2X ∅
8X 2.54
(0.100)
20.32
(0.800)
1.3
(0.051)
DIMENSIONS ARE IN MILLIMETERS (INCHES).
ALL DIMENSIONS ARE ± 0.025 mm UNLESS OTHERWISE SPECIFIED.
Figure 2b. Package Outline Drawing – Mezzanine Height with Extended Shield.
1 = VEE
N/C
2 = RD
Rx
3 = RD
4 = SD
5 = VCC
6 = VCC
7 = TD
Tx
8 = TD
N/C
9 = VEE
TOP VIEW
Figure 3. Pin Out Diagram.
5
(
+0.25
1.27 -0.05
+0.010
0.050 -0.002
)
2.0 ± 0.1
(0.079 ± 0.004)
Application Information
The following information is provided to answer some
of the most common questions about the use of these
parts.
Transceiver Optical Power Budget versus Link Length
Optical Power Budget (OPB) is the available optical
power for a fiber optic link to accommodate fiber cable
losses plus losses due to in-line connectors, splices,
optical switches, and to provide margin for link aging
and unplanned losses due to cable plant reconfiguration
or repair.
Figure 4 illustrates the predicted OPB associated with the
transceiver series specified in this data sheet at the Beginning of Life (BOL). These curves represent the attenuation and chromatic plus modal dispersion losses associated with the 62.5/125 μm and 50/125 μm fiber cables
only. The area under the curves represents the remaining
OPB at any link length, which is available for overcoming
non-fiber cable related losses.
Avago technologies’ LED technology has produced 1300
nm LED devices with lower aging characteristics than
normally associated with these technologies in the industry. The industry convention is 1.5 dB aging for 1300
nm LEDs. The Avago Technologies 1300 nm LEDs will
experience less than 1 dB of aging over normal commercial equipment mission life periods. Contact your Avago
Technologies sales representative for additional details.
Figure 4 was generated with an Avago Technologies’
fiber optic link model containing the current industry
conventions for fiber cable specifications and the FDDI
PMD and LCF-PMD optical parameters. These parameters
are reflected in the guaranteed performance of the transceiver specifications in this data sheet. This same model
has been used extensively in the ANSI and IEEE committees, including the ANSI X3T9.5 committee, to establish
the optical performance requirements for various fiber
optic interface standards. The cable parameters used
come from the ISO/IEC JTC1/SC 25/WG3 Generic Cabling
for Customer Premises per DIS 11801 document and the
EIA/TIA-568-A Commercial Building Telecommunications
Cabling Standard per SP-2840.
6
OPTICAL POWER BUDGET (dB)
The Applications Engineering group in the Avago Technologies Optical Communication Division is available to
assist you with the technical understanding and design
trade-offs associated with these transceivers. You can
contact them through your Avago Technologies sales
representative.
14
12
AFBR-5103Z, 62.5/125 µm
10
8
6
4
AFBR-5103Z,
50/125 µm
2
0
0.15 0.5 1.0
1.5
2.0
2.5
3.0
3.5 4.0
FIBER OPTIC CABLE LENGTH (km)
Figure 4. Optical Power Budget at BOL versus Fiber Optic Cable
Length.
Transceiver Signaling Operating Rate Range and BER
Performance
For purposes of definition, the symbol (Baud) rate,
also called signaling rate, is the reciprocal of the shortest symbol time. Data rate (bits/sec) is the symbol rate
divided by the encoding factor used to encode the data
(symbols/bit).
When used in FDDI and ATM 100 Mbps applications the
performance of the 1300 nm transceivers is guaranteed
over the signaling rate of 10 MBd to 125 MBd to the
full conditions listed in individual product specification
tables.
The transceivers may be used for other applications at
signaling rates outside of the 10 MBd to 125 MBd range
with some penalty in the link optical power budget
primarily caused by a reduction of receiver sensitivity.
Figure 5 gives an indication of the typical performance of
these 1300 nm products at different rates.
These transceivers can also be used for applications
which require different Bit Error Rate (BER) performance.
Figure 6 illustrates the typical trade-off between link BER
and the receivers input optical power level.
Transceiver Jitter Performance
Recommended Handling Precautions
The Avago Technologies 1300 nm transceivers are designed to operate per the system jitter allocations stated
in Tables E1 of Annexes E of the FDDI PMD and LCF-PMD
standards.
Avago Technologies recommends that normal static precautions be taken in the handling and assembly of these
transceivers to prevent damage which may be induced
by electrostatic discharge (ESD). The AFBR-5100Z series
of transceivers meet MIL-STD-883C Method 3015.4 Class
2 products.
The Avago Technologies 1300 nm transmitters will tolerate the worst case input electrical jitter allowed in these
tables without violating the worst case output jitter requirements of Sections 8.1 Active Output Interface of the
FDDI PMD and LCF-PMD standards.
Care should be used to avoid shorting the receiver data
or signal detect outputs directly to ground without
proper current limiting impedance.
The Avago Technologies 1300 nm receivers will tolerate
the worst case input optical jitter allowed in Sections 8.2
Active Input Interface of the FDDI PMD and LCF-PMD
standards without violating the worst case output electrical jitter allowed in the Tables E1 of the Annexes E.
3.0
1 x 10-2
2.5
1 x 10-3
2.0
BIT ERROR RATE
TRANSCEIVER RELATIVE OPTICAL POWER BUDGET
AT CONSTANT BER (dB)
The jitter specifications stated in the following 1300 nm
transceiver specification tables are derived from the
values in Tables E1 of Annexes E. They represent the worst
case jitter contribution that the transceivers are allowed
to make to the overall system jitter without violating the
Annex E allocation example. In practice the typical contribution of the Avago Technologies transceivers is well
below these maximum allowed amounts.
1.5
1.0
0
25
50
75
100 125 150 175 200
SIGNAL RATE (MBd)
CONDITIONS:
1. PRBS 27-1
2. DATA SAMPLED AT CENTER OF DATA SYMBOL.
3. BER = 10-6
4. TA = 25˚ C
5. VCC = 5 Vdc
6. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
Figure 5. Transceiver Relative Optical Power Budget at Constant BER
vs. Signaling Rate.
7
1 x 10-5
CENTER OF SYMBOL
1 x 10-6
1 x 10-7
1 x 10-8
2.5 x 10-10
1 x 10-11
1 x 10-12
0.5
0
AFBR-5103Z/5103TZ SERIES
1 x 10-4
-6
-4
-2
0
2
4
RELATIVE INPUT OPTICAL POWER - dB
CONDITIONS:
1. 125 MBd
2. PRBS 27-1
3. CENTER OF SYMBOL SAMPLING.
4. TA = 25˚ C
5. VCC = 5 Vdc
6. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
Figure 6. Bit Error Rate vs. Relative Receiver Input Optical Power.
Solder and Wash Process Compatibility
Board Layout - Decoupling Circuit and Ground Planes
The transceivers are delivered with protective process
plugs inserted into the duplex SC or duplex ST connector
receptacle.
It is important to take care in the layout of your circuit
board to achieve optimum performance from these
transceivers. Figure 7 provides a good example of a
schematic for a power supply decoupling circuit that
works well with these parts. It is further recommended that a contiguous ground plane be provided in the
circuit board directly under the transceiver to provide
a low inductance ground for signal return current. This
recommendation is in keeping with good high frequency board layout practices.
This process plug protects the optical subassemblies
during wave solder and aqueous wash processing and
acts as a dust cover during shipping.
These transceivers are compatible with either industry
standard wave or hand solder processes.
;; ;;
;;;;
;;;;;
Shipping Container
The transceiver is packaged in a shipping container designed to protect it from mechanical and ESD damage
during shipment or storage.
Rx
Tx
NO INTERNAL CONNECTION
RD
2
RD
3
Rx
VCC
5
SD
4
Tx
VCC
6
C1
TD
7
For applications providing a choice of either a duplex SC
or a duplex ST connector interface, while utilizing the
same pinout on the printed circuit board, the ST port
needs to protrude from the chassis panel a minimum of
9.53 mm for sufficient clearance to install the ST connector.
Tx
VEE
9
TD
8
Please refer to Figure 8A for a mechanical layout detailing
the recommended location of the duplex SC and duplex
ST transceiver packages in relation to the chassis panel.
C2
VCC
L1
TERMINATION
AT PHY
DEVICE
INPUTS
VCC
R5
C3
R7
TERMINATION
AT TRANSCEIVER
INPUTS
R10
RD
RD
SD
VCC
TD
NOTES:
THE SPLIT-LOAD TERMINATIONS FOR ECL SIGNALS NEED TO BE LOCATED AT THE INPUT
OF DEVICES RECEIVING THOSE ECL SIGNALS. RECOMMEND 4-LAYER PRINTED CIRCUIT
BOARD WITH 50 OHM MICROSTRIP SIGNAL PATHS BE USED.
R1 = R4 = R6 = R8 = R10 = 130 OHMS.
R2 = R3 = R5 = R7 = R9 = 82 OHMS.
C1 = C2 = C3 = C5 = C6 = 0.1 µF.
C4 = 10 µF.
Figure 7. Recommended Decoupling and Termination Circuits
8
For both shielded design options, Figure 8b identifies
front panel aperture dimensions.
R4
C5
R9
R8
R3
R1
C4
VCC FILTER
AT VCC PINS
TRANSCEIVER
C6
R6
R2
L2
The Avago Technologies transceiver complies with the
circuit board “Common Transceiver Footprint” hole
pattern defined in the original multisource announcement which defined the 1x9 package style. This drawing
is reproduced in Figure 8 with the addition of ANSI
Y14.5M compliant dimensioning to be used as a guide in
the mechanical layout of your circuit board.
Board Layout - Mechanical
NO INTERNAL CONNECTION
AFBR-510XZ
TOP VIEW
Rx
VEE
1
Board Layout - Hole Pattern
TD
Regulatory Compliance
Electromagnetic Interference (EMI)
These transceiver products are intended to enable commercial system designers to develop equipment that
complies with the various international regulations governing certification of Information Technology Equipment. See the Regulatory Compliance Table for details.
Additional information is available from your Avago
Technologies sales representative.
Most equipment designs utilizing these high speed
transceivers from Avago Technologies will be required
to meet the requirements of FCC in the United States,
CENELEC EN55022 (CISPR 22) in Europe and VCCI in
Japan.
Electrostatic Discharge (ESD)
There are two design cases in which immunity to ESD
damage is important.
The first case is during handling of the transceiver prior
to mounting it on the circuit board. It is important to
use normal ESD handling precautions for ESD sensitive
devices. These precautions include using grounded wrist
straps, work benches, and floor mats in ESD controlled
areas.
These products are suitable for use in designs ranging
from a desktop computer with a single transceiver to a
concentrator or switch product with a large number of
transceivers.
In all well-designed chassis, two 0.5” holes for ST connectors to protrude through will provide 4.6 dB more shielding than one 1.2” duplex SC rectangular cutout. Thus, in
a well-designed chassis, the duplex ST 1x9 transceiver
emissions will be identical to the duplex SC 1x9 transceiver emissions.
The second case to consider is static discharges to the
exterior of the equipment chassis containing the transceiver parts. To the extent that the duplex SC connector
is exposed to the outside of the equipment chassis it may
be subject to whatever ESD system level test criteria that
the equipment is intended to meet.
(2X)∅ 1.9 ± 0.1
.075 ± .004
20.32
.800
¯0.000
(9X)∅ 0.8 ± 0.1
.032 ± .004
20.32
.800
¯0.000
(8X) 2.54
.100
TOP VIEW
Figure 8. Recommended Board Layout Hole Pattern
9
M A
M A
-A-
42.0
12.0
24.8
9.53
(NOTE 1)
0.51
12.09
25.4
39.12
11.1
6.79
0.75
25.4
NOTE 1: MINIMUM DISTANCE FROM FRONT
OF CONNECTOR TO THE PANEL FACE.
Figure 8a. Recommended Common Mechanical Layout for SC and ST 1x9 Connectored Transceivers.
10
A
0.8
2x (0.032)
0.8
2x (0.032)
(
9.4
(0.374)
6.35
(0.25)
MODULE
PROTRUSION
PCB BOTTOM VIEW
DIMENSIONS ARE IN MILLIMETERS (INCHES).
ALL DIMENSIONS ARE ± 0.025 mm UNLESS OTHERWISE SPECIFIED.
Figure 8b. Dimensions Shown for Mounting Module with Extended Shield to Panel.
11
27.4 ± 0.50
(1.08 ± 0.02)
+ 0.5
10.9 Ð 0.25
+ 0.02
0.43 Ð 0.01
)
Regulatory Compliance Table
Feature
Test Method
Performance
Electrostatic Discharge (ESD)
to the Electrical Pins
MIL-STD-883C
Method 3015.4
Meets Class 2 (2000 to 3999 Volts)
Withstand up to 2200V applied between electrical pins
Electrostatic Discharge (ESD)
to the Duplex SC Receptacle
Variation of IEC 801-2
Typically withstand at least 25 kV without damage when the
Duplex SC Connector Receptacle is contacted by a Human
Body Model probe.
Electromagnetic
Interference (EMC)
FCC CLass B
CENELEC CEN55022
Class B (CISPR 22B)
VCCI Class 2
Typically provide a 13 dB margin to the noted standards,
however, it should be noted that final margin depends on the
customer’s board and chasis design.
Immunity
Variation of IEC
61000-4-3
Typically show no measurable effect from a
10 V/m field swept from 10 to 450 MHz applied to the transceiver when mounted to a circuit card without a chassis enclosure.
Dl - TRANSMITTER OUTPUT OPTICAL
SPECTRAL WIDTH (FWHM) -nm
200
180
160
3.0
1.5
3.5
2.0
140 2.5
120
3.0
tr/f - TRANSMITTER
OUTPUT OPTICAL
RISE/FALL TIMES - ns
3.5
100
1200
1300
1320
1340
1360
1380
lC - TRANSMITTER OUTPUT OPTICAL
CENTER WAVELENGTH -nm
AFBR-5103Z FDDI TRANSMITTER TEST RESULTS
OF lC, Dl AND tr/f ARE CORRELATED AND
COMPLY WITH THE ALLOWED SPECTRAL WIDTH
AS A FUNCTION OF CENTER WAVELENGTH FOR
VARIOUS RISE AND FALL TIMES.
Figure 9. Transmitter Output Optical Spectral Width (FWHM) vs. Transmitter
Output Optical Center Wavelength and Rise/Fall Times.
12
Immunity
Transceiver Reliability and Performance Qualification Data
Equipment utilizing these transceivers will be subject to
radio-frequency electromagnetic fields in some environments. These transceivers have a high immunity to such
fields.
The 1x9 transceivers have passed Avago Technologies’
reliability and performance qualification testing and
are undergoing ongoing quality monitoring. Details are
available from your Avago Technologies’ sales representative.
For additional information regarding EMI, susceptibility,
ESD and conducted noise testing procedures and results
on the 1x9 Transceiver family, please refer to Applications
Note 1075, Testing and Measuring Electromagnetic Compatibility Performance of the AFBR-510X/-520X Fiber
Optic Transceivers.
4.40
1.975
1.25
4.850
10.0
RELATIVE AMPLITUDE
1.025
1.00
0.975
0.90
5.6
0.075
100% TIME
INTERVAL
40 ± 0.7
0.50
± 0.725
± 0.725
0% TIME
INTERVAL
0.10
0.025
0.0
-0.025
-0.05
0.075
5.6
10.0
1.525
0.525
4.850
80 ± 500 ppm
1.975
4.40
TIME - ns
THE AFBR-5103Z OUTPUT OPTICAL PULSE SHAPE SHALL FIT WITHIN THE BOUNDARIES
OF THE PULSE ENVELOPE FOR RISE AND FALL TIME MEASUREMENTS.
Figure 10. Output Optical Pulse Envelope.
13
1.525
0.525
Applications Support Materials
Accessory Duplex SC Connectored Cable Assemblies
Contact your local Avago Technologies Component Field
Sales Office for information on how to obtain PCB layouts,
test boards and demo boards for the 1x9 transceivers.
Avago Technologies recommends for optimal coupling
the use of flexible-body duplex SC connectored cable.
Accessory Duplex ST Connectored Cable Assemblies
Evaluation Kits
Avsgo Technologies has available three evaluation kits
for the 1x9 transceivers. The purpose of these kits is to
provide the necessary materials to evaluate the performance of the AFBR-510XZ family in a pre-existing 1x13 or
2x11 pinout system design configuration or when connectored to various test equipment.
RELATIVE INPUT OPTICAL POWER (dB)
1. HFBR-0319 Evaluation Test Fixture Board
This test fixture converts +5 V ECL 1x9 transceivers to –5 V
ECL BNC coax connections so that direct connections to
industry standard fiber optic test equipment can be accomplished.
5
AFBR-5103Z SERIES
4
3
2.5 x 10-10 BER
2
1.0 x 10-12 BER
1
0
-4
-3
-2
-1
0
1
2
3
4
EYE SAMPLING TIME POSITION (ns)
CONDITIONS:
1.TA = 25˚ C
2. VCC = 5 Vdc
3. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
4. INPUT OPTICAL POWER IS NORMALIZED TO
CENTER OF DATA SYMBOL.
5. NOTE 20 AND 21 APPLY.
Figure 11. Relative Input Optical Power vs. Eye Sampling Time Position.
14
Avago Technologies recommends the use of Duplex
Push-Pull connectored cable for the most repeatable
optical power coupling performance.
-31.0 dBm
OPTICAL POWER
MIN (PO + 4.0 dB OR -31.0 dBm)
PA(PO + 1.5 dB
< PA < -31.0 dBm)
PO = MAX (PS OR -45.0 dBm)
(PS = INPUT POWER FOR BER < 102)
INPUT OPTICAL POWER
(> 1.5 dB STEP INCREASE)
INPUT OPTICAL POWER
(> 4.0 dB STEP DECREASE)
-45.0 dBm
SIGNAL
DETECT
OUTPUT
ANS - MAX
AS - MAX
SIGNAL - DETECT
(ON)
SIGNAL - DETECT
(OFF)
TIME
AS - MAX - MAXIMUM ACQUISITION TIME (SIGNAL).
AS - MAX IS THE MAXIMUM SIGNAL - DETECT ASSERTION TIME FOR THE STATION.
AS - MAX SHALL NOT EXCEED 100.0 µs (130 µs FOR -40˚C to 0˚C).
THE DEFAULT VALUE OF AS - MAX IS 100.0 µs.
ANS - MAX - MAXIMUM ACQUISITION TIME (NO SIGNAL).
ANS - MAX IS THE MAXIMUM SIGNAL - DETECT DEASSERTION TIME FOR THE STATION.
ANS - MAX SHALL NOT EXCEED 350 µs (130 µs FOR -40˚C to 0˚C).
THE DEFAULT VALUE OF AS - MAX IS 350 µs.
Figure 12. Signal Detect Thresholds and Timing.
AFBR-5103Z Series
Absolute Maximum Ratings
Parameter
Symbol
Min.
Storage Temperature
TS
-40
Lead Soldering Temperature
Typ.
Max.
Unit
100
°C
TSOLD
260
°C
Lead Soldering Time
tSOLD
10
sec.
Supply Voltage
VCC
-0.5
7.0
V
-0.5
Data Input Voltage
VI
VCC
V
Differential Input Voltage
VD
1.4
V
Output Current
IO
50
mA
15
Reference
Note 1
AFBR-5103Z Series
Recommended Operating Conditions*
Parameter
Symbol
Min.
Ambient Operating Temperature
TA
Supply Voltage
Typ.
Max.
Unit
0
70
°C
VCC
4.75
5.25
V
Data Input Voltage - Low
VIL - VCC
-1.810
-1.475
V
Data Input Voltage - High
VIH - VCC
-1.165
-0.880
V
Data and Signal Detect Output Load
RL
50
ý
Reference
Note 2
*Applies to AFBR-5103Z & AFBR-5103TZ & AFBR-5103PZ/-5103PEZ Series except for AFBR-5103AZ/-5103ATZ. TA for
AFBR-5103AZ/-5103ATZ is -40°C and 85°C.
Transmitter Electrical Characteristics*
(TA = 0°C to 70°C, VCC = 4.75 V to 5.25 V)
Parameter
Symbol
Supply Current
Min.
Typ.
Max.
Unit
Reference
ICC
145
185
mA
Note 3
Power Dissipation
PDISS
0.76
0.97
W
Data Input Current - Low
IIL
Data Input Current - High
IIH
-350
0
μA
14
350
μA
*Applies to AFBR-5103Z & AFBR 5103TZ & AFBR-5103PZ/-5103PEZ Series except for AFBR-5103AZ/-5103ATZ. TA for
AFBR-5103AZ/-5103ATZ is -40°C and 85°C..
Receiver Electrical Characteristics
(TA = 0°C to 70°C, VCC = 4.75 V to 5.25 V)*
Parameter
Symbol
Supply Current
Min.
Typ.
Max.
Unit
Reference
ICC
82
145
mA
Note 4
Power Dissipation
PDISS
0.3
0.5
W
Note 5
Data Output Voltage - Low
VOL - VCC
-1.83
-1.55
V
Note 6
Data Output Voltage - High
VOH - VCC
-1.085
-0.88
V
Note 6
Data Output Rise Time
tr
0.35
2.2
ns
Note 7
Data Output Fall Time
tf
0.35
2.2
ns
Note 7
Signal Detect Output Voltage - Low
VOL - VCC
-1.83
-1.55
V
Note 6
Signal Detect Output Voltage - High
VOH - VCC
-1.085
-0.88
V
Note 6
Signal Detect Output Rise Time
tr
0.35
2.2
ns
Note 7
Signal Detect Output Fall Time
tf
0.35
2.2
ns
Note 7
*Applies to AFBR-5103Z & AFBR 5103TZ & AFBR-5103PZ and 5103PEZ Series except for AFBR-5103AZ/-5103ATZ. TA for AFBR-5103AZ/-5103ATZ is
-40°C and 85°C.
16
AFBR-5103Z/-5103TZ
Transmitter Optical Characteristics
(TA = 0°C to 70°C, VCC = 4.75 V to 5.25 V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Reference
Output Optical Power
62.5/125 μm, NA = 0.275 Fiber
BOL
EOL
PO
-19
-20
-16.8
-14
dBm avg.
Note 11
Output Optical Power
50/125 μm, NA = 0.20 Fiber
BOL
EOL
PO
-22.5
-23.5
-20.3
-14
dBm avg.
Note 11
10
-10
%
dB
Note 12
-45
dBm avg.
Note 13
1308
1380
nm
Note 14
Figure 9
137
200
nm
Note 14
Figure 9
Optical Extinction Ratio
Output Optical Power at Logic “0” State
PO (“0”)
Center Wavelength
lC
Spectral Width - FWHM
Ðl
Optical Rise Time
tr
0.6
1.0
3.0
ns
Note 14, 15
Figure 9, 10
Optical Fall Time
tf
0.6
2.1
3.0
ns
Note 14, 15
Figure 9, 10
Duty Cycle Distortion
Contributed by the
Transmitter
DCD
0.02
0.6
ns p-p
Note 16
Data Dependent Jitter
Contributed by the
Transmitter
DDJ
0.02
0.6
ns p-p
Note 17
17
1270
AFBR-5103Z/-5103TZ
Receiver Optical and Electrical Characteristics
(TA = 0°C to 70°C, VCC = 4.75 V to 5.25 V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Reference
Input Optical Power
Minimum at Window Edge
PIN Min. (W)
-33.5
-31
dBm avg.
Note 19
Figure 11
Input Optical Power
Minimum at Eye Center
PIN Min. (C)
-34.5
-31.8
dBm avg.
Note 20
Figure 11
Input Optical Power Maximum
PIN Max.
-14
dBm avg.
Note 19
Operating Wavelength
l
1270
Duty Cycle Distortion
Contributed by the Receiver
DCD
Data Dependent Jitter
Contributed by the Receiver
-11.8
1380
nm
0.02
0.4
ns p-p
Note 8
DDJ
0.35
1.0
ns p-p
Note 9
Random Jitter
Contributed by the Receiver
RJ
1.0
2.14
ns p-p
Note 10
Signal Detect - Asserted
PA
PD + 1.5 dB
-33
dBm avg.
Note 21, 22
Figure 12
Signal Detect - Deasserted
PD
-45
dBm avg.
Note 23, 24
Figure 12
Signal Detect - Hysteresis
PA - PD
1.5
2.4
dB
Figure 12
Signal Detect Assert Time
(off to on)
AS_Max
0
55
100
μs
Note 21,
Figure 12
SignalDetectAssert Time
(off to on) for -40°C to 0°C
AS_Max
0
55
130
μs
Note 21,
Figure 12
Signal Detect Deassert Time
(on to off )
ANS_Max
0
110
350
μs
Note 23, 24
Figure 12
Notes:
1. This is the maximum voltage that can be applied across the Differential Transmitter Data Inputs to prevent damage to the input ESD
protection circuit.
2. The outputs are terminated with 50 ý connected to VCC -2 V.
3. The power supply current needed to operate the transmitter is
provided to differential ECL circuitry. This circuitry maintains a nearly
constant current flow from the power supply. Constant current operation helps to prevent unwanted electrical noise from being generated
and conducted or emitted to neighboring circuitry.
4. This value is measured with the outputs terminated into 50 ý connected to VCC - 2 V and an Input Optical Power level of -14 dBm
average.
5. The power dissipation value is the power dissipated in the receiver
itself. Power dissipation is calculated as the sum of the products of
supply voltage and currents, minus the sum of the products of the
output voltages and currents.
6. These values are measured with respect to VCC with the output
terminated into 50 ý connected to VCC - 2 V.
7. The output rise and fall times are measured between 20% and 80%
levels with the output connected to VCC -2 V through 50 ý.
8. Duty Cycle Distortion contributed by the receiver is measured at
the 50% threshold using an IDLE Line State, 125 MBd (62.5 MHz
square-wave), input signal. The input optical power level is -20 dBm
average. See Application Information - Transceiver Jitter Section for
further information.
18
9. Data Dependent Jitter contributed by the receiver is specified with
the FDDI DDJ test pattern described in the FDDI PMD Annex A.5. The
input optical power level is -20 dBm average. See Application Information - Transceiver Jitter Section for further information.
10. Random Jitter contributed by the receiver is specified with an IDLE
Line State, 125 MBd (62.5 MHz square-wave), input signal. The input
optical power level is at maximum “PIN Min. (W)”. See Application
Information - Transceiver Jitter Section for further information.
11. These optical power values are measured with the following
conditions:
• The Beginning of Life (BOL) to the End of Life (EOL) optical power
degradation is typically 1.5 dB per the industry convention for
long wavelength LEDs. The actual degradation observed in Avago
Technologies’ 1300 nm LED products is < 1 dB, as specified in this
data sheet.
• Over the specified operating voltage and temperature ranges.
• With HALT Line State, (12.5 MHz square-wave), input signal.
• At the end of one meter of noted optical fiber with cladding modes
removed. The average power value can be converted to a peak power
value by adding 3 dB. Higher output optical power transmitters are
available on special request.
12. The Extinction Ratio is a measure of the modulation depth of the
optical signal. The data “0” output optical power is compared to the
data “1” peak output optical power and expressed as a percentage.
With the transmitter driven by a HALT Line State (12.5 MHz squarewave) signal, the average optical power is measured. The data“1”peak
power is then calculated by adding 3 dB to the measured average
optical power. The data “0” output optical power is found by measuring the optical power when the transmitter is driven by a logic “0”
input. The extinction ratio is the ratio of the optical power at the “0”
level compared to the optical power at the “1” level expressed as a
percentage or in decibels.
13. The transmitter provides compliance with the need for Transmit_Disable commands from the FDDI SMT layer by providing an Output
Optical Power level of < -45 dBm average in response to a logic “0”
input. This specification applies to either 62.5/125 μm or 50/125
μm fiber cables.
14. This parameter complies with the FDDI PMD requirements for the
tradeoffs between center wave-length, spectral width, and rise/fall
times shown in Figure 9.
15. This parameter complies with the optical pulse envelope from the
FDDI PMD shown in Figure 10. The optical rise and fall times are
measured from 10% to 90% when the transmitter is driven by the
FDDI HALT Line State (12.5 MHz square-wave) input signal.
16. Duty Cycle Distortion contributed by the transmitter is measured at
a 50% threshold using an IDLE Line State, 125 MBd (62.5 MHz squarewave), input signal. See Application Information - Transceiver Jitter
Performance Section of this data sheet for further details.
17. Data Dependent Jitter contributed by the transmitter is specified
with the FDDI test pattern described in FDDI PMD Annex A.5. See
Application Information - Transceiver Jitter Performance Section of
this data sheet for further details.
18. Random Jitter contributed by the transmitter is specified with an
IDLE Line State, 125 MBd (62.5 MHz square-wave), input signal. See
Application Information - Transceiver Jitter Performance Section of
this data sheet for further details.
19. This specification is intended to indicate the performance of the
receiver section of the transceiver when Input Optical Power signal
characteristics are present per the following definitions. The Input
Optical Power dynamic range from the minimum level (with a window time-width) to the maximum level is the range over which the
receiver is guaranteed to provide output data with a Bit Error Ratio
(BER) better than or equal to 2.5 x 10-10.
• At the Beginning of Life (BOL)
• Over the specified operating temperature and voltage ranges
• Input symbol pattern is the FDDI test pattern defined in FDDI PMD
Annex A.5 with 4B/5B NRZI encoded data that contains a duty cycle
base-line wander effect of 50 kHz. This sequence causes a near worst
case condition for inter-symbol interference.
19
• Receiver data window time-width is 2.13 ns or greater and centered
at mid-symbol. This worst case window time-width is the minimum
allowed eye-opening presented to the FDDI PHY PM._Data indication input (PHY input) per the example in FDDI PMD Annex E. This
minimum window time-width of 2.13 ns is based upon the worst case
FDDI PMD Active Input Interface optical conditions for peak-to-peak
DCD (1.0 ns), DDJ (1.2 ns) and RJ (0.76 ns) presented to the receiver.
To test a receiver with the worst case FDDI PMD Active Input jitter
condition requires exacting control over DCD, DDJ and RJ jitter components that is difficult to implement with production test equipment.
The receiver can be equivalently tested to the worst case FDDI PMD
input jitter conditions and meet the minimum output data window
time-width of 2.13 ns. This is accomplished by using a nearly ideal
input optical signal (no DCD, insignificant DDJ and RJ) and measuring
for a wider window time-width of 4.6 ns. This is possible due to the
cumulative effect of jitter components through their superposition
(DCD and DDJ are directly additive and RJ components are rms additive). Specifically, when a nearly ideal input optical test signal is
used and the maximum receiver peak-to-peak jitter contributions
of DCD (0.4 ns), DDJ (1.0 ns), and RJ (2.14 ns) exist, the minimum
window time-width becomes 8.0 ns -0.4 ns - 1.0 ns - 2.14 ns = 4.46
ns, or conservatively 4.6 ns. This wider window time-width of 4.6 ns
guarantees the FDDI PMD Annex E minimum window time-width
of 2.13 ns under worst case input jitter conditions to the Avago
Technologies receiver.
• Transmitter operating with an IDLE Line State pattern, 125 MBd (62.5
MHz square-wave), input signal to simulate any cross-talk present
between the transmitter and receiver sections of the transceiver.
20. All conditions of Note 19 apply except that the measurement is made
at the center of the symbol with no window time-width.
21. This value is measured during the transition from low to high levels
of input optical power.
22. The Signal Detect output shall be asserted within 100 μs (130 μs
for —40°C to 0°C) after a step increase of the Input Optical Power.
The step will be from a low Input Optical Power, —45 dBm, into the
range between greater than PA, and —14 dBm. The BER of the receiver
output will be 10-2 or better during the time, LS_Max (15 μs) after
Signal Detect has been asserted. See Figure 12 for more information.
23. This value is measured during the transition from high to low levels
of input optical power. The maximum value will occur when the input
optical power is either -45 dBm average or when the input optical
power yields a BER of 10-2 or better, whichever power is higher.
24. Signal detect output shall be de-asserted within 350 μs after a step
decrease in the Input Optical Power from a level which is the lower of;
-31 dBm or PD + 4 dB (PD is the power level at which signal detect was
deasserted), to a power level of -45 dBm or less. This step decrease
will have occurred in less than 8 ns. The receiver output will have
a BER of 10-2 or better for a period of 12 μs or until signal detect is
deasserted. The input data stream is the Quiet Line State. Also, signal
detect will be deasserted within a maximum of 350 μs after the BER
of the receiver output degrades above 10-2 for an input optical data
stream that decays with a negative ramp function instead of a step
function. See Figure 12 for more information.
Ordering Information:
1300nm LED, 125 MBd, FDDI, 100 Mbps ATM and Fast Eternet
temperature range 0°C to +70°C
AFBR-5103Z Duplex SC Connector 1X9, Standard Height
AFBR-5103TZ Duplex ST Connector 1X9
AFBR-5103PZ Duplex SC Connector 1x9, Mezzanine Height
AFBR-5103PEZ Duplex SC Connector 1x9, Mezzanine Height with Extended Shield
1300nm LED, 125 MBd, FDDI, 100 Mbps ATM and Fast Ethernet
temperature range –40°C to +85°C
AFBR-5103AZ Duplex SC Connector 1X9
AFBR-5103ATZ Duplex ST Connector 1X9
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. Obsoletes 5989-2292EN
AV02-3606EN - June 12, 2012
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