AFBR-5205Z
ATM Multimode Fiber Transceivers for SONET OC-3/SDH STM-1
in Low Cost 1x9 Package Style
Data Sheet
Description
Features
The AFBR-5200Z family of transceivers from Avago Technologies provide the system designer with products
to implement a range of solutions for multimode fiber
SONET OC-3 (SDH STM-1) physical layers for ATM and
other services.
Full compliance with ATM Forum UNI SONET OC-3
Multimode Fiber Physical Layer Specification
These transceivers are all supplied in the new industry
standard 1x9 SIP package style with either a duplex SC or
a duplex ST* connector interface.
Multisourced 1x9 package style with choice of duplex
SC or duplex ST* receptacle
Wave solder and aqueous wash process compatibility
RoHS Compliance
Applications
ATM 2000 m Backbone Links
Multimode fiber ATM backbone links
The AFBR-5205Z/-5205TZ are 1300 nm products with
optical performance compliant with the SONET STS-3c
(OC-3) Physical Layer Interface Specification. This physical
layer is defined in the ATM Forum User-Network Inter face
(UNI) Specification Version 3.0. This document references
the ANSI T1E1.2 specification for the details of the interface
for 2000 meter multimode fiber backbone links.
Multimode fiber ATM wiring closet to desktop links
Selected versions of these transceivers may be used to
implement the ATM Forum UNI Physical Layer Interface at
the 155 Mbps/194 MBd rate.
The ATM 100 Mbps/125 MBd Physical Layer interface is
best implemented with the AFBR-5100Z family of FDDI
Transceivers which are specified for use in this 4B/5B
encoded physical layer per the FDDI PMD standard.
Transmitter Sections
The transmitter sections of the AFBR-5205Z series utilize
1300 nm InGaAsP LEDs. These LEDs are packaged in the
optical subassembly portion of the transmitter section.
They are driven by a custom silicon IC which converts
differential PECL logic signals, ECL referenced (shifted) to a
+5 Volt supply, into an analog LED drive current.
*ST is a registered trademark of AT&T Lightguide Cable Connectors.
ATM 155 Mbps/194 MBd encoded links (available upon
special request)
Part Numbers
AFBR-5205Z, AFBR-5205AZ, AFBR-5205APZ,
AFBR-5205ATZ, AFBR-5205PZ, AFBR-5205TZ,
AFBR-5205PEZ 1300 nm 2 km
Receiver Sections
The receiver sections of the AFBR-5205Z series utilize
InGaAs PIN photodiodes coupled to a custom silicon transimpedance preamplifier IC. These are packaged in the
optical subassembly portion of the receiver.
The electrical subassembly consists of a high volume
multilayer printed circuit board on which the IC chips
and various surface-mounted passive circuit elements are
attached.
These PIN/preamplifier combinations are coupled to a
custom quantizer IC which provides the final pulse shaping
for the logic output and the Signal Detect function.
The data output is differential. The signal detect output
is single-ended. Both data and signal detect outputs are
PECL compatible, ECL referenced (shifted) to a +5 volt
power supply.
The package includes internal shields for the electrical
and optical subassemblies to insure low EMI emissions
and high immunity to external EMI fields.
Package
The overall package concept for the Avago transceivers
consists of three basic elements; the two optical subassemblies, an electrical subassembly, and the housing as
illustrated in the block diagrams in Figure 1 and Figure 1a.
The package outline drawing and pin out are shown in
Figures 2, 2a, and 3. The details of this package outline
and pin out are compliant with the multisource definition
of the 1x9 SIP. The low profile of the Avago transceiver
design complies with the maximum height allowed for
the duplex SC connector over the entire length of the
package.
Figures 2b and 2c show the outline drawings for options
that include mezzanine height and extended and flush
shields respectively.
The optical subassemblies utilize a high volume assembly
process together with low cost lens elements which result
in a cost effective building block.
ELECTRICAL SUBASSEMBLY
The transceiver is attached to a printed circuit board with
the nine signal pins and the two solder posts which exit
the bottom of the housing. The two solder posts provide
the primary mechanical strength to withstand the loads
imposed on the transceiver by mating with the duplex or
simplex SC or ST connectored fiber cables.
Note: The “T” in the product numbers indicates a transceiver with a
duplex ST connector receptacle. Product numbers without a “T” indicate
transceivers with a duplex SC connector receptacle.
Application Information
The Applications Engineering group in the Avago Optical
Communication Division is available to assist you with the
technical understanding and design trade-offs associated
with these transceivers. You can contact them through
your Avago sales representative.
DUPLEX SC
RECEPTACLE
DIFFERENTIAL
DATA OUT
PIN PHOTODIODE
SINGLE-ENDED
SIGNAL
DETECT OUT
The outer housing including the duplex SC connector or
the duplex ST ports is molded of filled non-conductive
plastic to provide mechanical strength and electrical
isolation. The solder posts of the Avago design are isolated
from the circuit design of the transceiver and do not
require connection to a ground plane on the circuit board.
QUANTIZER IC
PREAMP IC
OPTICAL
SUBASSEMBLIES
DIFFERENTIAL
LED
DATA IN
DRIVER IC
TOP VIEW
Figure 1. SC block diagram.
2
ELECTRICAL SUBASSEMBLY
DUPLEX ST
RECEPTACLE
DIFFERENTIAL
DATA OUT
PIN PHOTODIODE
SINGLE-ENDED
SIGNAL
DETECT OUT
QUANTIZER IC
PREAMP IC
OPTICAL
SUBASSEMBLIES
DIFFERENTIAL
LED
DATA IN
DRIVER IC
TOP VIEW
Figure 1a. ST block diagram.
39.12
(1.540) MAX.
25.40
(1.000) MAX.
A
AREA
RESERVED
FOR
PROCESS
PLUG
12.70
(0.500)
5.93 ± 0.1
(0.233 ± 0.004)
+ 0.08
0.75 - 0.05
(0.030 + 0.003 )
- 0.002
10.35 MAX.
(0.407)
2.92
(0.115)
18.52
(0.729)
4.14
(0.163)
φ 0.46
(0.018) (9x)
NOTE 1
20.32
(0.800) [8x(2.54/.100)]
16.70
(0.657)
0.87
(0.034)
Figure 2. SC package outline drawing with standard height.
3
6.35
(0.250)
AFBR-5xxxZ
DATE CODE (YYWW)
SINGAPORE
3.30 ± 0.38
(0.130 ± 0.015)
23.55
(0.927)
12.70
(0.500)
+ 0.25
1.27 - 0.05
(0.050 + 0.010 )
- 0.002
NOTE 1
17.32 20.32 23.32
(0.682) (0.800) (0.918)
23.24
(0.915)
15.88
(0.625)
Note 1: Posphor bronse is the base material for the
posts & pins.
For lead-free soldering, the solder posts have tin
copper over
nickel plating, and the electrical pins have pure tin
over nickel plating.
Dimensions are in millimeters (inches).
42 MAX.
(1.654)
5.99
(0.236)
24.8
(0.976)
12.7
(0.500)
25.4
(1.000) MAX.
AFBR-5103TZ
DATE CODE (YYWW)
SINGAPORE
+ 0.08
0.5
- 0.05
(0.020) + 0.003
( - 0.002 (
12.0
(0.471) MAX.
2.6 ± 0.4
(0.102 ± 0.016)
φ 0.46
(0.018)
NOTE 1
3.3 ± 0.38
(0.130) (± 0.015)
20.32 ± 0.38
(± 0.015)
φ 2.6
(0.102)
+ 0.25
1.27 - 0.05
+ 0.010
( 0.050 - 0.002 (
20.32 [(8x (2.54/0.100)]
17.4
(0.800)
(0.685)
22.86
21.4
(0.900)
(0.843)
3.6
(0.142)
20.32
(0.800)
1.3
(0.051)
23.38
(0.921)
Note 1: Posphor bronse is the base material for the posts & pins.
For lead-free soldering, the solder posts have tin copper over
nickel plating, and the electrical pins have pure tin over nickel plating.
Dimensions are in millimeters (inches).
Figure 2a. ST package outline drawing with standard height.
4
18.62
(0.733)
29.6 UNCOMPRESSED
(1.16)
12.70
(0.50)
39.6
MAX.
(1.56)
AREA
RESERVED
FOR
PROCESS
PLUG
A
25.4
MAX.
(1.00)
SLOT DEPTH
+0.1
-0.05
+0.004
(0.010
)
-0.002
0.25
9.8 MAX.
(0.386)
+0.25
-0.05
9X φ
+0.010
(0.018
)
-0.002
23.8
(0.937)
20.32
(0.800)
2X φ
SLOT WIDTH
2.09 UNCOMPRESSED
(0.08)
10.2 MAX.
(0.40)
1.3
(0.05)
20.32
(0.80)
8X 2.54
(0.100)
1.3
(0.051)
Dimensions are in millimeters (inches).
All dimensions are ±0.025mm unless otherwise specified.
Figure 2b. Package outline drawing with mezzanine height and extended shield.
5
12.7
(0.50)
0.51
(0.02)
3.3 ± 0.38
(0.130 ± 0.015)
0.46
4.7
(0.185)
15.8 ± 0.15
(0.622 ± 0.006)
2X φ
+0.25
-0.05
+0.010
(0.050
)
-0.002
20.32
(0.800)
1.27
2.0 ± 0.1
(0.079 ± 0.004)
39.6
(1.56) MAX.
12.7
(0.50)
4.7
(0.185)
1.01
(0.40)
AREA
RESERVED
FOR
PROCESS
PLUG
A
25.4
(1.00) MAX.
25.8 MAX.
(1.02)
+0.1
0.25 -0.05
+0.004
(0.010 -0.002 )
9.8 MAX.
(0.386)
AREA
RESERVED
FOR
PROCESS
PLUG
8x 2.54
(0.100)
1.3
2x φ (0.051)
Figure 2c. Package outline drawing with mezzanine height and flush shield.
N/C
Rx
Tx
N/C
TOP VIEW
6
15.8 ± 0.15
(0.622 ± 0.006)
2x φ
Figure 3. Pin out diagram.
2.0 ± 0.1
(0.079 ± 0.004)
22.0
(0.87)
20.32
(0.800)
1 = VEE
2 = RD
3 = RD
4 = SD
5 = VCC
6 = VCC
7 = TD
8 = TD
9 = VEE
SLOT WIDTH
14.4
(0.57)
+0.25
0.46 -0.05
9x φ
+0.010
(0.018 -0.002 )
20.32
(0.800)
2.2
(0.09)
SLOT DEPTH
12.7
(0.50)
10.2 MAX.
(0.40)
3.3 ± 0.38
(0.130 ± 0.015)
23.8
(0.937)
29.7
(1.17)
+0.25
1.27 -0.05
+0.010
(0.050 -0.002 )
20.32
(0.800)
Dimensions are in millimeters (inches).
All dimensions are ±0.025mm unless
otherwise specified.
The following information is provided to answer some of
the most common questions about the use of these parts.
Premises per DIS 11801 document and the EIA/TIA-568-A
Commercial Building Telecommunications Cabling
Standard per SP-2840.
Transceiver Optical Power Budget versus Link Length
Figure 4 illustrates the predicted OPB associated with the
three transceivers series specified in this data sheet at
the Beginning of Life (BOL). These curves represent the
attenuation and chromatic plus modal dispersion losses
associated with the 62.5/125 m and 50/125 m fiber
cables only. The area under the curves represents the
remaining OPB at any link length, which is available for
overcoming non-fiber cable losses.
Avago LED technology has produced 1300 nm LED
devices with lower aging characteristics than normally
associated with these technologies in the industry. The
industry convention is 1.5 dB aging for 1300 nm LEDs. The
1300 nm Avago LEDs are specified to experience less than
1 dB of aging over normal commercial equipment mission
life periods. Contact your Avago sales representative for
additional details.
Figure 4 was generated for the 1300 nm transceivers with
an Avago fiber optic link model containing the current
industry conventions for fiber cable specifications and the
draft ANSI T1E1.2. These optical parameters are reflected
in the guaranteed performance of the transceiver specifications in this data sheet. This same model has been used
extensively in the ANSI and IEEE committees, including
the ANSI T1E1.2 committee, to establish the optical performance requirements for various fiber optic interface
standards. The cable parameters used come from the
ISO/IEC JTC1/SC 25/WG3 Generic Cabling for Customer
7
Transceiver Signaling Operating Rate Range and
BER Performance
For purposes of definition, the symbol (Baud) rate, also
called signaling rate, is the reciprocal of the symbol time.
Data rate (bits/sec) is the symbol rate divided by the
encoding factor used to encode the data (symbols/bit).
When used in 155 Mbps SONET OC-3 applications the
performance of the 1300 nm transceivers, AFBR-5205Z
is guaranteed to the full conditions listed in individual
product specification tables.
12
AFBR-5205Z, 62.5/125 μm
10
OPTICAL POWER BUDGET (dB)
Optical Power Budget (OPB) is the available optical power
for a fiber optic link to accommodate fiber cable losses plus
losses due to in-line connectors, splices, optical switches,
and to provide margin for link aging and unplanned losses
due to cable plant reconfiguration or repair.
8
AFBR-5205Z,
50/125 μm
6
4
2
0
0.3 0.5
1.0
1.5
FIBER OPTIC CABLE LENGTH (km)
Figure 4. Optical power budget vs. fiber optic cable length.
2.0
2.5
The transceivers may be used for other applications
at signaling rates different than 155 Mbps with some
variation in the link optical power budget. Figure 5 gives
an indication of the typical performance of these products
at different rates.
These transceivers can also be used for applications which
require different Bit Error Rate (BER) performance. Figure
6 illustrates the typical trade-off between link BER and the
receivers input optical power level.
Transceiver Jitter Performance
The Avago 1300 nm transceivers are designed to operate
per the system jitter allocations stated in Table B1 of Annex
B of the draft ANSI T1E1.2 Revision 3 standard.
The Avago 1300 nm transmitters will tolerate the worst
case input electrical jitter allowed in Annex B without
violating the worst case output optical jitter requirements.
The jitter specifications stated in the following 1300 nm
transceiver specification tables are derived from the values
in Table B1 of Annex B. They represent the worst case jitter
contribution that the transceivers are allowed to make
to the overall system jitter without violating the Annex B
allocation example. In practice, the typical contribution
of the Avago transceivers is well below these maximum
allowed amounts.
Recommended Handling Precautions
Avago recommends that normal static precautions be
taken in the handling and assembly of these transceivers
to prevent damage which may be induced by electrostatic
discharge (ESD). The AFBR-5205Z series of transceivers
meet MIL-STD-883C Method 3015.4 Class 2 products.
Care should be used to avoid shorting the receiver data or
signal detect outputs directly to ground without proper
current limiting impedance.
The Avago 1300 nm receivers will tolerate the worst case
input optical jitter allowed in Annex B without violating
the worst case output electrical jitter allowed.
1 x 10-2
2.0
1 x 10-3
1.5
BIT ERROR RATE
TRANSCEIVER RELATIVE OPTICAL POWER BUDGET
AT CONSTANT BER (dB)
2.5
1.0
0.5
0
0.5
0
25
50
75
100
125
150
175 200
SIGNAL RATE (MBd)
CONDITIONS:
1. PRBS 27-1
2. DATA SAMPLED AT CENTER OF DATA SYMBOL.
3. BER = 10-6
4. TA = 25° C
5. VCC = 5 Vdc
6. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
Figure 5. Transceiver relative optical power budget at constant BER vs.
signaling rate.
8
1 x 10-4
AFBR-5205Z
1 x 10-5
1 x 10-6
CENTER OF SYMBOL
1 x 10-7
1 x 10-8
1 x 10-9
1 x 10-10
1 x 10-11
1 x 10-12
-6
-4
-2
0
2
RELATIVE INPUT OPTICAL POWER – dB
CONDITIONS:
1. 155 MBd
2. PRBS 27-1
3. CENTER OF SYMBOL SAMPLING.
4. TA = 25°C
5. VCC = 5 Vdc
6. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
Figure 6. Bit error rate vs. relative receiver input optical power.
4
Solder and Wash Process Compatibility
Shipping Container
The transceivers are delivered with protective process
plugs inserted into the duplex SC or duplex ST connector
receptacle. This process plug protects the optical subassemblies during wave solder and aqueous wash processing and acts as a dust cover during shipping.
The transceiver is packaged in a shipping container
designed to protect it from mechanical and ESD damage
during shipment or storage.
These transceivers are compatible with either industry
standard wave or hand solder processes.
Rx
Tx
NO INTERNAL CONNECTION
NO INTERNAL CONNECTION
AFBR-520xZ
TOP VIEW
Rx
VEE
1
RD
2
RD
3
Rx
VCC
5
SD
4
Tx
VCC
6
C1
TD
7
Tx
VEE
9
TD
8
C2
VCC
L1
TERMINATION
AT PHY
DEVICE
INPUTS
VCC
R5
R7
C6
R6
C3
R2
L2
R1
C4
TERMINATION
AT TRANSCEIVER
INPUTS
R9
R10
RD
RD
SD
VCC
R4
C5
VCC FILTER
AT VCC PINS
TRANSCEIVER
R8
R3
TD
TD
Notes:
The split-load terminations for ECL signals need to be located at the input of devices receiving those ECL signals.
Recommend 4-layer printed circuit board with 50 Ohm microstrip signal paths be used.
R1 = R4 = R6 = R8 = R10 = 130 Ohms.
R2 = R3 = R5 = R7 = R9 = 82 Ohms.
C1 = C2 = C3 = C5 = C6 = 0.1F.
C4 = 10 F.
L1 = L2 = 1 H coil or ferrite inductor.
Figure 7. Recommended decoupling and termination circuits.
9
Board Layout – Decoupling Circuit and Ground Planes
Board Layout – Hole Pattern
It is important to take care in the layout of your circuit
board to achieve optimum performance from these transceivers. Figure 7 provides a good example of a schematic
for a power supply decoupling circuit that works well with
these parts. It is further recommended that a contiguous
ground plane be provided in the circuit board directly
under the transceiver to provide a low inductance ground
for signal return current. This recommendation is in
keeping with good high frequency board layout practices.
The Avago transceiver complies with the circuit board
“Common Transceiver Footprint” hole pattern defined in
the original multisource announcement which defined the
1x9 package style. This drawing is reproduced in Figure 8
with the addition of ANSI Y14.5M compliant dimensioning to be used as a guide in the mechanical layout of your
circuit board.
(2X) φ
20.32
.800
1.9 ± 0.1
.075 ± .004
φ0.000
(9X) φ
20.32
.800
0.8 ± 0.1
.032 ± .004
φ0.000
(8X)
2.54
.100
TOP VIEW
Figure 8. Recommended board layout hole pattern.
10
M A
M A
–A–
Board Layout – Mechanical
Electrostatic Discharge (ESD)
For applications interested in providing a choice of either
a duplex SC or a duplex ST connector interface, while
utilizing the same pinout on the printed circuit board,
the ST port needs to protrude from the chassis panel a
minimum of 9.53 nm for sufficient clearance to install the
ST connector.
There are two design cases in which immunity to ESD
damage is important.
Please refer to Figure 8a for a mechanical layout detailing
the recommended location of the duplex SC and duplex
ST transceiver packages in relation to the chassis panel.
For both shielded design options, Figures 8b and 8c
identify front panel aperture dimensions.
Regulatory Compliance
These transceiver products are intended to enable
commercial system designers to develop equipment
that complies with the various international regulations governing certification of Information Technology Equipment. See the Regulatory Compliance Table
for details. Additional information is available from your
Avago sales representative.
The first case is during handling of the transceiver prior
to mounting it on the circuit board. It is important to
use normal ESD handling precautions for ESD sensitive
devices. These precautions include using grounded wrist
straps, work benches, and floor mats in ESD controlled
areas.
The second case to consider is static discharges to the
exterior of the equipment chassis containing the transceiver parts. To the extent that the duplex SC connector is
exposed to the outside of the equipment chassis it may be
subject to whatever ESD system level test criteria that the
equipment is intended to meet.
42.0
12.0
0.51
24.8
9.53
(NOTE 1)
12.09
25.4
11.1
0.75
39.12
6.79
25.4
Note 1: Minimum distance from front of
connector to the panel face.
Figure 8a. Recommended common mechanical layout for ST and ST 1x9 connectored transceivers.
11
A
0.8
2x (0.032)
0.8
2x (0.032)
+ 0.5
10.9 – 0.25
+ 0.02
(0.43 – 0.01 )
9.4
(0.374)
6.35
(0.25)
MODULE
PROTRUSION
27.4 ± 0.50
(1.08 ± 0.02)
Dimensions are in millimeters (inches).
All dimensions are ±0.025mm unless otherwise specified.
PCB BOTTOM VIEW
Figure 8b. Dimensions shown for mounting module with extended shield to panel.
Electromagnetic Interference (EMI)
Most equipment designs utilizing these high speed transceivers from Avago will be required to meet the requirements of FCC in the United States, CENELEC EN55022
(CISPR 22) in Europe and VCCI in Japan.
These products are suitable for use in designs ranging
from a desktop computer with a single transceiver to a
concentrator or switch product with large number of
transceivers.
12
In all well-designed chassis, the two 0.5" holes required
for ST connectors to protrude through, will provide
4.6 dB more shielding than one 1.2" duplex SC rectangular cutout. Thus, in a well-designed chassis, the
duplex ST 1x9 transceiver emissions will be identical to
the duplex SC 1x9 transceiver emissions.
5
3.0
180
4
RELATIVE INPUT OPTICAL POWER (dB)
Δλ – TRANSMITTER OUTPUT OPTICAL
SPECTRAL WIDTH (FWHM) –nm
200
1.0
160
1.5
140
2.0
tr/f – TRANSMITTER
OUTPUT OPTICAL
RISE/FALL TIMES – ns
2.5
120
3
AFBR-5205Z SERIES
2
1
3.0
100
1260
0
1280
1300
1320
1340
1360
λC – TRANSMITTER OUTPUT OPTICAL
CENTER WAVELENGTH –nm
AFBR-5205Z TRANSMITTER TEST RESULTS OF λC, Δλ AND tr/f
ARE CORRELATED AND COMPLY WITH THE ALLOWED SPECTRAL
WIDTH AS A FUNCTION OF CENTER WAVELENGTH FOR VARIOUS
RISE AND FALL TIMES.
Figure 9. Transmitter output optical spectral width (FWHM) vs. transmitter
output optical center wavelength and rise/fall times.
-3
-2
-1
0
1
2
EYE SAMPLING TIME POSITION (ns)
CONDITIONS:
1. TA = 25°C
2. VCC = 5 Vdc
3. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
4. INPUT OPTICAL POWER IS NORMALIZED TO
CENTER OF DATA SYMBOL.
5. NOTE 16 AND 17 APPLY.
Figure 10. Relative input optical power vs. eye sampling time position.
Regulatory Compliance Table
Feature
Test Method
Performance
Electrostatic Discharge
(ESD) to the Electrical Pins
MIL-STD-883C
Method 3015.4
Meets Class 2 (2000 to 3999 Volts)
Withstand up to 2200 V applied between electrical pins.
Electrostatic Discharge
(ESD) to the Duplex SC
Receptacle
Variation of
IEC 801-2
Typically withstand at least 25 kV without damage
when the Duplex SC Connector Receptacle
is contacted by a Human Body Model probe.
Electromagnetic
Interference (EMI)
FCC Class B
CENELEC EN55022
Class B (CISPR 22B)
VCCI Class 2
Typically provide 13dB margin to the noted standards
however, it should be noted that final margin depends
on the customer's board and chasis design.
Immunity
Variation of IEC 61000-4-3
Typically show no measurable effect from a
10 V/m field swept from 10 to 450 MHz applied
to the transceiver when mounted to a circuit card
without a chassis enclosure.
13
3
THICKER PANEL WILL RECESS MODULE.
THINNER PANEL WILL PROTRUDE MODULE.
A
1.98
(0.078)
1.27 OPTIONAL SEPTUM
(0.05)
30.2
(1.19)
0.36
(0.014)
10.82
(0.426)
13.82
(0.544)
BOTTOM SIDE OF PCB
12.0
(0.47)
Dimensions are in millimeters (inches).
All dimensions are ±0.025mm unless otherwise specified.
Figure 8c. Dimensions shown for mounting module flush to panel.
14
KEEP OUT ZONE
26.4
(1.04)
14.73
(0.58)
Immunity
Evaluation Kits
Equipment utilizing these transceivers will be subject to
radio-frequency electromagnetic fields in some environments. These transceivers have a high immunity to such
fields.
Avago has available three evaluation kits for the 1x9
transceivers. The purpose of these kits is to provide the
necessary materials to evaluate the performance of the
AFBR-520XZ family in a pre-existing 1x13 or 2x11 pinout
system design configuration or when connectored to
various test equipment.
For additional information regarding EMI, susceptibility,
ESD and conducted noise testing procedures and results
on the 1x9 transceiver family, please refer to Applications
Note 1075, Testing and Measuring Electromagnetic Compatibility Performance of the AFBR-510XZ/-520XZ Fiber
Optic Transceivers.
Transceiver Reliability and Performance
Qualification Data
1. HFBR-0319 – Evaluation Test Fixture Board:
This test fixture converts +5 V ECL 1x9 transceivers to
–5 V ECL BNC Coax Connections so that direct connections to industry standard fiber optic test equipment can be accomplished.
Accessory Duplex SC Connectored Cable Assemblies
The 1x9 transceivers have passed Avago reliability and
performance qualification testing and are undergoing
ongoing quality monitoring. Details are available from
your Avago sales representative.
Avago recommends for optimal coupling the use of
flexible-body duplex SC connectored cable.
These transceivers are manufactured at the Avago
Singapore location which is an ISO 9002 certified facility.
Avago recommends the use of Duplex Push-Pull ST
connectored cable for optimal repeatibility of the optical
power coupling.
Applications Support Materials
Contact your local Avago Component Field Sales Office
for information on how to obtain Test Boards and demo
boards for the 1x9 transceivers.
15
Accessory Duplex ST Connectored Cable Assemblies
AFBR-5205Z Series
Absolute Maximum Ratings
Parameter
Symbol
Min.
Typ.
Max.
Unit
Storage Temperature
TS
-40
100
°C
Lead Soldering Temperature
TSOLD
260
°C
Lead Soldering Time
tSOLD
10
sec.
Supply Voltage
VCC
-0.5
7.0
V
-0.5
Data Input Voltage
VI
VCC
V
Differential Input Voltage
VD
1.4
V
Output Current
IO
50
mA
Max.
Unit
Reference
Note 1
AFBR-5205Z Series
Recommended Operating Conditions
Parameter
Symbol
Min.
Typ.
Ambient Operating Temperature*
TA
0
70
°C
Supply Voltage
VCC
4.75
5.25
V
Data Input Voltage - Low
VIL - VCC
-1.810
-1.475
V
Data Input Voltage - High
VIH - VCC
-1.165
-0.880
V
Data and Signal Detect Output Load
RL
50
Reference
Note 2
*Applies to AFBR-5205Z Series except for AFBR-5205AZ and AFBR-5205ATZ. Ambient Operating Temp. for AFBR-5205AZ and AFBR-5205ATZ is
Min. -40°C and Max. 85°C.
AFBR-5205Z Series
Transmitter Electrical Characteristics
(TA = 0°C to 70°C, VCC = 4.75 V to 5.25 V)*
Parameter
Symbol
Supply Current
Min.
Typ.
Max.
Unit
Reference
ICC
145
185
mA
Note 3
Power Dissipation
PDISS
0.76
0.97
W
Data Input Current - Low
IIL
Data Input Current - High
IIH
-350
A
0
14
350
A
*Applies to AFBR-5205Z Series except for AFBR-5205AZ and AFBR-5205ATZ. TA for AFBR-5205AZ and AFBR-5205ATZ is -40°C and 85°C.
16
AFBR-5205Z Series
Receiver Electrical Characteristics
(TA = 0°C to 70°C, VCC = 4.75 V to 5.25 V)*
Parameter
Symbol
Min.
Typ.
Max.
Unit
Reference
Supply Current
ICC
82
145
mA
Note 4
Power Dissipation
PDISS
0.3
0.5
W
Note 5
Data Output Voltage - Low
VOL - VCC
-1.83
-1.55
V
Note 6
Data Output Voltage - High
VOH - VCC
-1.085
-0.88
V
Note 6
Data Output Rise Time
tr
0.35
2.2
ns
Note 7
Data Output Fall Time
tf
0.35
2.2
ns
Note 7
Signal Detect Output Voltage - Low
VOL - VCC
-1.83
-1.55
V
Note 6
Signal Detect Output Voltage - High
VOH - VCC
-1.085
-0.88
V
Note 6
Signal Detect Output Rise Time
tr
0.35
2.2
ns
Note 7
Signal Detect Output Fall Time
tf
0.35
2.2
ns
Note 7
*Applies to AFBR-5205Z Series except for AFBR-5205AZ and AFBR-5205ATZ. TA for AFBR-5205AZ and AFBR-5205ATZ is -40°C and 85°C.
AFBR-5205Z/-5205AZ/-5205ATZ/-5205PZ/-5205TZ/-5205PEZ
Transmitter Optical Characteristics
(TA = 0°C to 70°C, VCC = 4.75 V to 5.25 V)*
Parameter
Symbol
Min.
Typ.
Max.
Unit
Reference
Output Optical Power
62.5/125 μm, NA = 0.275 Fiber
BOL
EOL
PO
-19
-20
-14
dBm avg.
Note 8
Output Optical Power
50/125 m, NA = 0.20 Fiber
BOL
EOL
PO
-22.5
-23.5
-14
dBm avg.
Note 8
dB
Note 9
-45
dBm avg.
Note 10
1380
nm
Note 23
Figure 9
nm
nm RMS
Note 11, 23
Figure 9
Optical Extinction Ratio
10
Output Optical Power at
Logic "0" State
PO ("0")
Center Wavelength
C
Spectral Width – FWHM
– nm RMS
1270
1310
137
58
Optical Rise Time
tr
0.6
1.0
3.0
ns
Note 12, 23
Figure 9
Optical Fall Time
tf
0.6
2.1
3.0
ns
Note 12, 23
Figure 9
Systematic Jitter Contributed
by the Transmitter
SJ
0.04
1.2
ns p-p
Note 13
Random Jitter Contributed
by the Transmitter
RJ
0
0.52
ns p-p
Note 14
*Applies to 5205Z Series except for AFBR-5205AZ/-5205ATZ. TA for AFBR-5205AZ/-5205ATZ is -40°C and 85°C.
17
AFBR-5205Z/-5205AZ/-5205ATZ/-5205PZ/-5205TZ/-5205PEZ
Receiver Optical and Electrical Characteristics
(TA = 0°C to 70°C, VCC = 4.75 V to 5.25 V)*
Parameter
Symbol
Input Optical Power
Minimum at Window Edge
Input Optical Power
Minimum at Eye Center
Min.
Typ.
Max.
Unit
Reference
PIN Min. (W)
-30
dBm avg.
Note 15
Figure 10
PIN Min. (C)
-31
dBm avg.
Note 16
Figure 10
dBm avg.
Note 15
1380
nm
Input Optical Power Maximum
PIN Max.
-14
Operating Wavelength
1270
Systematic Jitter Contributed
by the Receiver
SJ
0.2
1.2
ns p-p
Note 17
Random Jitter Contributed
by the Receiver
RJ
1
1.91
ns p-p
Note 18
-31
Signal Detect - Asserted
PA
PD + 1.5 dB
dBm avg.
Note 19
Signal Detect - Deasserted
PD
-45
dBm avg.
Note 20
Signal Detect - Hysteresis
PA - PD
1.5
dB
Signal Detect Assert Time
(off to on)
Signal Detect Assert Time
(off to on) for -40°C to 0°C
Signal Detect Deassert Time
(on to off )
Max
0
55
100
s
Note 21
0
55
130
s
Note 21
0
110
350
s
Note 22
*Applies to 5205Z Series except for AFBR-5205AZ. TA for AFBR-5205AZ is -40°C to 85°C.
Notes:
1. This is the maximum voltage that can be applied across the Differential Transmitter Data Inputs to prevent damage to the input ESD protection
circuit.
2. The outputs are terminated with 50 connected to VCC -2 V.
3. The power supply current needed to operate the transmitter is provided to differential ECL circuitry. This circuitry maintains a nearly constant
current flow from the power supply. Constant current operation helps to prevent unwanted electrical noise from being generated and conducted
or emitted to neighboring circuitry.
4. This value is measured with the outputs terminated into 50 connected to VCC -2 V and an Input Optical Power level of -14 dBm average.
5. The power dissipation value is the power dissipated in the receiver itself. Power dissipation is calculated as the sum of the products of supply
voltage and currents, minus the sum of the products of the output voltages and currents.
6. This value is measured with respect to VCC with the output terminated into 50 connected to VCC -2 V.
7. The output rise and fall times are measured between 20% and 80% levels with the output connected to VCC -2 V through 50 .
8. These optical power values are measured with the following conditions:
The Beginning of Life (BOL) to the End of Life (EOL) optical power degradation is typically 1.5 dB per the industry convention for long wavelength
LEDs. The actual degradation observed in Avago’s 1300 nm LED products is
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