AFBR-5803AQZ and AFBR-5803ATQZ
FDDI, 100 Mb/s ATM, and Fast Ethernet Transceivers
in Low Cost 1 x 9 Package Style
Data Sheet
Description
Features
The AFBR-5800Z family of transceivers from Avago Technologies provide the system designer with products
to implement a range of Fast Ethernet, FDDI and ATM
(Asynchronous Transfer Mode) designs at the 100 Mb/s125 MBd rate.
• Full compliance with the optical performance requirements of the FDDI PMD standard
The transceivers are all supplied in the industry standard
1 x 9 SIP package style with either a duplex SC or a duplex
ST* connector interface.
• Full compliance with the optical performance requirements of 100 Base‑FX version of IEEE 802.3u
FDDI PMD, ATM and Fast Ethernet 2 km Backbone Links
The AFBR-5803AQZ/ATQZ are 1300 nm products with
optical performance compliant with the FDDI PMD
standard. The FDDI PMD standard is ISO/IEC 9314‑3: 1990
and ANSI X3.166 - 1990.
These transceivers for 2 km multimode fiber backbones
are supplied in the small 1 x 9 duplex SC or ST package
style.
The AFBR-5803AQZ/ATQZ is useful for both ATM 100
Mb/s interfaces and Fast Ethernet 100 Base-FX interfaces. The ATM Forum User-Network Interface (UNI)
Standard, Version 3.0, defines the Physical Layer for 100
Mb/s Multimode Fiber Interface for ATM in Section 2.3 to
be the FDDI PMD Standard. Likewise, the Fast Ethernet
Alliance defines the Physical Layer for 100 Base-FX for
Fast Ethernet to be the FDDI PMD Standard.
ATM applications for physical layers other than 100 Mb/s
Multimode Fiber Interface are supported by Avago Technologies. Products are available for both the single mode
and the multimode fiber SONET OC-3c (STS‑3c) ATM interfaces and the 155 Mb/s-194 MBd multimode fiber ATM
interface as specified in the ATM Forum UNI.
Contact your Avago Technologies sales representative
for information on these alternative Fast Ethernet, FDDI
and ATM products.
• Full compliance with the FDDI LCF-PMD standard
• Full compliance with the optical performance requirements of the ATM 100 Mb/s physical layer
• Multisourced 1 x 9 package style with choice of
duplex SC or duplex ST* receptacle
• Wave solder and aqueous wash process compatible
• Single +3.3 V or +5 V power supply
• RoHS Compliance
• Industrial range -40 to 85C
Applications
• Multimode fiber backbone links
• Multimode fiber wiring closet to desktop links
• Very low cost multimode fiber links from wiring
closet to desktop
• Multimode fiber media converters
*ST is a registered trademark of AT&T Lightguide Cable Connectors.
Transmitter Sections
The transmitter section of the AFBR-5803AQZ and AFBR5805Z series utilize 1300 nm Surface Emitting InGaAsP
LEDs. These LEDs are packaged in the optical subassembly portion of the transmitter section. They are driven
by a custom silicon IC which converts differential PECL
logic signals, ECL referenced (shifted) to a +3.3 V or +5 V
supply, into an analog LED drive current.
Receiver Sections
The receiver sections of the AFBR-5803AQZ and AFBR5805Z series utilize InGaAs PIN photodiodes coupled to
a custom silicon transimpedance preamplifier IC. These
are packaged in the optical subassembly portion of the
receiver.
These PIN/preamplifier combinations are coupled to
a custom quantizer IC which provides the final pulse
shaping for the logic output and the Signal Detect
function. The data output is differential. The signal detect
output is single-ended. Both data and signal detect
outputs are PECL compatible, ECL referenced (shifted) to
a +3.3 V or +5 V power supply.
Package
The overall package concept for the Avago Technologies
transceivers consists of the following basic elements; two
optical subassemblies, an electrical subassembly and the
housing as illustrated in Figure 1 and Figure 1a.
of the 1 x 9 SIP. The low profile of the Avago Technologies
transceiver design complies with the maximum height
allowed for the duplex SC connector over the entire
length of the package.
The optical subassemblies utilize a high volume assembly
process together with low cost lens elements which result
in a cost effective building block.
The electrical subassembly consists of a high volume
multilayer printed circuit board on which the IC chips
and various surface-mounted passive circuit elements
are attached.
The package includes internal shields for the electrical
and optical subassemblies to ensure low EMI emissions
and high immunity to external EMI fields.
The outer housing including the duplex SC connector
receptacle or the duplex ST ports is molded of filled
nonconductive plastic to provide mechanical strength
and electrical isolation. The solder posts of the Avago
Technologies design are isolated from the circuit design
of the transceiver and do not require connection to a
ground plane on the circuit board.
The transceiver is attached to a printed circuit board with
the nine signal pins and the two solder posts which exit
the bottom of the housing. The two solder posts provide
the primary mechanical strength to withstand the loads
imposed on the transceiver by mating with duplex or
simplex SC or ST connectored fiber cables.
The package outline drawings and pin out are shown in
Figures 2, 2a and 3. The details of this package outline
and pin out are compliant with the multisource definition
ELECTRICAL SUBASSEMBLY
DUPLEX SC
RECEPTACLE
DIFFERENTIAL
DATA OUT
PIN PHOTODIODE
SINGLE-ENDED
SIGNAL
DETECT OUT
QUANTIZER IC
PREAMP IC
OPTICAL
SUBASSEMBLIES
DIFFERENTIAL
LED
DATA IN
DRIVER IC
TOP VIEW
Figure 1. SC Connector Block Diagram.
ELECTRICAL SUBASSEMBLY
DUPLEX ST
RECEPTACLE
DIFFERENTIAL
DATA OUT
PIN PHOTODIODE
SINGLE-ENDED
SIGNAL
DETECT OUT
QUANTIZER IC
PREAMP IC
OPTICAL
SUBASSEMBLIES
DIFFERENTIAL
LED
DATA IN
DRIVER IC
TOP VIEW
Figure 1a. ST Connector Block Diagram.
Case Temperature
Measurement Point
39.12
MAX.
(1.540)
12.70
(0.500)
AREA
RESERVED
FOR
PROCESS
PLUG
25.40
MAX.
(1.000)
AFBR-5803AQZ
DATE CODE (YYWW)
SINGAPORE
+ 0.08
0.75
– 0.05
2.6 ± 0.4
+ 0.003 )
(0.030
(0.102 ± 0.016)
– 0.002
6.35
(0.250)
12.70
(0.500)
AVAGO
5.93 ± 0.1
(0.233 ± 0.004)
3.30 ± 0.38
(0.130 ± 0.015)
10.35 MAX.
(0.407)
2.92
(0.115)
Ø
23.55
(0.927)
0.46
(9x)
(0.018)
NOTE 1
20.32 [8x(2.54/.100)]
(0.800)
4.14
(0.163
17.32 20.32
(0.682 (0.800)
23.24
(0.915)
15.88
(0.625)
Phosphor bronze is the base material for the posts & pins. For lead-free soldering, the solder posts
have Tin Copper over Nickel plating, and the electrical pins have pure Tin over Nickel plating.
DIMENSIONS ARE IN MILLIMETERS (INCHES).
Figure 2. SC Connector Package Outline Drawing with standard height.
1.27 + 0.25
– 0.05
+
(0.050 0.010 )
– 0.002
NOTE 1
16.70
(0.657)
0.87
(0.034)
Note 1:
18.52
(0.729)
23.32
(0.918)
42 MAX.
(1.654)
5.99
(0.236)
24.8
(0.976)
12.7
(0.500)
25.4
MAX.
(1.000)
Case Temperature
Measurement Point
12.0
MAX.
(0.471)
2.6 ±0.4
(0.102 ± 0.016)
20.32
Ø 0.46
(0.018)
NOTE 1
20.32
[(8x (2.54/0.100)]
(0.800)
22.86
(0.900)
21.4
(0.843)
3.6
(0.142)
Note 1:
+ 0.25
- 0.05
(0.050) + 0.010
( - 0.002 )
1.27
17.4
(0.685)
20.32
(0.800)
23.38
(0.921)
18.62
(0.733)
Phosphor bronze is the base material for the posts & pins. For lead-free soldering, the solder posts
have Tin Copper over Nickel plating, and the electrical pins have pure Tin over Nickel plating.
DIMENSIONS IN MILLIMETERS (INCHES).
Figure 2a. ST Connector Package Outline Drawing with standard height.
1 = VEE
N/C
2 = RD
Rx
3 = RD
4 = SD
5 = VCC
6 = VCC
7 = TD
8 = TD
9 = VEE
Tx
N/C
TOP VIEW
Figure 3. Pin Out Diagram.
3.3 ± 0.38
(0.130 ± 0.015)
± 0.38
(± 0.015)
Ø 2.6
(0.102)
1.3
(0.051)
+ 0.08
0.5
- 0.05
(0.020) + 0.003
( - 0.002
(
AFBR-5803AQZ
DATE CODE (YYWW)
SINGAPORE
Application Information
The Applications Engineering group in the Avago Technologies Fiber Optics Communication Division is available
to assist you with the technical understanding and design
trade-offs associated with these transceivers. You can
contact them through your Avago Technologies sales
representative.
The following information is provided to answer some
of the most common questions about the use of these
parts.
Transceiver Optical Power Budget versus Link Length
Optical Power Budget (OPB) is the available optical
power for a fiber optic link to accommodate fiber cable
losses plus losses due to in-line connectors, splices,
optical switches, and to provide margin for link aging
and unplanned losses due to cable plant reconfiguration
or repair.
Figure 4 illustrates the predicted OPB associated with
the transceiver series specified in this data sheet at the
Beginning of Life (BOL). These curves represent the attenuation and chromatic plus modal dispersion losses associated with the 62.5/125 µm and 50/125 µm fiber cables
only. The area under the curves represents the remaining
OPB at any link length, which is available for overcoming
non-fiber cable related losses.
Avago Technologies LED technology has produced
1300 nm LED devices with lower aging characteristics
than normally associated with these technologies in the
industry. The industry convention is 1.5 dB aging for 1300
nm LEDs. The Avago Technologies 1300 nm LEDs will
experience less than 1 dB of aging over normal commer
cial equipment mission life periods. Contact your Avago
Technologies sales representative for additional details.
12
AFBR-5803, 62.5/125 µm
OPTICAL POWER BUDGET (dB)
10
8
AFBR-5803
50/125 µm
6
4
2
0
0.3 0.5
1.0
1.5
2.0
2.5
FIBER OPTIC CABLE LENGTH (km)
Figure 4. Optical Power Budget at BOL versus Fiber
Optic Cable Length.
Transceiver Signaling Operating Rate Range and BER
Performance
For purposes of definition, the symbol (Baud) rate, also
called signaling rate, is the reciprocal of the shortest
symbol time. Data rate (bits/sec) is the symbol rate
divided by the encoding factor used to encode the data
(symbols/bit).
When used in Fast Ethernet, FDDI and ATM 100 Mb/s applications the performance of the 1300 nm transceivers
is guaranteed over the signaling rate of 10 MBd to 125
MBd to the full conditions listed in individual product
specification tables.
The transceivers may be used for other applications at
signaling rates outside of the 10 MBd to 125 MBd range
with some penalty in the link optical power budget
primarily caused by a reduction of receiver sensitivity.
Figure 5 gives an indication of the typical performance of
these 1300 nm products at different rates.
These transceivers can also be used for applications which
require different Bit Error Rate (BER) performance. Figure 6
illustrates the typical trade-off between link BER and the
receivers input optical power level.
TRANSCEIVER RELATIVE OPTICAL POWER BUDGET
AT CONSTANT BER (dB)
Figure 4 was generated with a Avago Technologies fiber
optic link model containing the current industry conventions for fiber cable specifications and the FDDI PMD
and LCF-PMD optical parameters. These parameters are
reflected in the guaranteed performance of the transceiver specifications in this data sheet. This same model
has been used extensively in the ANSI and IEEE committees, including the ANSI X3T9.5 committee, to establish
the optical performance requirements for various fiber
optic interface standards. The cable parameters used
come from the ISO/IEC JTC1/SC 25/WG3 Generic Cabling
for Customer Premises per DIS 11801 document and the
EIA/TIA-568-A Commercial Building Telecommunications
Cabling Standard per SP-2840.
2.5
2.0
CONDITIONS:
1. PRBS 27-1
2. DATA SAMPLED
AT CENTER OF
DATA SYMBOL.
3. BER = 10-6
4. TA = +25˚ C
5. VCC = 3.3 V to 5 V dc
6. INPUT OPTICAL
RISE/FALL TIMES
= 1.0/2.1 ns.
1.5
1.0
0.5
0
0.5
0
25
50
75
100
125
150
175 200
SIGNAL RATE (MBd)
Figure 5. Transceiver Relative Optical Power Budget at Constant BER vs.
Signaling Rate.
Transceiver Jitter Performance
-2
1 x 10
The Avago Technologies 1300 nm transceivers are
designed to operate per the system jitter allocations
stated in Tables E1 of Annexes E of the FDDI PMD and
LCF-PMD standards.
-3
BIT ERROR RATE
1 x 10
-4
1 x 10
AFBR-5803 SERIES
-5
1 x 10
-6
1 x 10
-7
1 x 10-8
1 x 10-9
1 x 10
1 x 10 -10
1 x 10 -11
1 x 10 -12
The Avago Technologies 1300 nm transmitters will
tolerate the worst case input electrical jitter allowed in
these tables without violating the worst case output jitter
requirements of Sections 8.1 Active Output Interface of
the FDDI PMD and LCF-PMD standards.
CENTER OF SYMBOL
-6
-4
-2
0
2
RELATIVE INPUT OPTICAL POWER - dB
4
The Avago Technologies 1300 nm receivers will tolerate
the worst case input optical jitter allowed in Sections 8.2
Active Input Interface of the FDDI PMD and LCF-PMD
standards without violating the worst case output electrical jitter allowed in the Tables E1 of the Annexes E.
CONDITIONS:
1. 155 MBd
2. PRBS 2 7-1
3. CENTER OF SYMBOL SAMPLING
4. TA = +25˚C
5. VCC = 3.3 V to 5 V dc
6. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
The jitter specifications stated in the following 1300 nm
transceiver specification tables are derived from the
values in Tables E1 of Annexes E. They represent the worst
case jitter contribution that the transceivers are allowed
to make to the overall system jitter without violating the
Annex E allocation example. In practice the typical contribution of the Avago Technologies transceivers is well
below these maximum allowed amounts.
Figure 6. Bit Error Rate vs. Relative Receiver Input Optical Power.
Rx
Tx
NO INTERNAL CONNECTION
NO INTERNAL CONNECTION
AFBR-5803
TOP VIEW
Rx
VEE
1
RD
2
RD
3
SD
4
Rx
VCC
5
Tx
VCC
6
C1
VCC
R5
C6
R6
R2
L2
R1
C3
C4
VCC FILTER
AT VCC PINS
TRANSCEIVER
R9
R7
R8
RD
SD
VCC
VCC
R3
C5
R4
TERMINATION
AT TRANSCEIVER
INPUTS
R10
RD
Tx
VEE
9
TD
8
C2
L1
TERMINATION
AT PHY
DEVICE
INPUTS
TD
7
TD
TD
NOTES:
THE SPLIT-LOAD TERMINATIONS FOR ECL SIGNALS NEED TO BE LOCATED AT THE INPUT
OF DEVICES RECEIVING THOSE ECL SIGNALS. RECOMMEND 4-LAYER PRINTED CIRCUIT
BOARD WITH 50 OHM MICROSTRIP SIGNAL PATHS BE USED.
R1 = R4 = R6 = R8 = R10 = 130 OHMS FOR +5.0 V OPERATION, 82 OHMS FOR +3.3 V OPERATION.
R2 = R3 = R5 = R7 = R9 = 82 OHMS FOR +5.0 V OPERATION, 130 OHMS FOR +3.3 V OPERATION.
C1 = C2 = C3 = C5 = C6 = 0.1 µF.
C4 = 10 µF.
L1 = L2 = 1 µH COIL OR FERRITE INDUCTOR.
Figure 7. Recommended Decoupling and Termination Circuits
Recommended Handling Precautions
Avago Technologies recommends that normal static precautions be taken in the handling and assembly of these
transceivers to prevent damage which may be induced
by electrostatic discharge (ESD). The AFBR-5800 series of
transceivers meet MIL-STD-883C Method 3015.4 Class 2
products.
Care should be used to avoid shorting the receiver data
or signal detect outputs directly to ground without
proper current limiting impedance.
Solder and Wash Process Compatibility
The transceivers are delivered with protective process
plugs inserted into the duplex SC or duplex ST connector
receptacle. This process plug protects the optical subassemblies during wave solder and aqueous wash processing and acts as a dust cover during shipping.
These transceivers are compatible with either industry
standard wave or hand solder processes.
Shipping Container
The transceiver is packaged in a shipping container
designed to protect it from mechanical and ESD damage
during shipment or storage.
Board Layout - Decoupling Circuit and Ground Planes
20.32
(0.800)
The Avago Technologies transceiver complies with the
circuit board “Common Transceiver Footprint” hole
pattern defined in the original multisource announce
ment which defined the 1 x 9 package style. This drawing
is reproduced in Figure 8 with the addition of ANSI
Y14.5M compliant dimensioning to be used as a guide in
the mechanical layout of your circuit board.
Board Layout - Mechanical
For applications providing a choice of either a duplex SC
or a duplex ST connector interface, while utilizing the
same pinout on the printed circuit board, the ST port
needs to protrude from the chassis panel a minimum
of 9.53 mm for sufficient clearance to install the ST
connector.
Please refer to Figure 8a for a mechanical layout detailing
the recommended location of the duplex SC and duplex
ST transceiver packages in relation to the chassis panel.
9 x Ø 0.8 ± 0.1
(0.032 ± 0.004)
TOP VIEW
DIMENSIONS ARE IN MILLIMETERS (INCHES)
Figure 8. Recommended Board Layout Hole Pattern
Board Layout - Hole Pattern
2 x Ø 1.9 ± 0.1
(0.075 ± 0.004)
20.32
(0.800)
2.54
(0.100)
It is important to take care in the layout of your circuit
board to achieve optimum performance from these
transceivers. Figure 7 provides a good example of a
schematic for a power supply decoupling circuit that
works well with these parts. It is further recommended
that a contiguous ground plane be provided in the
circuit board directly under the transceiver to provide
a low inductance ground for signal return current. This
recommendation is in keeping with good high frequency
board layout practices.
42.0
12.0
24.8
9.53
(NOTE 1)
0.51
12.09
25.4
11.1
0.75
39.12
6.79
25.4
NOTE 1: MINIMUM DISTANCE FROM FRONT
OF CONNECTOR TO THE PANEL FACE.
Figure 8a. Recommended Common Mechanical Layout for SC and ST 1 x 9 Connectored Transceivers.
Regulatory Compliance
These transceiver products are intended to enable
commercial system designers to develop equipment
that complies with the various international regulations governing certification of Information Technology
Equipment. See the Regulatory Compliance Table for
details. Additional information is available from your
Avago Technologies sales representative.
Electrostatic Discharge (ESD)
There are two design cases in which immunity to ESD
damage is important.
The first case is during handling of the transceiver prior
to mounting it on the circuit board. It is important to
use normal ESD handling precautions for ESD sensitive
devices. These precautions include using grounded wrist
straps, work benches, and floor mats in ESD controlled
areas.
The second case to consider is static discharges to the
exterior of the equipment chassis containing the transceiver parts. To the extent that the duplex SC connector
is exposed to the outside of the equipment chassis it may
be subject to whatever ESD system level test criteria that
the equipment is intended to meet.
Regulatory Compliance Table
Feature
Test Method
Performance
Electrostatic Discharge (ESD)
to the Electrical Pins
MIL-STD-883
Method 3015.4
Meets Class 1 ( 1.5 dB STEP INCREASE)
PO = MAX (PS OR -45.0 dBm)
(PS = INPUT POWER FOR BER < 102)
INPUT OPTICAL POWER
(> 4.0 dB STEP DECREASE)
SIGNAL
DETECT
OUTPUT
-45.0 dBm
SIGNAL – DETECT
(ON)
AS – MAX
ANS – MAX
SIGNAL – DETECT
(OFF)
TIME
AS – MAX — MAXIMUM ACQUISITION TIME (SIGNAL).
AS – MAX IS THE MAXIMUM SIGNAL – DETECT ASSERTION TIME FOR THE STATION.
AS – MAX SHALL NOT EXCEED 100.0 µs. THE DEFAULT VALUE OF AS – MAX IS 100.0 µs.
ANS – MAX — MAXIMUM ACQUISITION TIME (NO SIGNAL).
ANS – MAX IS THE MAXIMUM SIGNAL – DETECT DEASSERTION TIME FOR THE STATION.
ANS – MAX SHALL NOT EXCEED 350 µs. THE DEFAULT VALUE OF AS – MAX IS 350 µs.
Figure 12. Signal Detect Thresholds and Timing.
11
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause catastrophic damage to the device. Limits apply to each parameter in isolation, all other parameters having values within the recommended operating conditions. It should not be assumed that
limiting values of more than one parameter can be applied to the product at the same time. Exposure to the absolute maximum
ratings for extended periods can adversely affect device reliability.
Parameter
Symbol
Min.
Storage Temperature
TS
-40
Lead Soldering Temperature
TSOLD
Lead Soldering Time
tSOLD
Supply Voltage
VCC
-0.5
Data Input Voltage
VI
-0.5
Differential Input Voltage
VD
Output Current
IO
Typ.
Max.
Unit
+100
°C
Reference
+260
°C
10
sec.
7.0
V
VCC
V
1.4
V
50
mA
Max.
Unit
Reference
Note A
Note 1
Recommended Operating Conditions
Parameter
Symbol
Min.
Ambient Operating Temperature
AFBR-5803AQZ/5803ATQZ
Typ.
TA
-40
+85
°C
Supply Voltage
VCCVCC
3.1354.75
3.55.25
VV
Data Input Voltage - Low
VIL - VCC
-1.810
-1.475
V
Data Input Voltage - High
VIH - VCC
-1.165
-0.880
V
Data and Signal Detect Output Load
RL
W
50
Note 2
Notes:
A. Ambient Operating Temperature corresponds to transceiver case temperature of -40 °C mininum to +100 °C maximum with necessary airflow
applied. Recommended case temperature measurement point can be found in Figure 2.
Transmitter Electrical Characteristics
(AFBR-5803AQZ/AFBR-5803ATQZ: TA = -40°C to +85°C, VCC = 3.135 V to 3.5 V or 4.75 V to 5.25 V)
Parameter
Symbol
Typ.
Max.
Unit
Reference
Supply Current
ICC
133
175
mA
Note 3
at VCC = 3.3 V
PDISS
0.45
0.6
W
at VCC = 5.0 V
PDISS
0.76
0.97
W
Power
Dissipation
Data Input Current - Low
IIL
Data Input Current - High
IIH
12
Min.
-350
-2
18
µA
350
µA
Receiver Electrical Characteristics
(AFBR-5803AQZ/AFBR-5803ATQZ: TA = -40°C to +85°C, VCC = 3.135 V to 3.5 V or 4.75 V to 5.25 V)
Parameter
Symbol
Typ.
Max.
Unit
Reference
Supply Current
ICC
87
120
mA
Note 4
at VCC = 3.3 V
PDISS
0.15
0.25
W
Note 5
at VCC = 5.0 V
PDISS
0.3
Power
Dissipation
Min.
0.5
W
Note 5
Data Output Voltage - Low
VOL - VCC
-1.83
-1.55
V
Note 6
Data Output Voltage - High
VOH - VCC
-1.085
-0.88
V
Note 6
Data Output Rise Time
tr
0.35
2.2
ns
Note 7
Data Output Fall Time
tf
0.35
2.2
ns
Note 7
Signal Detect Output Voltage - Low
VOL - VCC
-1.83
-1.55
V
Note 6
Signal Detect Output Voltage - High
VOH - VCC
-1.085
-0.88
V
Note 6
Signal Detect Output Rise Time
tr
0.35
2.2
ns
Note 7
Signal Detect Output Fall Time
tf
0.35
2.2
ns
Note 7
Transmitter Optical Characteristics
(AFBR-5803AQZ/AFBR-5803ATQZ: TA = -40°C to +85°C, VCC = 3.135 V to 3.5 V or 4.75 V to 5.25 V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Reference
Output Optical Power
62.5/125 µm, NA = 0.275 Fiber
BOL
EOL
PO
-19
-20
-14
dBm avg.
Note 11
Output Optical Power
50/125 µm, NA = 0.20 Fiber
BOL
EOL
PO
-22.5
-23.5
-14
dBm avg.
Note 11
10
-10
%
dB
Note 12
-45
dBm avg.
Note 13
1380
nm
Note 14
nm
Note 14
Figure 9
Optical Extinction Ratio
Output Optical Power at Logic “0” State
PO (“0”)
Center Wavelength
lC
Spectral Width
- FWHMSpectral Width
- nm RMS
Dl
Optical Rise Time
tr
0.6
1.9
3.0
ns
Note 14, 15
Figure 9, 10
Optical Fall Time
tf
0.6
1.6
3.0
ns
Note 14, 15
Figure 9, 10
Duty Cycle Distortion Contributed
by the Transmitter
DCD
0.6
ns p-p
Note 16
Data Dependent Jitter Contributed
by the Transmitter
DDJ
0.6
ns p-p
Note 17
Random Jitter Contributed
by the Transmitter
RJ
0.69
ns p-p
Note 18
13
1270
1308
147
63
Receiver Optical and Electrical Characteristics
(AFBR-5803AQZ/AFBR-5803ATQZ: TA = -40°C to +85°C, VCC = 3.135 V to 3.5 V or 4.75 V to 5.25 V)
Parameter
Symbol
Input Optical Power Minimum at Window Edge
Min.
Typ.
Max.
Unit
Reference
PIN Min. (W)
-33.9
-31
dBm avg.
Note 19
Figure 11
Input Optical Power Minimum at Eye Center
PIN Min. (C)
-35.2
-31.8
dBm avg.
Note 20
Figure 11
Input Optical Power Maximum
PIN Max.
-14
dBm avg.
Note 19
Operating Wavelength
l
1270
Duty Cycle Distortion Contributed
by the Receiver
1380
nm
DCD
0.4
ns p-p
Note 8
Data Dependent Jitter Contributed
by the Receiver
DDJ
1.0
ns p-p
Note 9
Random Jitter Contributed by the Receiver
RJ
2.14
ns p-p
Note 10
Signal Detect - Asserted
PA
PD + 1.5 dB
-33
dBm avg.
Note 21, 22
Figure 12
Signal Detect - Deasserted
PD
-45
dBm avg.
Note 23, 24
Figure 12
Signal Detect - Hysteresis
PA - PD
1.5
dB
Figure 12
Signal Detect Assert Time (off to on)
AS_Max
0
2
100
µs
Note 21, 22
Figure 12
Signal Detect Deassert Time (on to off )
ANS_Max
0
8
350
µs
Note 23, 24
Figure 12
Notes:
1. This is the maximum voltage that can be applied across the Differential Transmitter Data Inputs to prevent damage to the input ESD protection circuit.
2. The outputs are terminated with 50 W connected to VCC -2 V.
3. The power supply current needed to operate the transmitter is provided to differential ECL circuitry. This circuitry maintains a nearly constant
current flow from the power supply. Constant current operation helps to prevent unwanted electrical noise from being generated and conducted or emitted to neighboring circuitry.
4. This value is measured with the outputs terminated into 50 W connected to VCC - 2 V and an Input Optical Power level of
-14 dBm average.
5. The power dissipation value is the power dissipated in the receiver itself. Power dissipation is calculated as the sum of the products of supply
voltage and currents, minus the sum of the products of the output voltages and currents.
6. This value is measured with respect to VCC with the output terminated into 50 W connected to VCC - 2 V.
7. The output rise and fall times are measured between 20% and 80% levels with the output connected to VCC -2 V through 50 W.
8. Duty Cycle Distortion contributed by the receiver is measured at the 50% threshold using an IDLE Line State, 125 MBd
(62.5 MHz square-wave), input signal. The input optical power level is -20 dBm average. See Application Information - Transceiver Jitter Section for further information.
9. Data Dependent Jitter contributed by the receiver is specified with the FDDI DDJ test pattern described in the FDDI PMD Annex A.5. The
input optical power level is -20 dBm average. See Application Information - Transceiver Jitter Section for further information.
10. Random Jitter contributed by the receiver is specified with an IDLE Line State,
125 MBd (62.5 MHz square-wave), input signal. The input optical power level is at maximum “PIN Min. (W)”. See Application Information - Transceiver Jitter Section for further information.
11. These optical power values are measured with the following conditions:
• The Beginning of Life (BOL) to the End of Life (EOL) optical power degradation is typically 1.5 dB per the industry convention for long
wavelength LEDs. The actual degradation observed in Avago Technologies’ 1300 nm LED products is
< 1 dB, as specified in this data sheet.
• Over the specified operating voltage and temperature ranges.
• With HALT Line State, (12.5 MHz square-wave), input signal.
• At the end of one meter of noted optical fiber with cladding modes removed.
The average power value can be converted to a peak power value by adding 3 dB. Higher output optical power transmitters are available on
special request.
14
12. The Extinction Ratio is a measure of the modulation depth of the optical signal. The data “0” output optical power is compared to the data “1”
peak output optical power and expressed as a percentage. With the transmitter driven by a HALT Line State (12.5 MHz square-wave) signal,
the average optical power is measured. The data “1” peak power is then calculated by adding 3 dB to the measured average optical power.
The data “0” output optical power is found by measuring the optical power when the transmitter is driven by a logic “0” input. The extinction
ratio is the ratio of the optical power at the “0” level compared to the optical power at the “1” level expressed as a percentage or in decibels.
13. The transmitter provides compliance with the need for Transmit_Disable commands from the FDDI SMT layer by providing an Output Optical
Power level of
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