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AFBR-5972BZ

AFBR-5972BZ

  • 厂商:

    AVAGO(博通)

  • 封装:

    -

  • 描述:

    TXRX FAST ETHERNET POF

  • 数据手册
  • 价格&库存
AFBR-5972BZ 数据手册
AFBR-5972EZ, AFBR-5972BZ Compact 650nm Transceiver with Compact Versatile Link Connector for Fast Ethernet over POF Data Sheet Description Features The AFBR-5972xZ transceivers provide system designers with the ability to implement Fast Ethernet (100 Mbps) over standard bandwidth 0.5±0.05 NA POF. The new compact Versatile-Link duplex connector is compatible with existing simplex Versatile-Link connectors and features a very compact design with a form factor similar to the UTP connector. To enable easy visual differentiation the AFBR-5972EZ uses standard black port color while the AFBR-5972BZ has a blue colored port. The AFBR-5972xZ transceivers are lead free and compliant with RoHS.  Fast Ethernet communications over POF Transmitter Applications The transmitter contains a 650nm LED with a driver IC. The LED driver operates at 3.3V. It receives an LVDS electrical input, and converts it into a modulated current driving the LED. IC and LED are packaged in an optical subassembly, part of the transmitter section. The optical subassembly couples the output optical power efficiently into POF fiber.  Factory automation at Fast Ethernet speeds Receiver The receiver utilizes an amplifier/quantizer IC with an integrated double photodiode. The IC is packaged in an optical sub-assembly, part of the receiver section. This optical subassembly couples the optical power efficiently from POF fiber to the receiving photodiode. The integrated IC operates at 3.3V and converts the photocurrent into LVDS electrical output. Package The transceiver package consists of three basic elements; two opto-electical subassemblies and the housing as illustrated in the block diagrams in figure 1. The package outline drawing and pin-outs are shown in figures 2 and 7.  Link lengths up to 50m POF (NA0.5) or 70m POF (NA0.3)  Compact foot print  3.3V operation  Data rates up to 250 MBd  LVDS Input and Output data connections  Analog RSSI (receiver signal strength) monitor output  Temperature range -40°C to 85°C  Fast Ethernet networking over POF Differential Data Output Integrated Receiver Integrated Photodiode RSSI Output Differential Data Input Figure 1. Block diagram LED Driver LED The opto-electrical subassemblies utilize a high volume assembly process together with low cost lens elements which result in a cost effective building block. It consists of the active III-V devices, IC chips and various surface mounted passive components. 7.77 7.77 4.44 3.17 1.9 0.63 0 0.64 1.91 3.18 4.45 There are eight signal pins, four EMI shield solder posts and two mounting posts, which exit the bottom of the housing. The solder posts are isolated from the internal circuit of the transceiver and are to be connected to chassis ground. The mounting posts are to provide mechanical strength to hold the transceiver to the application board. S T ANDOF F AR E A (2 x 0.65 x 1.03) 8.89 4 2 6.35 ‡ 0. 9 +0 .1 8.66 ND LD G S H IE +0 .1 ( 2 x) ‡ 1 .6 8 6 (8 x) 1 3 5 7 3) R ecommended P C B Thickness 1.57 ± 0.05 0 ‡ 3.2 1) Dimens ion: mm 2) G eneral tolerance: ±0.05 3.18 3.05 NOT E S : 4) P in des cription 0 +0.1 MOUNT P OS T UNP LAT E D (2x) 3.73 (2x) S T ANDOF F AR E A (4 x 1.9 x 1) F UNC T D+ T DT xV cc G ND R xVcc RSSI R D+ R D- 5.76 6.7 7.78 2.45 0 2.45 7.78 6.7 5.76 T op View P IN 1 2 3 4 5 6 7 8 ź F ront ź Figure 2. PCB footprint and pinout diagram Pin Description Pin 1 TData+: Transmitter data in positive. This input is an LVDS compatible differential line. Pin 2 TData-: Transmitter data in negative. This input is an LVDS compatible differential line. Pin 3 TxVCC: Transmitter power supply pin. Provide +3.3 V DC via a transmitter power supply filter circuit. Locate the power supply filter circuit as close as possible to the TxVcc pin. Pin 4 GND: Common ground pin. Directly connect this pin to the signal ground plane of the host board. Pin 5 RxVCC: Receiver power supply pin. Provide +3.3 V DC via a receiver power supply filter circuit. Locate the power supply filter circuit as close as possible to the RxVcc pin. Pin 6 RSSI: Receiver signal strength pin, delivers a DC output current proportional to the average incoming light power. Pin 7 RData+: Receiver data out positive. This data line is an LVDS compatible differential output line which should be properly terminated. In absence of an optical input signal, this line is squelched. Pin 8 RData-: Receiver data out negative. This data line is an LVDS compatible differential output line which should be properly terminated. In absence of an optical input signal, this line (same as RData+) is squelched. Shield Shield This is to be connected to the equipment chassis ground. 2 Application Circuit The recommended application circuitry is shown in figure 3 1μH 100nF L1 VCC 3.3V C9 1μH Control Circuitry 10μF 100nF C5 C6 L2 AFBR-5972xZ TxVcc K LED-Driver R1 50 100nF C3 100 RD+ 100nF C2 100 LVDS 50 10μF 100nF C7 C8 LVDS 100nF C4 50 RD- A Tx TDRxVcc RD+ RD- Amplifier and quantizer K Rx LL TD- TD+ LL 100nF C1 50 TD+ A RSSI RRSSI 2k C10 100nF GND Chasis GND Figure 3. Recommended application circuitry Board Layout – Decoupling Circuit and Ground Planes It is important to take care of the layout of the application circuitry to achieve optimum performance of the transceiver. A power supply decoupling circuit is recommended to filter out noise, to assure optimal product performance. It is further recommended that a contiguous signal ground plane be provided in the circuit board directly under the transceiver to provide a low inductance ground for signal return current. It is also recommended that the shield posts be connected to the chassis ground to provide optimum EMI, ESD and EMS performance. This recommendation is in keeping with good high frequency board layout practices. Regulatory Compliance Table Feature Test Method Performance Electrostatic discharge (ESD) to the electrical Pins ESD22-A114 Withstands up to 2000V HBM applied between the electrical pins. Immunity Variation of IEC 61000-4-3 Typically shows no measurable effect from a 15V/m field swept from 8MHz to 1GHz applied to the transceiver when mounted on a circuit board without chassis enclosure. Eye Safety EN 60825-1:52007 Laser class 1 product (LED radiation only). TÜV certificate: R 50217706. CAUTION – Use of controls or adjustments of performance or procedures other than those specified herein may result in hazardous radiation exposure Component recognition Underwriter Laboratories UL File #: E173874 3 Transceiver diagnostics timing characteristics Parameter Symbol Time to initialize Assert time De-assert time Min Max Unit Notes t_init 5 ms Note 1, figure 4 t_ass 100 μs Notes 2, 4 t_deass 100 μs Notes 3, 4 Notes: 1. Time from power on to when the modulated optical output rises above 90% of nominal. 2. Time from valid optical signal to assertion. 3. Time from loss of optical signal to de-assertion. 4. There is an internal SD (signal detect) signal which is directly related to assert (PA) and de-assert (PD) levels as specified in table “Receiver Optical Characteristics”. There is no direct access to the SD signal, however the Rx data outputs will squelch and the RSSI will switch off, once the optical input power falls below PD. Furthermore, the Rx data and RSSI outputs will be activated, once the optical input power exceeds PA OCCURANCE OF LOSS OPTICAL SIGNAL TX, RX Vcc > 2.97V SD (internal) t_deass t_ass TRANSMITTER SIGNAL t_init t_init: t_ass & t_deass Figure 4. Transceiver timing diagrams Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause catastrophic damage to the device. Limits apply to each parameter in isolation. all other parameters having values within the recommended operation conditions. It should not be assumed that limiting values of more than one parameter can be applied to the products at the same time. Exposure to the absolute maximum ratings for extended periods can adversely affect device reliability. Parameter Symbol Min Max Unit Notes Storage Temperature TS -40 +100 °C Case Operating Temperature TC -40 +85 °C Note 1, 2 Lead Soldering Temperature TSOLD 260 °C Note3 Lead Soldering Time tSOLD 10 s Note 3 Supply Voltage VCC -0.5 4.0 V Data Input Voltage VI -0.5 VCC V Notes: 1. Operating the product outside the maximum rated case operating temperature range will compromise its reliability and may damage the product. 2. The temperature is measured using a thermocouple connected to the hottest position of the housing. 3. The transceiver is Pb-free wave solderable. 4 Recommended Operating Conditions Parameter Symbol Min. Typ. Case Operating Temperature TC -40 Supply Voltage VCC 2.97 Receiver Output Termination Impedance RL 100 Ω Signaling Rate (Fast Ethernet) BFE 125 MBd 4B/5B, note 3 Signaling Rate (general) BG MBd Note 4 3.30 10 Max. Unit Notes +85 °C Note 1, 2 3.63 V 250 Notes: 1. The temperature is measured using a thermocouple connected to the housing. 2. Electrical and optical specifications of the product are guaranteed across recommended case operating temperature range only. 3. Ethernet auto-negotiation pulses are not supported. 4. Min. signaling rate for bi-phase coded signal. Max. signaling rate for 8B/10B coded signal (verified by PRBS 27-1 test pattern). Transceiver Electrical Characteristics Parameter Symbol Supply Current ICC Power Dissipation PDISS Power Supply Noise Immunity PSNI Min. Typ. Max. Unit 50 65 mA 165 240 50 mW mV Tx Differential Input Voltage (pk-pk) VDI 200 1800 mV Tx Input Voltage Range to Circuit Common 0 2.4 V VI Notes Peak to peak, Note 1 Notes: 1. Frequencies from 0.1MHz to 100MHz, sine wave. Transmitter Optical Characteristics Parameter Symbol Min. Typ. Max. Unit Notes Average Launched Power (1mm POF, NA=0.5) PO-POF -10.0 -6.5 -3.0 dBm Note 1 Extinction Ratio EXT 10 dB Note 1 Central Wavelength λC 635 nm Note 1, 2 Spectrum RMS Δλ Optical Rise Time (10%-90%) 650 675 17 nm Note 2, 3 tR 1.7 2 ns Note 1 Optical Fall Time (90%-10%) tF 1.6 2 ns Note 1 Duty Cycle Distortion Contributed by the Transmitter DCD 1 ns Peak to peak, note 1 Data Dependent Jitter JDD 0.6 ns Note 1 Random Jitter Contributed by the Transmitter JR 0.76 ns Peak to peak, notes 1, 4 Overshoot OS 25 % Note 1 7 Notes: 1. Measured at the end of 1 meter plastic optical fiber with a PRBS 2-7 sequence, running at 250 MBd data rate 2. Central wavelength is defined as: Ref: EIA/TIA standard FOTP-127/6.1, 1991 3. Spectrum RMS is defined as: Ref: EIA/TIA standard FOTP-127/6.3, 1991 4. Based on BER=2.5x10-10 5 Receiver Electrical Characteristics Parameter Symbol Min. 500 Typ. Max. Unit Differential Output Voltage (pk-pk) VDO Output Common Mode Voltage VOCM 1.2 Data Output Rise Time (10%-90%) tR 0.8 Data Output Fall Time (90%-10%) tF 0.8 1.5 ns Note 1 Duty Cycle Distortion DCD 1.0 ns Notes 1, 2 Data Dependent Jitter JDD 1.2 ns Notes1, 2 Random Jitter JR RSSI Output Responsivity IRSSI/PIN Voltage at RSSI Output VRSSI 900 Notes 1.5 2.14 0.45 0 VCC-1.5 mV Note 1 V Note 1 ns Note 1 ns Peak to peak, notes 1, 2, 3 A/W Fig. 5, 6 V Notes: 1. Characterized with LVDS termination (100 Ω) 2. Contributed by Rx only. 3. Based on BER=2.5x10-10 1000 0.8 IRSSI/PIN - A//W VRSSI - mV 0.7 100 10 0.6 0.5 0.4 0.3 1 0.2 -30 -20 -10 PIN - OPTICAL INPUT POWER - dBm 0 Figure 5. Typical RSSI output voltage across RRSSI = 2 kΩ -40 -20 0 20 40 T - TEMPERATURE - °C 60 80 Figure 6. Typical responsivity vs. temperature Notes: RSSI is actually a current output, providing an output current proportional to the coupled optical power. To provide a suitable monitoring voltage, choose the value of RRSSI according to the particular optical power situation. For the characterization of the RSSI output responsivity, as shown in figure 5, a 2 kΩ resistor was used. The lower the power, the higher the resistor value should be. However, do not override the max. limit of VRSSI. Receiver Optical Characteristics Parameter Symbol Min Unstressed receiver sensitivity, (POF) for Fast Ethernet data rate (125 MBd) CSEN125 Unstressed receiver sensitivity, (POF) for data rate 250 Mbd CSEN250 Input Optical Power Maximum, (POF) PIN-MAX Typ Max Unit Notes -26 dBm Note 1 -22 dBm Note 2 dBm Notes 1, 3 -3.0 635 650 675 nm Operating Wavelength λC Assert input power level PA -29.5 dBm Notes 4, 5 De-assert input power level PD -31 dBm Notes 4, 5 Hysteresis between assert and de-assert PA-PD 1.0 dBm Note 5 Notes: 1. Measured with PRBS 27-1 sequence at 125 MBd, BER < 2.5x10-10 2. Measured with PRBS 27-1 sequence at 250 MBd, BER < 2.5x10 -10 3. Input Optical Power Maximum is defined as the maximum optical modulation amplitude where the receiver duty cycle distortion reaches ±1 ns. 4. Asserted and De-asserted levels are indicated as dB below unstressed receiver sensitivity level for POF. 5. There is an internal SD (signal detect) signal which is directly related to assert (PA) de-assert (PD) levels. There is no direct access to the SD signal, however the Rx data outputs will squelch and the RSSI will switch off, once the optical input power falls below PD. Furthermore, the Rx data and RSSI outputs will be activated, once the optical input power exceeds PA 6 Package Outline Drawing 2.54 (6x) 2.54 0 0.63 1.5 1.9 3.23 4.23 3.68 2.68 (4 x ) 6.35 0 3.4 5.75 7.65 5 21.45 R0 . 15.9 TX (0.3) 6.65 12.6 11.9 Optical Axes 3 RX 1 2.67 7.35 0.25 (2x) 3.04 n0.4 (8x) 11.52 10.8 NOTES (unless otherwise specified): 1) Dimension: mm 2) Label with Partnumber, Lotnumber and Datecode (10mm x 12mm) 2) Figure 7. Package Outline Drawing DISCLAIMER: Avago’s products and software are not specifically designed, manufactured or authorized for sale as parts, components or assemblies for the planning, construction, maintenance or direct operation of a nuclear facility or for use in medical devices or applications. Customer is solely responsible, and waives all rights to make claims against Avago or its suppliers, for all loss, damage, expense or liability in connection with such use. For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2015 Avago Technologies. All rights reserved. AV02-4953EN - September 17, 2015
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