AFBR-59E4APZ-HT

AFBR-59E4APZ-HT Multimode Small Form Factor (SFF) Transceiver for Fast Ethernet, with LC Connector Data Sheet Description Features The AFBR-59E4APZ-HT is a new power saving Small Form Factor transceiver that gives the system designer a product to implement a range of solutions for multimode fiber Fast Ethernet.  This transceiver is supplied in the industry standard 2 × 5 DIP style with an LC fiber connector interface.      Transmitter The transmitter section of the AFBR-59E4APZ-HT transceiver utilizes a 1310 nm LED. This LED is packaged in the optical subassembly portion of the transmitter section. It is driven by an integrated circuit that converts differential LVPECL logical signals into an analog LED drive current.    Application  Receiver Multisourced 2 × 5 package style Operates with 62.5/125 μm and 50/125 μm multimode fiber Single +3.3 V power supply Wave solder and aqueous wash process compatibility Manufactured in an ISO 9001 certified facility Compatible with the optical performance requirements of 100Base-FX version of IEEE 802.3u RoHS compliant LVPECL Signal Detect Output Temperature range: –40 °C to +95 °C The receiver utilizes an InGaAs PIN photodiode coupled to a trans-impedance pre-amplifier IC. It is packaged in the optical subassembly of the receiver. The PIN/preamplifier combination is connected to a quantizer IC, which provides the final pulse shaping for data output. The data output is differential LVPECL. The Signal Detect output is single-ended. Both Data and Signal Detect outputs are LVPECL compatible. Avago Technologies -1- Fast Ethernet AFBR-59E4APZ-HT Data Sheet Package Package Pin Descriptions The package outline drawing and pinout are shown in Figure 1 and Figure 5. The low profile of the Avago transceiver design complies with the maximum height allowed for the LC connector over the entire length of the package. Pin 1 Receiver Signal Ground VEE RX The optical subassemblies utilize a high-volume assembly process together with low-cost lens elements, which result in a cost-effective building block. The electrical subassembly consists of a high volume multilayer printed circuit board on which the ICs and various surface-mounted passive circuit elements are attached. The receiver and transmitter sections include an internal shield for the electrical and optical subassemblies to ensure high immunity to external EMI fields. The outer housing including the LC ports is molded of filled nonconductive plastic to provide mechanical strength. The solder posts of the Avago design are isolated from the internal circuit of the transceiver. The transceiver is attached to a printed circuit board with the ten signal pins and the two solder posts, which exit the bottom of the housing. The two solder posts provide the primary mechanical strength to withstand the loads imposed on the transceiver by mating with the LC connector fiber cables. Figure 1 Pin Out Diagram RX Directly connect this pin to the receiver ground plane. Pin 2 Receiver Power Supply VCC RX Provide +3.3 V DC via the recommended receiver power supply filter circuit. Locate the power supply filter circuit as close as possible to the VCC RX pin. Pin 3 Signal Detect SD Normal optical input levels to the receiver result in a logic “1” output. Low optical input levels to the receiver result in a logic “0” output. Pin 4 Receiver Data Out Bar RDSignal AC coupled LVPECL. See Figure 2. Pin 5 Receiver Data Out RD+ Signal AC coupled LVPECL. See Figure 2. Pin 6 Transmitter Power Supply VCC TX Provide +3.3 V DC via the recommended transmitter power supply filter circuit. Locate the power supply filter circuit as close as possible to the VCC TX pin. TX Pin 7 Transmitter Signal Ground VEE TX Mounting Studs/Solder Posts Directly connect this pin to the transmitter ground plane. Pin 8 NC Not connected. Housing leads Top Pin 9 Transmitter Data In TD+ View Signal AC coupled LVPECL. See Figure 2. RECEIVER SIGNAL GROUND RECEIVER POWER SUPPLY SIGNAL DETECT RECEIVER DATA OUT BAR RECEIVER DATA OUT o o o o o 1 2 3 4 5 10 9 8 7 6 o o o o o TRANSMITTER DATA IN BAR TRANSMITTER DATA IN NC TRANSMITTER SIGNAL GROUND TRANSMITTER POWER SUPPLY Pin 10 Transmitter Data In Bar TDSignal AC coupled LVPECL. See Figure 2. Mounting Studs/Solder Posts The mounting studs are provided for transceiver mechanical attachment to the circuit board. It is recommended that you connect the holes in the circuit board to chassis ground. Housing Leads The transceiver housing leads are provided for additional signal grounding. The holes in the circuit board must be tied to signal ground. Avago Technologies -2- AFBR-59E4APZ-HT Data Sheet Application Information Application Information Shipping Container The Applications Engineering group is available to assist you with the technical understanding and design trade-offs associated with these transceivers. You can contact them through your Avago sales representative. The transceiver is packaged in a shipping container designed to protect it from mechanical and ESD damage during shipment of storage. The following information is provided to answer some of the most common questions about the use of these parts. Board Layout – Decoupling Circuit, Ground Planes and Termination Circuits Transceiver Optical Power Budget versus Link Length Optical Power Budget (OPB) is the available optical power for a fiber optic link to accommodate fiber cable losses plus losses due to in-line connectors, splices, optical switches, and to provide margin for link aging and unplanned losses due to cable plant reconfiguration or repair. Avago. LED technology has produced 1300 nm LED devices with lower aging characteristics than normally associated with these technologies in the industry. The industry convention is 1.5 dB aging for 1300 nm LEDs. The 1300 nm Avago LEDs are specified to experience less than 1 dB of aging over normal commercial equipment mission life periods. Contact your Avago sales representative for additional details. Recommended Handing Precautions Avago recommends that normal status precautions be taken in the handling and assembly of these transceivers to prevent damage, which may be induced by electrostatic discharge (ESD). The AFBR-59E4APZ-HT transceiver meets Jedec JESD22-A114 Class 2 products. Care should be used to avoid shorting the receiver data or signal detect outputs directly to ground without proper current limiting impedance. Solder and Wash Process Compatibility To achieve optimum performance from these transceivers, do take care in the layout of your circuit board. Figure 2 provides a schematic for a recommended termination circuit that works well with these parts, It is further recommended that a contiguous ground plane be provided in the circuit board directly under the transceiver to provide a low-inductance ground for signal return current. This recommendation is in keeping with good high frequency board layout practices. Figure 3 shows a recommended power supply filter. Board Layout – Hole Pattern The Avago transceiver complies with the circuit board “Common Transceiver Footprint” hole pattern defined in the multisource announcement that defined the 2 × 5 package style (except for the position of one housing lead as shown in Figure 5). This drawing is reproduced in Figure 5 with the addition of ANSI Y14.5M compliant dimensioning to be used as a guide in the mechanical layout of your circuit board. Figure 5 illustrates the recommended panel opening and the position of the circuit board with respect to this panel. Regulatory Compliance These transceiver products are intended to enable commercial system designers to develop equipment that complies with the various international regulations governing certification of Information Technology Equipment. See the Regulatory Compliance Table for details. Additional information is available from your Avago sales representative. The transceivers are delivered with protective process plugs inserted into the LC receptacle. This process plug protects the optical subassemblies during wave solder and aqueous wash processing, and acts as a dust cover during shipping. These transceivers are compatible with either industry standard wave or hand solder processes. Avago Technologies -3- AFBR-59E4APZ-HT Data Sheet Regulatory Compliance Figure 2 Recommended Termination Circuit AFBR-59E4APZ-HT SerDes IC (AC Coupling Data) 50 Ω TX+ 100 nF i 50 Ω i TX- 100 nF 100Ω LED Driver LED AMPLIFIER & QUANTIZER PD 3.3 V 2.7 kΩ 50 Ω 2.7 kΩ RX+ 100 nF i 50 Ω 100 Ω i 4.3 kΩ RX- 4.3 kΩ GND 100 nF 150 Ω Control Logic SD PECL input 150 Ω GND 10 kΩ GND NOTE Refer to SerDes supplier's recommendation regarding the interface between AFBR-59E4APZ-HT and SerDes. The proposed termination is recommended for LVPECL AC-coupled signals. Other terminations could also be applicable, depending on the SerDes interface. Figure 3 Recommended Power Supply Filter AFBR-59E4APZ-HT 1 μH Vcc TX 0.1 μF 1 μH Vcc RX 0.1 μF NOTE 10 μF 0.1 μF 10 μF 3.3V Inductors should have less than 1  series resistor per MSA. Avago Technologies -4- AFBR-59E4APZ-HT Data Sheet Regulatory Compliance Figure 4 Package Outline Drawing 0.5 MIN clearance/creepage NOTE All dimensions are in millimeters (inches). Avago Technologies -5- AFBR-59E4APZ-HT Data Sheet Regulatory Compliance Figure 5 Recommended Board Layout Hole Pattern 0.81 ± .10 20 x Ø (.032 ± .004) 25.75 (1.014) SEE DETAIL B SEE NOTE 3 4 x Ø 1.40 ± .10 (NOTE 5) (.055 ± .004) SEE DETAIL A SEE NOTE 5 13.34 (.525) 12.16 (.479) 10.16 (.400) 15.24 MIN. PITCH (.600) 54321 7.59 10.16 (.299) (.400) 6 7 8 9 10 2 x Ø 2.29 MAX. (AREA FOR EYELET'S) (.090) 2 x Ø 1.40 ± .10 (NOTE 4) (.055 ± .004) 3 (.118) 3 (.118) 7.11 (.280) 3.56 (.140) 6 (.236) 8.89 (.350) DETAIL A (4 x) 1.78 9 X (.070) 1.8 .071 1 .039 15.24 (.600) MIN. PITCH + 1.50 1.00 - 0 (+.059) (.039) (- .000) DETAIL B (4 x) A 14.22 ± .10 (.560 ± .004) TOP OF PCB A 10.16 ± .10 (.400 ± .004) +0 15.75 - 0.75 (+.000) (.620) (- .030) A SECTION A - A NOTE 1. 2. 3. 4. 5. 6. This page describes the recommended circuit board footprint and front panel openings for SFF transceivers. The hatched areas are keep-out areas reserved for housing stand-offs. No metal traces are allowed in keep-out areas. The drawing shows extra pin holes for 2x6 pin and 2x10 pin transceivers. These extra holes are not required for AFBR-59E4APZ-HT and other 2x5 pin SFF modules. Holes for mounting studs must not be tied to signal ground; they should be tied to chassis ground. Hole position deviates from “Common Transceiver Footprint” hole pattern defined in the multisource announcement. All dimensions are in millimeters (inches). Avago Technologies -6- AFBR-59E4APZ-HT Data Sheet Electrostatic Discharge (ESD) Electrostatic Discharge (ESD) Immunity There are two design cases in which immunity to ESD damage is important. Equipment utilizing these transceivers will be subject to radio-frequency electromagnetic fields in some environments. These transceivers have a high immunity to such fields. The first case is when the transceiver is handled before it is mounted on the circuit board. NOTE Use normal ESD handling precautions for ESD-sensitive devices. These precautions include using grounded wrist straps, work benches, and floor mats in ESD-controlled areas. The second case to consider is static discharges to the exterior of the equipment chassis that contains the transceiver parts. To the extent that the LC connector is exposed to the outside of the equipment chassis, it may be subject to whatever ESD system-level test criteria that the equipment is intended to meet. For additional information regarding EMI, susceptibility, ESD and conducted noise testing procedures and results, refer to Application Note 1166, Minimizing Radiated Emissions of High-Speed Data Communications Systems. Transceiver Reliability and Performance Qualification Data The 2 × 5 transceivers have passed Avago reliability and performance qualification testing and are undergoing ongoing quality and reliability monitoring. Details are available from your Avago sales representative. Electromagnetic Interference (EMI) Most equipment designs utilizing this high speed transceiver from Avago will be required to meet the requirements of FCC in the United States, and CENELEC EN55022 (CISPR 22) in Europe. Avago Technologies -7- AFBR-59E4APZ-HT Data Sheet Regulatory Compliance Table Regulatory Compliance Table Feature Test Method Performance Electrostatic Discharge (ESD) to the Electrical Pins JEDEC JESD22-A114 Meets Class 2 (2000 to 3999 V).Withstand up to 2000 V applied between electrical pins. Electrostatic Discharge (ESD) to the LC Receptacle Variation of IEC 61000-4-2 Typically withstand at least 9 kV without damage when the LC connector receptacle is contacted by a Human Body Model probe. Typically withstand 15 kV air discharge on LC-connector receptacle. Electromagnetic Interference (EMI) FCC Class B CENELEC CEN55022 Class B Transceivers typically provide a 10 dB margin to the noted standard limits when tested at a certified test range with the transceiver mounted to a circuit card. Immunity Variation of IEC 61000-4-3 Typically show no measurable effect from a 10 V/m field swept from 80 MHz to 1 GHz applied to the transceiver when mounted to a circuit card without a chassis enclosure. Eye Safety EN 60950-1:2006+A11+A1+A12 EN 60825-1:2007 EN 60825-2:2004+A1+A2 Compliant per Avago testing under single fault conditions. TUV Certification – R 50236535 0003 Component Recognition UL File #: E173874, Vol. 1 Underwriters Laboratories and Canadian Standards Association Joint Component Recognition for Information Technology Equipment including Electrical Business Equipment RoHS Compliance Reference to RoHS Directive 2011/65EU Annex II Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause catastrophic damage to the device. Limits apply to each parameter in isolation, all other parameters having values within the recommended operating conditions. It should not be assumed that limiting values of more than one parameter can be applied to the product at the same time. Exposure to the absolute maximum ratings for extended periods can adversely affect device reliability. Parameter Symbol Minimum Maximum Unit +100 °C TSOLD +260 °C Lead Soldering Time tSOLD 10 sec Supply Voltage VCC –0.5 3.63 V Data Input Voltage VI –0.5 VCC V Differential Input Voltage (p-p) VD 1.9 V Storage Temperature TS Lead Soldering Temperature –40 Typical NOTE 1. Moisture sensitivity level is MSL-1. Avago Technologies -8- Notes 1 AFBR-59E4APZ-HT Data Sheet Recommended Operating Conditions Recommended Operating Conditions Parameter Symbol Minimum Typical Maximum Unit Case Operating Temperature TC –40 Supply Voltage VCC 3.0 Data Output Load RL 100  Signaling Rate B 125 MBd 3.3 +95 °C 3.6 V Notes 1 NOTE 1. Fast Ethernet 4B/5B. Transmitter Electrical Characteristics Parameter Symbol Minimum Typical Maximum Unit Notes Supply Current ICC 80 120 mA Power Dissipation PDISS 270 440 mW Differential Input Voltage VDIFF 1.0 1.6 V 2 Input Differential Impedance RIN  3 0.8 100 1 NOTE 1. 2. 3. Typical values are for room temperature at 3.3 V. Peak to Peak. Tx data inputs are AC coupled. Receiver Electrical Characteristics Parameter Symbol Minimum Typical Maximum Units Notes Supply Current ICC 65 85 mA Power Dissipation PDISS 215 310 mW Data Output: Differential Output Voltage (RD+/-) |VOH – VOL| 2.0 V Data Output Rise Time (10%-90%) tr 2.2 ns Data Output Fall Time (10%-90%) tf 2.2 ns Signal Detect Output Voltage - Low SDVOL Vdd -– 1.81 Vdd – 1.62 V 3 Signal Detect Output Voltage - High SDVOH Vdd – 1.02 Vdd – 0.88 V 3 0.4 1, 2 NOTE 1. 2. 3. Differential output voltage is internally AC-coupled. The low and high voltages are measured using 100 Ohm differential termination. RD+ and RD- outputs are squelched at SD deassert level. Measured with an external 10 kOhm resistor to ground. Avago Technologies -9- AFBR-59E4APZ-HT Data Sheet Transmitter Optical Characteristics Transmitter Optical Characteristics Parameter Symbol Min. Output Optical Power 62.5/125 μm, NA = 0.275 Fiber PO –20.0 Output Optical Power 50/125 μm, NA = 0.20 Fiber PO –23.5 Typ. –16.5 Extinction Ratio ER 10 Center Wavelength C 1270 1308 Spectral Width – FWHM  Optical Rise Time (10%–90%) tr 0.6 Optical Fall Time (10%–90%) tf 0.6 Duty Cycle Distortion Contributed by the Transmitter Data Dependent Jitter Contributed by the Transmitter Random Jitter Contributed by the Transmitter Max. Units Notes –14.0 dBm 1, 2 –14.0 dBm 1, 2 dB 1380 nm 1.0 3.0 ns 1.0 3.0 ns DCD 0.6 ns 3 DDJ 0.6 ns 3 RJ 0.69 ns 3, 4 147 nm NOTE 1. 2. Optical values are measured over the specified operating voltage and temperature ranges. The average power can be converted to a peak value by adding 3 dB. Average. 3. 4. Characterized with 125 MBd, PRBS27-1 pattern. Peak to Peak. Avago Technologies - 10 - Receiver Optical and Electrical Characteristics Parameter Symbol Min. Typ. Max. Units Notes Input Optical Power PIN –31 -14 dBm 1, 2 Operating Wavelength  1270 1380 nm Duty Cycle Distortion Contributed by the Receiver DCD 0.4 ns 3, 4 Data Dependent Jitter Contributed by the Receiver DDJ 1.0 ns 3 Random Jitter Contributed by the Receiver RJ 2.14 ns 3, 5 Signal Detect – Assert SDA -33.0 dBm 2 Signal Detect – Deassert SDD –45.0 dBm 2 Signal Detect – Hysteresis SDD – SDA 0.5 Signal Detect Assert Time (off to on) SDon 0 100 μs 6 Signal Detect Deassert Time (on to off ) SDoff 0 350 μs 7 1.9 dB NOTE 1. 2. 3. 4. 5. 6. 7. This specification is intended to indicate the performance of the receiver section of the transceiver when Optical Input Power signal characteristics are present per the following definitions. * Over the specified operating temperature and voltage ranges * Bit Error Rate (BER) is better than or equal to 1 × 10-10 * Transmitter is operating to simulate any cross-talk present between the transmitter and receiver sections of the transceiver. Average. Characterized with 125 MBd, PRBS27-1 pattern. Duty Cycle Distortion contributed by the receiver is measured at 50% threshold of the electrical signal. The input optical power level is –20 dBm average. Peak to Peak. Signal Detect output shall be asserted within the specified time after a step increase of the Optical Input Power. Signal Detect output shall be deasserted within the specified time after a step decrease of the Optical Input Power. For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago Technologies and the A logo are trademarks of Avago Technologies in the United States and other countries. All other brand and product names may be trademarks of their respective companies. Data subject to change. Copyright © 2015–2016 Avago Technologies. All Rights Reserved. pub-005160 – March 24, 2016