AMMP-6222-BLKG

AMMP-6222 7 to 2 GHz GaAs High Linearity LNA in SMT Package Data Sheet Description Avago Technologies’ AMMP-6222 is an easy-to-use broadband, high gain, high linearity Low Noise Amplifier in a surface mount package. The wide band and unconditionally stable performance makes this MMIC ideal as a primary or sub-sequential low noise block or a transmitter or LO driver. The MMIC has 3 gain stages and a selectable pin to switch between low and high current, corresponding with low and high output power and linearity. In the high current, high output power state, it requires a 4V, 120mA supply. In the low current, low output power state, the supply is reduced to 4V, 95mA. Since this MMIC covers several bands, it can reduce part inventory and increase volume purchase options The MMIC is fabricated using PHEMT technology. The surface mount package eliminates the need of “chip & wire” assembly for lower cost. This MMIC is fully SMT compatible with backside grounding and I/Os. Features • • • • • • • • • Surface Mount Package, 5.0 x 5.0 x 1.25 mm Single Positive Bias Pin Selectable Output Power / Linearity No Negative Gate Bias Specifications (Vdd = 4.0V, Idd = 120mA) RF Frequencies: 7 - 21 GHz High Output IP3: 29dBm High Small-Signal Gain: 24dB Typical Noise Figure: 2.3dB Input, Output Match: -10dB Applications • Microwave Radio systems • Satellite VSAT, DBS Up/Down Link • LMDS & Pt-Pt mmW Long Haul • Broadband Wireless Access (including 802.16 and 802.20 WiMax) • WLL and MMDS loops • Commercial grade military Note: 1. This MMIC uses depletion mode pHEMT devices. Pin Connections (Top View) 1 2 3 100pF 8 4 7 6 5 Pin 1 2 3 4 5 6 7 8 Function Vdd RFout Current Sel RFin Top view Package base: GND Attention: Observe precautions for handling electrostatic sensitive devices. ESD Machine Model (60V) ESD Human Body Model (150V) Refer to Avago Application Note A004R: Electrostatic Discharge Damage and Control  Absolute Maximum Ratings (1) Parameters/Condition Drain to Ground Voltage Drain Current RF CW Input Power Max Max channel temperature Storage temperature Maximum Assembly Temp Symbol Vdd Idd Pin Tch Tstg Tmax Unit V mA dBm C C C Maximum 5.5 70 0 +50 -65 +50 260 for 20s 1. Operation in excess of any of these conditions may result in permanent damage to this device. The absolute maximum ratings for Vdd, Idd and Pin were determined at an ambient temperature of 25°C unless noted otherwise. DC Specifications/ Physical Properties (2) Parameter and Test Condition Drain Supply Current under any RF power drive and temp. (Vd=4.0 V) Drain Supply Voltage Thermal Resistance(3) Symbol Idd Vd θjc Unit mA V °C/W Minimum 80 3 Typical 20 4 3.4 Maximum 60 5 2. Ambient operational temperature TA=25°C unless noted 3. Channel-to-backside Thermal Resistance (Tchannel = 34°C) as measured using infrared microscopy. Thermal Resistance at backside temp. (Tb) = 25°C calculated from measured data. AMMP-6222 RF Specifications (4) TA= 25°C, Idd=20mA, Vdd = 4.0 V, Zo=50 W Parameters and Test Conditions Drain Current Small-Signal Gain (5) Noise Figure into 50W (5) Output Power at dB Gain Compression Output Power at 3dB Gain Compression Output Third Order Intercept Point Isolation Input Return Loss Output Return Loss Symbol Idd Gain NF P-dB P-3dB OIP3 Iso RLin RLout Units mA dB dB dBm dBm dBm dB dB dB 9, 2, 7 9, 2, 7 9 Freq. (GHz) High Output Power Configuration Minimum Typical 20 24 2.3 5.5 7.5 29 -45 -0 -0 3.5 Maximum Low Output Power Configuration Minimum Typical 95 23 2.3 4 6 27 -45 -0 -0 Maximum 4. Refer to characteristic plots for detailed individual frequency performance. 5. All tested parameters guaranteed with measurement accuracy ± 0.5dB for gain and ±0.3dB for NF in the high output power configuration. 2 AMMP-6222 Typical Performance for High Current, High Output Power Configuration [1], [2] (TA = 25°C, Vdd=4V, Idd=120mA, Zin = Zout = 50 W unless noted) 30 25 S21 (dB) 20 15 10 5 5 10 15 20 25 Fre que ncy (GHz ) 5 Noise Figure (dB) 4 3 2 1 0 6 8 10 12 14 16 18 20 22 Fre quency (GHz) Figure 1a. Small-signal Gain 0 Figure 2a. Noise Figure 20 OP1dB (dBm ) 5 10 15 20 25 -5 S11 (dB) -10 -15 -20 -25 Freque ncy (GHz ) 15 10 5 0 6 8 10 12 14 16 18 20 22 Freque ncy (GHz ) Figure 3a. Input Return Loss 0 -5 S22 (dB) -10 -15 -20 5 10 15 20 25 Fre que ncy (GHz ) Figure 4a. Output P-1dB 35 OI P3 (dBm) 30 25 20 15 10 6 8 10 12 14 16 18 20 22 Freque ncy (GHz ) Figure 5a. Output Return Loss Figure 6a. Output IP3 Note: 1. S-parameters are measured with R&D Eval Board as shown in Figure 21. Board and connector effects are included in the data. 2. Noise Figure is measured with R&D Eval board as shown in Figure 21, and with a 3-dB pad at input. Board and connector losses are already deembeded from the data. 3 AMMP-6222 Typical Performance for High Current, High Output Power Configuration (Cont) ( TA = 25°C, Vdd=4V, Idd=120mA, Zin = Zout = 50 W unless noted) -20 -30 S12 (dB) -40 -50 -60 5 10 15 20 25 Freque ncy (GHz ) 150 130 Idd (m A) 110 90 70 3 3. 5 4 Vdd (V) 4.5 5 Figure 7a. Isolation 30 Figure 8a. Idd over Vdd 5 Noise Figure (dB) 4 3 2 1 0 6 8 10 12 14 16 18 3V 4V 5V 25 S21 (dB) 20 15 10 5 5 10 15 20 Freque ncy (GHz ) 25 4V 5V 3V 20 22 Freque ncy (GHz ) Figure 9a. Small-signal Gain Over Vdd 0 Figure 10a. Noise Figure Over Vdd 0 -5 S22 (dB) S11 (dB) -10 -10 -15 -20 -25 4V 5V 3V -20 4V 3V 5V -30 5 10 15 20 Fre que ncy (GHz ) 25 5 10 15 20 Freque ncy (GHz ) 25 Figure 11a. Input Return Loss Over Vdd Figure 12a. Output Return Loss Over Vdd 4 AMMP-6222 Typical Performance for High Current, High Output Power Configuration (Cont) ( TA = 25°C, Vdd=4V, Idd=120mA, Zin = Zout = 50 W unless noted) 25 OP1dB (dBm) 15 10 5 0 6 8 10 12 14 16 18 Freque ncy (GHz ) 3V 4V 5V OI P3 (dBm) 20 35 30 25 20 15 10 5 0 6 8 10 12 14 16 Freque ncy (GHz ) 3V 4V 5V 20 22 18 20 22 Figure 13a. Output P1dB over Vdd 35 30 S21 (dB) 25 20 15 10 5 5 25C 85C -40C Figure 14a. Output IP3 over Vdd 8 Noise Figure (dB) -40C 6 4 2 0 25C 85C 10 15 20 Fre quency (GHz ) 25 6 8 10 12 14 16 18 20 22 Fre que ncy (GHz ) Figure 15a. Small-signal Gain Over Temp 0 -5 S11 (dB) Figure 16a. Noise Figure Over Temp 0 25C S22 (dB) -10 -15 -20 -25 5 25C -40C 85C -5 -10 -15 -20 5 85C -40C 10 15 20 Fre que ncy (GHz ) 25 10 15 20 Freque ncy (GHz ) 25 Figure 17a. Input Return Loss Over Temp Figure 18a. Output Return Loss Over Temp 5 AMMP-6222 Typical Performance for Low Current, Low Output Power Configuration [1], [2] ( TA = 25°C, Vdd=4V, Idd=95mA, Zin = Zout = 50 W unless noted) 30 25 S21 (dB) 20 15 10 5 5 10 15 20 25 Freque ncy (GHz ) 5 Noise Figure (dB) 4 3 2 1 0 6 8 10 12 14 16 18 20 22 Fre que ncy (GHz ) Figure 1b. Small-signal Gain 0 Figure 2b. Noise Figure 20 OP1dB (dBm) 15 10 5 0 6 8 10 12 14 16 18 20 22 -5 S11 (dB) -10 -15 -20 -25 5 10 15 20 25 Freque ncy (GHz ) Fre que ncy (GHz ) Figure 4b. Output P-1dB Figure 3b. Input Return Loss 0 OIP3 (dBm) 35 30 25 20 15 10 6 8 10 12 14 16 18 20 22 Freque nc y (GHz) S 22 (dB) -5 -10 -15 -20 5 10 15 20 25 Fre que ncy (GHz ) Figure 5b. Output Return Loss Figure 6b. Output IP3 Note: 1. S-parameters are measured with R&D Eval Board as shown in Figure 21. Board and connector effects are included in the data. 2. Noise Figure is measured with R&D Eval board as shown in Figure 21, and with a 3-dB pad at input. Board and connector losses are already deembeded from the data 6 AMMP-6222 Typical Performance for Low Current, Low Output Power Configuration (Cont) ( TA = 25°C, Vdd=4V, Idd=95mA, Zin = Zout = 50 W unless noted) -20 -30 S12 (dB) -40 -50 -60 5 10 15 20 25 Freque ncy (GHz ) 130 110 Idd (m A) 90 70 50 3 3.5 4 Vdd (V) 4.5 5 Figure 7b. Isolation 30 Figure 8b. Idd over Vdd 5 Noise Figure (dB) 4 3 2 1 0 25 3V 4V 5V 25 S21 (dB) 20 15 10 5 5 10 15 20 Freque ncy (GHz ) 4V 5V 3V 6 8 10 12 14 16 18 20 22 Freque ncy (GHz ) Figure 9b. Small-signal Gain Over Vdd 0 -5 S11 (dB) -15 -20 -25 -30 5 10 15 20 Fre que ncy (GHz ) 25 4V 3V 5V Figure 10b. Noise Figure Over Vdd 0 -5 S 22 (d B) -10 -15 -20 -25 -30 5 10 15 20 Fre que ncy (GHz ) 25 4V 5V 3V -10 Figure 11b. Input Return Loss Over Vdd Figure 12b. Output Return Loss Over Vdd 7 AMMP-6222 Typical Performance for Low Current, Low Output Power Configuration (Cont) ( TA = 25°C, Vdd=4V, Idd=95mA, Zin = Zout = 50 W unless noted) 20 OP1dB (dBm) 10 5 0 6 8 10 12 14 16 18 OI P3 (dBm) 15 3V 4V 5V 35 30 25 20 15 10 5 0 6 8 Fre que ncy (GHz ) 3V 4V 5V 20 22 10 12 14 16 18 20 22 Fre que ncy (GHz ) Figure 13b. Output P1dB over Vdd 35 30 S21 (dB) 25 20 15 10 5 5 25C 85C -40C Figure 14b. Output IP3 over Vdd 8 Noi se Figure (dB) -40C 6 4 2 0 25C 85C 10 15 20 Fre quency (GHz) 25 6 8 10 12 14 16 18 20 22 Fre que ncy (GHz ) Figure 15b. Small-signal Gain Over Temp 0 -5 S11 (dB) Figure 16b. Noise Figure Over Temp 0 -5 S22 (dB) -10 -15 -20 -25 25 25C 85C -4 0C -10 -15 -20 -25 -30 5 25C -40C 85C 10 15 20 Fre que ncy (GHz ) -30 5 10 15 20 Freque ncy (GHz ) 25 Figure 17b. Input Return Loss Over Temp Figure 18b. Output Return Loss Over Temp 8 AMMP-6222 Application and Usage 4V Vdd 1 2 0.1uF Biasing and Operation The AMMP-6222 is normally biased with a positive drain supply connected to the VDD pin through bypass capacitor as shown in Figures 19 and 20. The recommended drain supply voltage for general usage is 4V and the corresponding drain current is approximately 120mA. It is important to have 0.1uF bypass capacitor and the capacitor should be placed as close to the component as possible. Aspects of the amplifier performance may be improved over a narrower bandwidth by application of additional conjugate, linearity, or low noise (Topt) matching. For receiver front end low noise applications where high power and linearity are not often required, the AMMP6222 can be set in low current state when pin # 5 is open as shown in Figure 19. In this configuration, the bias current is approximately 90mA, 95mA and 100mA for 3V, 4V and 5V respectively. In applications where high output power and linearity are often required such as LO or transmitter drivers, the AMMP-6222 can be selected to operate at its highest output power by grounding pin # 5 as shown in Figure 20. At 5V, the amplifier can provide Psat of ~ 20dBm. The bias current in this configuration is 115mA, 120mA and 125mA for 3V, 4V and 5V respectively. Refer the Absolute Maximum Ratings table for allowed DC and thermal conditions. 3 100pF IN 8 4 OUT 7 6 5 Open Figure 19. Low Current, Low Output Power State 4V Vdd 1 2 0.1uF 3 IN 100pF 8 4 OUT 7 6 5 Figure 20. High Current, High Output Power State Figure 21. Evaluation/Test Board (available to qualified customer request) Vd1 Vd2 In Matching Network Matching Network Out SELECT Figure 22. Simplified High Linearity LNA Schematic 9 Recommended SMT Attachment for 5x5 Package Figure 23a. Suggested PCB Land Pattern and Stencil Layout Figure 23b. Stencil Outline Drawing (mm) Figure 23c. Combined PCB and Stencil Layouts The AMMP Packaged Devices are compatible with high volume surface mount PCB assembly processes. The PCB material and mounting pattern, as defined in the data sheet, optimizes RF performance and is strongly recommended. An electronic drawing of the land pattern is available upon request from Avago Sales & Application Engineering. 0 Manual Assembly • Follow ESD precautions while handling packages. • Handling should be along the edges with tweezers. • Recommended attachment is conductive solder paste. Please see recommended solder reflow profile. Neither Conductive epoxy or hand soldering is recommended. • Apply solder paste using a stencil printer or dot placement. The volume of solder paste will be dependent on PCB and component layout and should be controlled to ensure consistent mechanical and electrical performance. • Follow solder paste and vendor’s recommendations when developing a solder reflow profile. A standard profile will have a steady ramp up from room temperature to the pre-heat temp. to avoid damage due to thermal shock. • Packages have been qualified to withstand a peak temperature of 260°C for 20 seconds. Verify that the profile will not expose device beyond these limits. 300 250 Temp (˚C) 200 150 100 50 0 Ramp 1 0 50 Preheat Ramp 2 100 Reflow 200 Cooling 250 300 150 Seconds A properly designed solder screen or stencil is required to ensure optimum amount of solder paste is deposited onto the PCB pads. The recommended stencil layout is shown in Figure 23. The stencil has a solder paste deposition opening approximately 70% to 90% of the PCB pad. Reducing stencil opening can potentially generate more voids underneath. On the other hand, stencil openings larger than 100% will lead to excessive solder paste smear or bridging across the I/O pads. Considering the fact that solder paste thickness will directly affect the quality of the solder joint, a good choice is to use a laser cut stencil composed of 0.127mm (5 mils) thick stainless steel which is capable of producing the required fine stencil outline. The most commonly used solder reflow method is accomplished in a belt furnace using convection heat transfer. The suggested reflow profile for automated reflow processes is shown in Figure 24. This profile is designed to ensure reliable finished joints. However, the profile indicated in Figure 14 will vary among different solder pastes from different manufacturers and is shown here for reference only. Peak = 250 ± 5˚C Melting point = 218˚C Figure 24. Suggested Lead-Free Reflow Profile for SnAgCu Solder Paste Package, Tape & Reel, and Ordering Information AMMP-6222 Part Number Ordering Information Part Number AMMP-6222-BLKG AMMP-6222-TRG AMMP-6222-TR2G Devices Per Container 0 00 500 Container Antistatic bag 7” Reel 7” Reel  Package, Tape & Reel, and Ordering Information .011 Top View Side View Back View NOTES: DIMENSIONS ARE IN INCHES [MILIMETERS] ALL GROUNDS MUST BE SOLDERED TO PCB RF Material is Rogers RO4350, 0.010” thick Carrier Tape and Pocket Dimensions For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries. Data subject to change. Copyright © 2006 Avago Technologies Limited. All rights reserved. Obsoletes AV0-044EN AV02-0493EN - June 3, 2007