Data Sheet
BCM53125S
Multiport Gigabit Ethernet Switches
F E A T U RE S
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Seven 10/100/1000 media access controllers
Five-port 10/100/1000 transceivers for TX
One GMII/RGMII/MII/RvMII/TMII/RvTMII
interface for an inband management port (IMP)
for connection to a CPU/management entity
without PHY
One GMII/RGMII/MII/RvMII/TMII/RvTMII
interface for WAN management port
Dual IMP ports support, WAN interface (port 5) to
be management port-capable
IEEE 802.1p, MAC Port, ToS, and DiffServ QoS
for four queues, plus two time-sensitive queues
Port-based VLAN
IEEE 802.1Q-based VLAN with 4K entries
MAC-based trunking with automatic link failover
Port-based rate control
Port mirroring
BroadSync® HD for IEEE 802.1AS support
– Timestamp tagging at MAC interface
– Time-aware egress scheduler
DoS attack prevention
– Support IPv6
– Ingress mirroring
IGMP snooping, MLD snooping support
Spanning tree support (multiple spanning trees,
up to eight)
Embedded CPU (8051) processor for cable
diagnostics, and green power saving mode.
CableChecker™ with unmanaged mode support
Double tagging/QinQ
Egress VID remarking
IEEE 802.az EEE (Energy Efficient Ethernet™)
support
IEEE 802.1AS support
IEEE 802.3x programmable per-port flow control
and backpressure, with IEEE 802.1x support for
secure user authentication
EEPROM, MDC/MDIO, and SPI Interface
Serial Flash Interface for accessing embedded
CPU (8051)
4K entry MAC address table with automatic
learning and aging
128 KB packet buffer (1 KB = 1024 bytes)
128 multicast group support
Jumbo frame support up to 9720 byte
1.2V for core and 3.3V for I/O
RGMII with option of 2.5V or 1.5V
JTAG support
186-pin multirow MLF (MML) package
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The BCM53125S has a rich feature set suitable for
not only standard GbE connectivity for desktop and
laptop PCs, but also for next-generation gaming
consoles, set-top boxes, networked DVD players, and
home theater receivers. It is also specifically designed
for next-generation SOHO/SMB routers and
gateways.
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The Broadcom BCM53125S is a highly integrated,
cost-effective smart-managed Gigabit switch. The
switch design is based on the field-proven, industryleading ROBO architecture. This device combines all
the functions of a high-speed switch system including
packet buffers, PHY transceivers, media access
controllers (MACs), address management, portbased rate control, and a nonblocking switch fabric
into a single 65-nm CMOS device. Designed to be
fully compliant with the IEEE 802.3 and IEEE 802.3x
specifications, including the MAC-control PAUSE
frame, the BCM53125S provides compatibility with all
industry-standard Ethernet, fast Ethernet, and Gigabit
Ethernet (GbE) devices.
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GE NE R AL DE S C RI PT ION
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The BCM53125S contains five full-duplex 1000BaseT/100Base-TX/10Base-T Ethernet transceivers. In
addition, the BCM53125S has one GMII/RGMII/MII/
RvMII/TMII/RvTMII interface for the CPU or a router
chip, providing flexible
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10/100/1000 Mbps connectivity. A GMII/RGMII/MII/
RvMII/TMII/RvTMII interface for the WAN port can be
configured as an IMP port.
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The BCM53125S provides 70+ on-chip MIB counters
to collect receive and transmit statistics for each port.
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The BCM53125S is available in industrial
temperature (I-Temp) and commercial temperature
(C-Temp) rated packages. The BCM53125S is
available in one package type, a 186-pin multirow
MLF (MML) package.
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53125S-DS06-R
Corporate Headquarters: San Jose, CA
March 11, 2016
BCM53125S Data Sheet
Revision History
Figure 1: Functional Block Diagram
BCM53125S
TRD[3:0]_0± (port 0)
10/100/1000
GPHY
GMAC
Registers
TRD[3:0]_1± (port 1)
10/100/1000
GPHY
GMAC
Packet Buffer
MMU
10/100/1000
GPHY
TRD[3:0]_3± (port 3)
10/100/1000
GPHY
GMAC
GMII/RGMII/MII/RvMII/TMII (port 5)
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GMAC
LED Interface
8051
controller
LED
Flash Memory
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GMAC
EEPROM/ SPI
Interface
EEPROM/CPU
GMAC
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GMII/RGMII/MII/RvMII/TMII (IMP)
GMAC
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10/100/1000
GPHY
Address
Management
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TRD[3:0]_4± (port 4)
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TRD[3:0]_2± (port 2)
Broadcom®
March 11, 2016 • 53125S-DS06-R
BROADCOM CONFIDENTIAL
Page 2
Revision History
Revision
Date
Change Description
53125S-DS06-R
3/11/16
Note: Page numbers referenced are valid for this revision of the document
only.
Updated:
• Section 12: “Ordering Information,” on page 307
04/27/11
53125S-DS04-R
01/19/11
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53125S-DS05-R
Added:
• “JTAG Interface” on page 300
Updated:
• “TMII (TURBO MII) and RvTMII (Reverse TMII) Interface” on page 96:
removed the Note stating “The BCM53125S does not support RvTMII
(Reverse TMII) mode."
• Table 33: “Signal Descriptions,” on page 131: corrected the typo of the
FCS_B signal name.
• Table 286: “Absolute Maximum Ratings,” on page 293: changed VESD
Maximum value to 1800V.
Added:
• “BroadSync HD Egress Time Stamp Status Registers (Page 90h:
Address D0h)” on page 283
• “BroadSync HD Link Status Register (Page 90h: Address E0h–E1h)” on
page 284
• Figure 63: “MDC/MDIO Timing (Master Mode),” on page 309
© 2016 by Broadcom. All rights reserved.
Broadcom®, the pulse logo, Connecting everything®, the Connecting everything logo, Avago Technologies,
BroadSync® HD, CableChecker™, Ethernet@Wirespeed™, and RoboSwitch™ are among the trademarks of
Broadcom and/or its affiliates in the United States, certain other countries and/or the EU. Any other trademarks
or trade names mentioned are the property of their respective owners.
Broadcom reserves the right to make changes without further notice to any products or data herein to improve
reliability, function, or design.
Information furnished by Broadcom is believed to be accurate and reliable. However, Broadcom does not
assume any liability arising out of the application or use of this information, nor the application or use of any
product or circuit described herein, neither does it convey any license under its patent rights nor the rights of
others.
This data sheet (including, without limitation, the Broadcom component(s) identified herein) is not designed,
intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations,
pollution control, hazardous substances management, or other high-risk application. BROADCOM
PROVIDES THIS DATA SHEET “AS-IS,” WITHOUT WARRANTY OF ANY KIND. BROADCOM DISCLAIMS
ALL WARRANTIES, EXPRESSED AND IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT.
BCM53125S Data Sheet
Date
Change Description
Updated:
• “Multicast Addresses” on page 63
• “Address Aging” on page 66
• Figure 45: “Write Access to the Register Set Using the Pseudo-PHY
(PHYAD = 11110) MDC/MDIO Path,” on page 122
• Figure 50: “Internal Digital Regulator Controller,” on page 129
• Table 33: “Signal Descriptions,” on page 131
• “MLF IPMC Forward Map Register (Page 00h: Address 36h–37h)” on
page 162
• “Software Reset Control Register (Page 00h: Address 79h)” on page 166
• “VLAN Table Entry Register (Page 05h: Address 83h–86h)” on page 198
• “PHY Identifier Register (Page 10h–14h: Address 04h)” on page 205
• “Port Receive Rate Control Register (Page 41h: Address 10h)” on
page 264
• “Port Egress Rate Control Configuration Register (Page 41h: Address
80h–91h)” on page 267
• Table 287: “Recommended Operating Conditions,” on page 294
• Table 299: “RGMII Output Timing (Normal Mode),” on page 302
• Table 300: “RGMII Output Timing (Delayed Mode),” on page 303
• Table 304: “GMII Input Timing,” on page 307
• Table 306: “MDC/MDIO Timing (Master Mode),” on page 309
• “SPI Timings” on page 311
Removed:
• Figure “SPI Timings, SS Asserted During SCK Low”
Added
• Table 286: “Internal Voltage Regulator Electrical Characteristics,” on
page 291
• Figure 67: “186-Pin Package (1 of 3) - Top View,” on page 312
• Figure 68: “186-Pin Package (2 of 3) - SectionC-C,” on page 313
• Figure 69: “186-Pin Package (3 of 3) - Bottom View,” on page 314
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Revision
Revision History
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09/20/10
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53125S-DS03-R
Broadcom®
March 11, 2016 • 53125S-DS06-R
BROADCOM CONFIDENTIAL
Page 4
BCM53125S Data Sheet
Revision
Revision History
Date
Change Description
53125S-DS03-R
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(continued)
Updated:
• Features on page 2
• “Deep Green Mode” on page 64
• Table 30: “20 LED Display Mode (GMII_LED_SEL=1),” on page 120
• Table 31: “10 LED Display Mode (GMII_LED_SEL=0),” on page 120
• Table 32: “Dual Input Configuration/LED Output Function,” on page 123
• “Internal Digital Regulator Controller” on page 124
• Figure 50: “Internal Digital Regulator Controller,” on page 125
• Table 34: “Signal Descriptions,” on page 127
• “LED Interfaces” on page 119
• “Pin List by Pin Number” on page 138
• “Pin List by Signal Name” on page 141
• Table 85: “Broadcom Tag Control Register (Page 02h: Address 03h),” on
page 171
• Table 96: “Egress Mirror MAC Address Register (Page 02h: Address
40h),” on page 176
• Table 87: “Aging Time Control Register (Page 02h: Address 06h–09h),”
on page 172
• Table 200: “Default IEEE 802.1Q Tag Register (Page 34h: Address 10h–
21h),” on page 252
• “Absolute Maximum Ratings” on page 289
• “Recommended Operating Conditions” on page 289
• “Electrical Characteristics” on page 290
• Table 285: “Electrical Characteristics,” on page 290
• Section 10: “Thermal Characteristics,” on page 309
• Figure 67: “186-Pin Package (1 of 3) - Top View,” on page 312
• Figure 51: “Reset and Clock Timing,” on page 292
• “BCM53125MKMML 2-Layer PCB Package Without a Heat Sink” on
page 310
• “BCM53125MKMML 2-Layer PCB Package With a Heat Sink” on
page 309
• “BCM53125MKMML 4-Layer PCB Package Without a Heat Sink” on
page 311
Broadcom®
March 11, 2016 • 53125S-DS06-R
BROADCOM CONFIDENTIAL
Page 5
BCM53125S Data Sheet
Revision
Revision History
Date
Change Description
53125S-DS03-R
Removed:
• Table 238: Loop Detection Control Register (Page 72h)
• Table 239: Loop Detection Control Registers (Page 72h: Address 00h01h)
• Table 239: Loop Detection Control Registers (Page 72h: Address 00h01h)
• Table 240: Discovery Frame Timer Control Registers (Page 72h:
Address 02h)
• Table 241: LED Warning Port Map registers (Page 72h: Address 03h04h)
• Table 242: Module ID 0 Registers (Page 72h: Address 05h-0Ah)
• Table 243: Module ID 1 Registers (Page 72h: Address 0Bh-10h)
• Table 244: Loop Detect Source Address Registers (Page 72h: Address
11h-16h)
• Figure 67: 186-Pin Package
• Figure 68: BCM53125S Pin Number Orientation
Added:
• Table 65: “RGMII Timing Delay Register for IMP Port (Page 00h:
Address 60h),” on page 162
• Table 66: “RGMII Timing Delay Register for Port 5 (Page 00h, Address
65h),” on page 163
• Note after Table 284: “Recommended Operating Conditions,” on
page 289
05/18/10
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53125S-DS02-R
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(continued)
Broadcom®
March 11, 2016 • 53125S-DS06-R
BROADCOM CONFIDENTIAL
Page 6
BCM53125S Data Sheet
Revision
Revision History
Date
Change Description
Updated:
• Figure 1: “Functional Block Diagram,” on page 2
• “Double Tagging” on page 39
• “WAN Port” on page 43
• “Ingress Rate Control” on page 44
• “Reserved Multicast Addresses” on page 60
• “LED Interfaces” on page 119
• Table 85: “Broadcom Tag Control Register (Page 02h: Address 03h),” on
page 171
• Default values in Table 130: “MII Control Register (Page 10h–14h:
Address 00h–01h),” on page 199, Table 134: “Auto-Negotiation
Advertisement Register (Page 10h–14h: Address 08h–09h),” on
page 201, Table 139: “1000BASE-T Control Register (Page 10h–14h:
Address 12h–13h),” on page 205, Table 213: “Global Rate Control
Register (Page 41h: Address 00h–03h),” on page 259, Table 215: “Port
Rate Control Register (Page 41h: Address 10h–33h),” on page 261
• Table 259: “EEE Enable Control Register (Page 92h: Address 00h),” on
page 281
• Table 260: “EEE LPI Assert Register (Page 92h: Address 02h),” on
page 282
• Table 261: “EEE LPI Indicate Register (Page 92h: Address 04h),” on
page 282
• Table 262: “EEE RX Idle Symbol Register (Page 92h: Address 06h),” on
page 283
• Table 263: “EEE Pipeline Timer Register (Page 92h: Address 0Ch),” on
page 283
• Table 277: “EEE TXQ Congestion Threshold Register (Page 92h:
Address C6h),” on page 286
• Table 278: “EEE TXQ Congestion Threshold Register (Page 92h:
Address C6h–D1h),” on page 287
• IDD in Table 285: “Electrical Characteristics,” on page 290
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53125S-DS02-R
(continued)
Broadcom®
March 11, 2016 • 53125S-DS06-R
Removed:
• Table 151: “Expansion Register Access Register (Page 10h–14h:
Address 2Eh–2Fh)”
• Table 152: “Expansion Register Select Values”
• “Expansion Registers”
BROADCOM CONFIDENTIAL
Page 7
BCM53125S Data Sheet
Revision History
Date
Change Description
53125S-DS01-R
01/13/10
53125S-DS00-R
11/16/09
Updated:
• “TMII (TURBO MII) and RvTMII (Reverse TMII) Interface” on page 57:
TMII SPEED setting register.
• “SCK: Serial Clock” on page 60: Maximum operating frequency.
• “Internal Digital Regulator Controller” on page 89: Voltage values.
• Table 27, ”Dual Input Configuration/LED Output Function,” on page 88:
LED[1] input pins.
• Table 29, ”Signal Descriptions,” on page 92: IMP_TXCLK, SCK/SK,
LED1 LED5, LED6 definitions.
• Table 291, ”Electrical Characteristics,” on page 245: IDD conditions and
input and output voltages.
• Table 292, ”Reset and Clock Timing,” on page 246: RESET rise time
maximum.
• Table 310, ”SPI Timings,” on page 259: SCK clock period and SCK high/
low time values.
• Figure 67, ”BCM53125S Pin Number Orientation,” on page 263: Ring
labels.
Initial release
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Revision
Broadcom®
March 11, 2016 • 53125S-DS06-R
BROADCOM CONFIDENTIAL
Page 8
BCM53125S Data Sheet
Table of Contents
Table of Contents
About This Document ................................................................................................................................ 31
Purpose and Audience .......................................................................................................................... 31
Acronyms and Abbreviations................................................................................................................. 31
Notational Conventions ......................................................................................................................... 31
Document Conventions ......................................................................................................................... 32
References ............................................................................................................................................ 32
Technical Support ...................................................................................................................................... 32
Section 1: Introduction ..................................................................................................... 33
Overview...................................................................................................................................................... 33
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Section 2: Features and Operation .................................................................................. 34
Overview...................................................................................................................................................... 34
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Quality of Service ....................................................................................................................................... 35
Egress Transmit Queues....................................................................................................................... 36
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Port-Based QoS .................................................................................................................................... 37
IEEE 802.1p QoS .................................................................................................................................. 37
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MACDA-Based QoS.............................................................................................................................. 37
ToS/DSCP QoS..................................................................................................................................... 38
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TC Decision Tree .................................................................................................................................. 38
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Non-BroadSync HD Frame ............................................................................................................ 38
BroadSync HD Frame .................................................................................................................... 38
Queuing Class (COS) Determination .................................................................................................... 39
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Port-Based VLAN........................................................................................................................................ 40
IEEE 802.1Q VLAN...................................................................................................................................... 40
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IEEE 802.1Q VLAN Table Organization................................................................................................ 40
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Double Tagging .......................................................................................................................................... 41
ISP Port ................................................................................................................................................. 42
Customer Port ....................................................................................................................................... 42
Uplink Traffic (from Customer Port to ISP)..................................................................................... 43
Downlink Traffic (from ISP to Customer Port) ................................................................................ 43
Jumbo Frame Support ............................................................................................................................... 44
Port Trunking/Aggregation........................................................................................................................ 44
WAN Port..................................................................................................................................................... 45
Rate Control ................................................................................................................................................ 46
Ingress Rate Control ............................................................................................................................. 46
Two-Bucket System .............................................................................................................................. 46
Egress Rate Control .............................................................................................................................. 47
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Table of Contents
Bucket Bit Rate...................................................................................................................................... 47
IMP Port Egress Rate Control ............................................................................................................... 47
Protected Ports........................................................................................................................................... 48
Port Mirroring.............................................................................................................................................. 48
Enabling Port Mirroring.......................................................................................................................... 48
Capture Port .......................................................................................................................................... 49
Mirror Filtering Rules ............................................................................................................................. 49
Port Mask Filter .............................................................................................................................. 49
Packet Address Filter ..................................................................................................................... 49
Packet Divider Filter ....................................................................................................................... 49
IGMP Snooping........................................................................................................................................... 50
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MLD Snooping ............................................................................................................................................ 50
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IEEE 802.1x Port-Based Security .............................................................................................................. 50
DoS Attack Prevention............................................................................................................................... 51
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MSTP Multiple Spanning Tree ................................................................................................................... 52
Software Reset............................................................................................................................................ 52
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BroadSync™ HD ......................................................................................................................................... 52
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Time Base and Slot Generation ............................................................................................................ 52
Transmission Shaping and Scheduling ................................................................................................. 53
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BroadSync HD Class5 Media Traffic.............................................................................................. 54
BroadSync HD Class4 Media Traffic.............................................................................................. 54
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CableChecker™ ........................................................................................................................................... 55
Egress PCP Remarking.............................................................................................................................. 57
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Address Management ................................................................................................................................ 57
Address Table Organization.................................................................................................................. 57
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Address Learning .................................................................................................................................. 58
Address Resolution and Frame Forwarding.......................................................................................... 59
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Unicast Addresses ......................................................................................................................... 59
Multicast Addresses ....................................................................................................................... 60
Reserved Multicast Addresses....................................................................................................... 61
Static Address Entries ........................................................................................................................... 62
Accessing the ARL Table Entries.......................................................................................................... 62
Searching the ARL Table ............................................................................................................... 63
Address Aging ....................................................................................................................................... 63
Normal Aging ................................................................................................................................. 63
Fast Aging ...................................................................................................................................... 63
Power Savings Modes................................................................................................................................ 64
Auto Power-Down Mode ....................................................................................................................... 64
Energy Efficient Ethernet Mode............................................................................................................. 65
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Table of Contents
Short Cable Mode (Green Mode) .......................................................................................................... 65
Deep Green Mode................................................................................................................................. 66
Interrupt....................................................................................................................................................... 66
Section 3: System Functional Blocks.............................................................................. 67
Overview...................................................................................................................................................... 67
Media Access Controller............................................................................................................................ 67
Receive Function................................................................................................................................... 67
Transmit Function.................................................................................................................................. 68
Flow Control .......................................................................................................................................... 68
10/100 Mbps Half-Duplex............................................................................................................... 68
10/100/1000 Mbps Full-Duplex ...................................................................................................... 68
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Integrated 10/100/1000 PHY....................................................................................................................... 69
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Encoder ................................................................................................................................................. 69
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Decoder................................................................................................................................................. 70
Link Monitor........................................................................................................................................... 70
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Digital Adaptive Equalizer ..................................................................................................................... 71
Echo Canceler....................................................................................................................................... 71
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Cross Talk Canceler.............................................................................................................................. 71
Analog-to-Digital Converter ................................................................................................................... 71
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Clock Recovery/Generator .................................................................................................................... 72
Baseline Wander Correction ................................................................................................................. 72
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Multimode TX Digital-to-Analog Converter............................................................................................ 72
Stream Cipher ....................................................................................................................................... 72
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Wire Map and Pair Skew Correction ..................................................................................................... 73
Automatic MDI Crossover ..................................................................................................................... 73
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10BASE-T/100BASE-TX Forced Mode Auto-MDIX .............................................................................. 74
Resetting the PHY................................................................................................................................. 74
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PHY Address......................................................................................................................................... 75
Super Isolate Mode ............................................................................................................................... 75
Standby Power-Down Mode.................................................................................................................. 75
Auto Power-Down Mode ....................................................................................................................... 75
External Loopback Mode....................................................................................................................... 76
Full-Duplex Mode .................................................................................................................................. 77
Copper Mode ................................................................................................................................. 77
Master/Slave Configuration ................................................................................................................... 77
Next Page Exchange............................................................................................................................. 78
Frame Management.................................................................................................................................... 78
In-Band Management Port .................................................................................................................... 78
Broadcom Tag Format for Egress Packet Transfer............................................................................... 80
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Table of Contents
Broadcom Tag Format for Ingress Packet Transfer .............................................................................. 81
MIB Engine .................................................................................................................................................. 82
MIB Counters Per Port .......................................................................................................................... 82
Integrated High-Performance Memory ..................................................................................................... 89
Switch Controller........................................................................................................................................ 89
Buffer Management............................................................................................................................... 89
Memory Arbitration ................................................................................................................................ 89
Transmit Output Port Queues ............................................................................................................... 90
Section 4: System Interfaces............................................................................................ 91
Overview...................................................................................................................................................... 91
Copper Interface ......................................................................................................................................... 91
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Auto-Negotiation.................................................................................................................................... 91
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Lineside (Remote) Loopback Mode ...................................................................................................... 92
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Frame Management Port Interface............................................................................................................ 92
MII Interface .......................................................................................................................................... 92
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TMII (TURBO MII) and RvTMII (Reverse TMII) Interface...................................................................... 92
Reverse MII Interface (RvMII) ............................................................................................................... 92
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GMII Interface........................................................................................................................................ 93
RGMII Interface ..................................................................................................................................... 93
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WAN Interface ............................................................................................................................................. 94
Configuration Pins ..................................................................................................................................... 94
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Programming Interfaces ............................................................................................................................ 94
SPI-Compatible Programming Interface................................................................................................ 94
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SS: Slave Select ............................................................................................................................ 95
SCK: Serial Clock........................................................................................................................... 95
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MOSI: Master Output Slave Input .................................................................................................. 95
MISO: Master Input Slave Output .................................................................................................. 95
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Without External PHY .................................................................................................................... 97
External PHY Registers ................................................................................................................. 97
Reading and Writing BCM53125S Registers Using SPI ................................................................ 98
Normal Read Operation ................................................................................................................. 99
Fast Read Operation.................................................................................................................... 103
Normal Write Operation ............................................................................................................... 106
EEPROM Interface.............................................................................................................................. 109
EEPROM Format ......................................................................................................................... 109
Serial Flash Interface .......................................................................................................................... 111
MDC/MDIO Interface........................................................................................................................... 111
MDC/MDIO Interface Register Programming...................................................................................... 111
Pseudo-PHY........................................................................................................................................ 112
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Table of Contents
LED Interfaces .......................................................................................................................................... 117
Dual-Input Configuration/LED Output Function................................................................................... 121
Internal Digital Regulator Controller....................................................................................................... 123
Section 5: Hardware Signal Definition Table ................................................................ 124
I/O Signal Types........................................................................................................................................ 124
Signal Descriptions .................................................................................................................................. 125
Section 6: Pin Assignment ............................................................................................. 136
Pin List by Pin Number ............................................................................................................................ 136
Pin List by Signal Name........................................................................................................................... 139
Section 7: Register Definitions ...................................................................................... 142
Register Definition.................................................................................................................................... 142
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Register Notations.................................................................................................................................... 142
Global Page Register ............................................................................................................................... 142
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Page 00h: Control Registers ................................................................................................................... 144
Port Traffic Control Register (Page 00h: Address 00h)....................................................................... 145
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IMP Port Control Register (Page 00h: Address 08h) .......................................................................... 146
Switch Mode Register (Page 00h: Address 0Bh) ................................................................................ 147
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IMP Port State Override Register (Page 00h: Address 0Eh) .............................................................. 147
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LED Control Register (Page 00h: Address 0Fh–1Bh)......................................................................... 148
LED Refresh Register (Page 00h: Address 0Fh) ................................................................................ 148
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LED Function 0 Control Register (Page 00h: Address 10h)................................................................ 149
LED Function 1 Control Register (Page 00h: Address 12h)................................................................ 150
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LED Function Map Register (Page 00h: Address 14h–15h) ............................................................... 150
LED Enable Map Register (Page 00h: Address 16h–17h).................................................................. 150
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LED Mode Map 0 Register (Page 00h: Address 18h–19h) ................................................................. 151
LED Mode Map 1 Register (Page 00h: Address 1Ah–1Bh) ................................................................ 151
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Port Forward Control Register (Page 00h: Address 21h).................................................................... 152
Protected Port Selection Register (Page 00h: Address 24h–25h) ...................................................... 153
WAN Port Select Register (Page 00h: Address 26h–27h) .................................................................. 153
Pause Capability Register (Page 00h: Address 28h–2Bh).................................................................. 153
Reserved Multicast Control Register (Page 00h: Address 2Fh).......................................................... 154
Unicast Lookup Failed Forward Map Register (Page 00h: Address 32h) ........................................... 155
Multicast Lookup Failed Forward Map Register (Page 00h: Address 34h–35h) ................................. 156
MLF IPMC Forward Map Register (Page 00h: Address 36h–37h)...................................................... 156
Pause Pass Through for RX Register (Page 00h: Address 38h–39h) ................................................ 157
Pause Pass Through for TX Register (Page 00h: Address 3Ah–3Bh)................................................ 157
Disable Learning Register (Page 00h: Address 3Ch–3Dh)................................................................. 157
Software Learning Register (Page 00h: Address 3Eh–3Fh) ............................................................... 158
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Table of Contents
Port State Override Register (Page 00h: Address 58h) ...................................................................... 158
RGMII Timing Delay Register for IMP Port (Page 00h: Address 60h) ................................................ 159
RGMII Timing Delay Register for Port 5 (Page 00h, Address 65h)..................................................... 160
MDIO WAN Port Address Register (Page 00h: Address 75h) ............................................................ 160
MDIO IMP PORT Address Register (Page 00h: Address 78h) ........................................................... 160
Software Reset Control Register (Page 00h: Address 79h)................................................................ 160
Pause Frame Detection Control Register (Page 00h: Address 80h)................................................... 161
Fast-Aging Control Register (Page 00h: Address 88h) ....................................................................... 161
Fast-Aging Port Control Register (Page 00h: Address 89h) ............................................................... 161
Fast-Aging VID Control Register (Page 00h: Address 8Ah–8Bh) ....................................................... 161
Page 01h: Status Registers ..................................................................................................................... 163
l
Link Status Summary (Page 01h: Address 00h) ................................................................................. 163
tia
Link Status Change (Page 01h: Address 02h) .................................................................................... 164
Port Speed Summary (Page 01h: Address 04h) ................................................................................. 164
en
Duplex Status Summary (Page 01h: Address 08h)............................................................................. 164
fid
Pause Status Summary (Page 01h: Address 0Ah) ............................................................................. 165
Source Address Change Register (Page 01h: Address 0Eh) ............................................................. 165
on
Last Source Address Register (Page 01h: Address 10h).................................................................... 166
Page 02h: Management/Mirroring Registers ......................................................................................... 167
C
Global Management Configuration Register (Page 02h: Address 00h) .............................................. 168
Broadcom Header Control Register (Page 02h: Address 03h) ........................................................... 168
om
RMON MIB Steering Register (Page 02h: Address 04h) .................................................................... 169
Aging Time Control Register (Page 02h: Address 06h) ...................................................................... 169
dc
Mirror Capture Control Register (Page 02h: Address 10h) ................................................................. 169
Ingress Mirror Control Register (Page 02h: Address 12h) .................................................................. 170
oa
Ingress Mirror Divider Register (Page 02h: Address 14h)................................................................... 171
Ingress Mirror MAC Address Register (Page 02h: Address 16h)........................................................ 171
Br
Egress Mirror Control Register (Page 02h: Address 1Ch) .................................................................. 172
Egress Mirror Divider Register (Page 02h: Address 1Eh)................................................................... 173
Egress Mirror MAC Address Register (Page 02h: Address 20h) ........................................................ 173
Device ID Register (Page 02h: Address 30h–33h) ............................................................................. 173
Revision Number Register (Page 02h: Address 40h) ......................................................................... 173
High-Level Protocol Control Register (Page 02h: Address 50h–53h) ................................................. 174
Page 03h: Interrupt Control Register...................................................................................................... 176
Page 04h: ARL Control Register ............................................................................................................. 178
Global ARL Configuration Register (Page 04h: Address 00h) ............................................................ 179
BPDU Multicast Address Register (Page 04h: Address 04h).............................................................. 179
Multiport Control Register (Page 04h: Address 0Eh–0Fh) .................................................................. 179
Multiport Address N (N=0–5) Register (Page 04h: Address 10h) ....................................................... 181
Broadcom®
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BCM53125S Data Sheet
Table of Contents
Multiport Vector N (N=0–5) Register (Page 04h: Address 18h) .......................................................... 182
Page 05h: ARL/VTBL Access Registers................................................................................................. 182
ARL Table Read/Write Control Register (Page 05h: Address 00h) .................................................... 184
MAC Address Index Register (Page 05h: Address 02h) ..................................................................... 184
VLAN ID Index Register (Page 05h: Address 08h) ............................................................................. 185
ARL Table MAC/VID Entry N (N=0-3) Register (Page 05h: Address 10h).......................................... 185
ARL Table Data Entry N (N=0-3) Register (Page 05h: Address 18h) ................................................. 186
ARL Table Search Control Register (Page 05h: Address 50h) ........................................................... 187
ARL Search Address Register (Page 05h: Address 51h) ................................................................... 188
ARL Table Search MAC/VID Result N (N=0-1) Register (Page 05h: Address 60h) ........................... 188
ARL Table Search Data Result N (N=0-1) Register (Page 05h: Address 68h)................................... 189
l
VLAN Table Read/Write/Clear Control Register (Page 05h: Address 80h) ........................................ 190
tia
VLAN Table Address Index Register (Page 05h: Address 81h).......................................................... 191
VLAN Table Entry Register (Page 05h: Address 83h–86h) ................................................................ 191
en
Internal Regulator Control Register (Page 0Fh: Address 12h)............................................................ 192
fid
Page 10h–14h: Internal GPHY MII Registers.......................................................................................... 193
MII Control Register (Page 10h–14h: Address 00h–01h) ................................................................... 195
on
MII Status Register (Page 10h–14h: Address 02h)............................................................................. 196
PHY Identifier Register (Page 10h–14h: Address 04h)....................................................................... 196
C
Auto-Negotiation Advertisement Register (Page 10h–14h: Address 08h) .......................................... 197
Auto-Negotiation Link Partner Ability Register (Page 10h–14h: Address 0Ah)................................... 198
om
Next Page .................................................................................................................................... 199
Acknowledge................................................................................................................................ 199
dc
Auto-Negotiation Expansion Register (Page 10h–14h: Address 0Ch)................................................ 199
Next Page Transmit Register (Page 10h–14h: Address 0Eh)............................................................. 200
oa
Link Partner Received Next Page Register (Page 10h–14h: Address 10h)........................................ 200
1000BASE-T Control Register (Page 10h–14h: Address 12h) ........................................................... 201
Br
Test Mode .................................................................................................................................... 202
Master/Slave Configuration Enable.............................................................................................. 202
1000BASE-T Status Register (Page 10h–14h: Address 14h)............................................................. 202
IEEE Extended Status Register (Page 10h–14h: Address 1Eh) ......................................................... 203
PHY Extended Control Register (Page 10h–14h: Address 20h)......................................................... 204
PHY Extended Status Register (Page 10h–14h: Address 22h) .......................................................... 205
Receive Error Counter Register (Page 10h–14h: Address 24h) ......................................................... 206
Copper Receive Error Counter..................................................................................................... 206
False Carrier Sense Counter Register (Page 10h–14h: Address 26h) ............................................... 206
Copper False Carrier Sense Counter........................................................................................... 206
10BASE-T/100BASE-TX/1000BASE-T Packets Received with Transmit Error Codes Counter......... 206
Packets Received with Transmit Error Codes Counter................................................................ 207
Broadcom®
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BCM53125S Data Sheet
Table of Contents
Receiver NOT_OK Counter Register (Page 10h–14h: Address 28h) ................................................. 207
Copper Local Receiver NOT_OK Counter ................................................................................... 207
Copper Remote Receiver NOT_OK Counter ............................................................................... 207
Receive CRC Counter Register (Page 10h–14h: Address 28h) ......................................................... 207
Copper CRC Counter................................................................................................................... 207
Auxiliary Control Shadow Value Access Register (Page 10h–14h: Address 30h) .............................. 208
External Loopback ....................................................................................................................... 209
Receive Extended Packet Length ................................................................................................ 209
Edge Rate Control (1000BASE-T) ............................................................................................... 209
Edge Rate Control (100BASE-TX)............................................................................................... 209
Shadow Register Select............................................................................................................... 210
l
10BASE-T Register ............................................................................................................................. 210
tia
Power/MII Control Register (Page 10h–14h: Address 30h) ................................................................ 211
Super Isolate (Copper Only) ........................................................................................................ 211
en
Shadow Register Select............................................................................................................... 211
fid
Miscellaneous Test Register (Page 10h–14h: Address 30h) .............................................................. 211
Miscellaneous Control Register (Page 10h–14h: Address 30h).......................................................... 212
on
Auxiliary Status Summary Register (Page 10h–14h: Address 32h).................................................... 213
Interrupt Status Register (Page 10h–14h: Address 34h) .................................................................... 214
C
10BASE-T/100BASE-TX/1000BASE-T Register 38h Access ............................................................. 215
Spare Control 2 Register (Page 10h–14h: Address 38h).................................................................... 216
om
Auto Power-Down Register (Page 10h–14h: Address 38h) ................................................................ 216
LED Selector 2 Register (Page 10h–14h: Address 38h)..................................................................... 217
dc
Mode Control Register (Page 10h–14h: Address 38h) ....................................................................... 219
Master/Slave Seed Register (Page 10h–14h: Address 3Ah) .............................................................. 219
oa
HCD Status Register (Page 10h–14h: Address 3Ah).......................................................................... 220
Test Register 1 (Page 10h–14h: Address 3Ch) .................................................................................. 222
Br
Block Address Number (Page 010h–017h: Address 03Eh) ................................................................ 222
Page 20h–28h: Port MIB Registers ......................................................................................................... 223
Page 30h: QoS Registers......................................................................................................................... 227
QoS Global Control Register (Page 30h: Address 00h)...................................................................... 228
QoS IEEE 802.1p Enable Register (Page 30h: Address 04h) ............................................................ 229
QoS DiffServ Enable Register (Page 30h: Address 06h).................................................................... 229
Port N (N=0-5, 8) PCP_To_TC Register (Page 30h: Address 10h) .................................................... 229
DiffServ Priority Map 0 Register (Page 30h: Address 30h) ................................................................. 230
DiffServ Priority Map 1 Register (Page 30h: Address 36h) ................................................................. 231
DiffServ Priority Map 2 Register (Page 30h: Address 3Ch) ................................................................ 231
DiffServ Priority Map 3 Register (Page 30h: Address 42h) ................................................................. 232
TC_To_CoS Mapping Register (Page 30h: Address 62h–63h) .......................................................... 232
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BCM53125S Data Sheet
Table of Contents
CPU_To_CoS Map Register (Page 30h: Address 64h–67h) .............................................................. 233
TX Queue Control Register (Page 30h: Address 80h) ........................................................................ 234
TX Queue Weight Register (Page 30h: Address 81h) ........................................................................ 234
Page 31h: Port-Based VLAN Registers .................................................................................................. 235
Port-Based VLAN Control Register (Page 31h: Address 00h) ............................................................ 235
Page 32h: Trunking Registers................................................................................................................. 236
MAC Trunking Control Register (Page 32h: Address 00h) ................................................................. 236
Trunking Group 0 Register (Page 32h: Address 10h) ......................................................................... 236
Trunking Group 1 Register (Page 32h: Address 12h) ......................................................................... 237
Page 34h: IEEE 802.1Q VLAN Registers ................................................................................................ 237
Global IEEE 802.1Q Register (Pages 34h: Address 00h)................................................................... 238
l
Global IEEE 802.1Q VLAN Control 1 Register (Page 34h: Address 01h)........................................... 239
tia
Global VLAN Control 2 Register (Page 34h: Address 02h)................................................................. 240
Global VLAN Control 3 Register (Page 34h: Address 03h)................................................................. 240
en
Global VLAN Control 4 Register (Page 34h: Address 05h)................................................................. 241
fid
Global VLAN Control 5 Register (Page 34h: Address 06h)................................................................. 242
VLAN Multiport Address Control Register (Page 34h: Address 0Ah–0Bh) ......................................... 242
on
Default IEEE 802.1Q Tag Register (Page 34h: Address 10h) ............................................................ 244
Double Tagging TPID Register (Page 34h: Address 30h–31h) .......................................................... 244
C
ISP Port Selection Portmap Register (Page 34h: Address 32h–33h) ................................................. 245
Page 36h: DoS Prevent Register............................................................................................................. 246
om
DoS Control Register (Page 36h: Address 00h–03h) ......................................................................... 246
Minimum TCP Header Size Register (Page 36h: Address 04h) ......................................................... 248
dc
Maximum ICMPv4 Size Register (Page 36h: Address 08h–0Bh) ....................................................... 248
Maximum ICMPv6 Size Register (Page 36h: Address 0Ch–0Fh)....................................................... 248
oa
DoS Disable Learn Register (Page 36h: Address 10h)....................................................................... 248
Page 40h: Jumbo Frame Control Register............................................................................................. 249
Br
Jumbo Frame Port Mask Register (Page 40h: Address 01h).............................................................. 249
Standard Max Frame Size Register (Page 40h: Address 05h) ........................................................... 250
Page 41h: Broadcast Storm Suppression Register .............................................................................. 250
Ingress Rate Control Configuration Register (Page 41h: Address 00h).............................................. 251
Port Receive Rate Control Register (Page 41h: Address 10h) ........................................................... 253
Port Egress Rate Control Configuration Register (Page 41h: Address 80h–91h)............................... 256
IMP Port (IMP/Port 5) Egress Rate Control Configuration Register (Page 41h: Address C0h–C1h).. 256
Page 42h: EAP Register........................................................................................................................... 258
EAP Global Control Register (Page 42h: Address 00h)...................................................................... 258
EAP Multiport Address Control Register (Page 42h: Address 01h) .................................................... 259
EAP Destination IP Register 0 (Page 42h: Address 02h) ................................................................... 260
EAP Destination IP Register 1 (Page 42h: Address 0Ah) ................................................................... 260
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BCM53125S Data Sheet
Table of Contents
Port EAP Configuration Register (Page 42h: Address 20h)................................................................ 260
Page 43h: MSPT Register ........................................................................................................................ 261
MSPT Control Register (Page 43h: Address 00h) .............................................................................. 261
MSPT Aging Control Register (Page 43h: Address 02h) .................................................................... 262
MSPT Table Register (Page 43h: Address 10h) ................................................................................. 262
SPT Multiport Address Bypass Control Register (Page 43h: Address 50h–51h)................................ 263
Page 70h: MIB Snapshot Control Register ............................................................................................ 263
MIB Snapshot Control Register (Page 70h: Address 00h).................................................................. 264
Page 71h: Port Snapshot MIB Control Register .................................................................................... 264
Page 85h: WAN Interface (Port 5) External PHY MII Registers ............................................................ 264
Page 88h: IMP Port External PHY MII Registers Page Summary ......................................................... 265
l
Page 90h: BroadSync HD Register ......................................................................................................... 265
tia
BroadSync HD Enable Control Register (Page 90h: Address 00h–01h) ............................................ 266
BroadSync HD Time Stamp Report Control Register (Page 90h: Address 02h) ................................ 266
en
BroadSync HD PCP Value Control Register (page 90h: Address 03h) .............................................. 266
fid
BroadSync HD Max Packet Size Register (Page 90h: Address 04h) ................................................. 267
BroadSync HD Time Base Register (Page 90h: Address 10h–13h) ................................................... 267
on
BroadSync HD Time Base Adjustment Register (Page 90h: Address 14h–17) .................................. 267
BroadSync HD Slot Number and Tick Counter Register (Page 90h: Address 18h–1Bh) ................... 268
C
BroadSync HD Slot Adjustment Register (Page 90h: Address 1Ch–1Fh) .......................................... 268
BroadSync HD Class 5 Bandwidth Control Register (Page 90h: Address 30h).................................. 269
om
BroadSync HD Class 4 Bandwidth Control Register (Page 90h: Address 60h).................................. 270
BroadSync HD Egress Time Stamp Register (Page 90h: Address 90h)............................................. 270
dc
BroadSync HD Egress Time Stamp Status Register (Page 90h: Address AFh)................................. 271
BroadSync HD Link Status Register (Page 90h: Address B0h–B1h).................................................. 271
oa
BroadSync HD Egress Time Stamp Status Registers (Page 90h: Address D0h) ............................... 271
BroadSync HD Link Status Register (Page 90h: Address E0h–E1h).................................................. 272
Br
Page 91h: Traffic Remarking Register.................................................................................................... 272
Traffic Remarking Control Register (Page 91h: Address 00h) ............................................................ 272
Egress Packet TC to PCP Mapping Register (Page 91h: Address 10h)............................................. 273
Page 92h: EEE Control Registers ........................................................................................................... 274
Global Registers ....................................................................................................................................... 279
SPI Data I/O Register (Global, Address F0h)...................................................................................... 280
SPI Status Register (Global, Address FEh) ........................................................................................ 280
Page Register (Global, Address FFh) ................................................................................................. 280
Section 8: Electrical Characteristics ............................................................................. 281
Absolute Maximum Ratings .................................................................................................................... 281
Recommended Operating Conditions .................................................................................................... 281
Electrical Characteristics......................................................................................................................... 282
Broadcom®
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BCM53125S Data Sheet
Table of Contents
Section 9: Timing Characteristics.................................................................................. 284
Reset and Clock Timing........................................................................................................................... 284
MII/TMII Interface Timing.......................................................................................................................... 285
MII/TMII/TMII Input Timing .................................................................................................................. 285
MII/TMII Output Timing........................................................................................................................ 286
Reverse MII/TMII Interface Timing........................................................................................................... 287
Reverse MII/TMII Input Timing ............................................................................................................ 287
Reverse MII/TMII Output Timing ......................................................................................................... 288
RGMII Interface Timing ............................................................................................................................ 289
RGMII Output Timing (Normal Mode) ................................................................................................. 289
RGMII Output Timing (Delayed Mode)................................................................................................ 290
l
RGMII Input Timing (Normal Mode) .................................................................................................... 291
tia
RGMII Input Timing (Delayed Mode)................................................................................................... 292
en
GMII Interface Timing ............................................................................................................................... 293
GMII Interface Output Timing .............................................................................................................. 293
fid
GMII Interface Input Timing................................................................................................................. 293
MDC/MDIO Timing .................................................................................................................................... 295
on
Serial LED Interface Timing..................................................................................................................... 297
SPI Timings ............................................................................................................................................... 298
C
EEPROM Timing ....................................................................................................................................... 299
JTAG Interface .......................................................................................................................................... 300
om
Section 10: Thermal Characteristics ............................................................................. 301
BCM53125S 2-Layer PCB Package With a Heat Sink............................................................................ 301
dc
BCM53125S 2-Layer PCB Package Without a Heat Sink ...................................................................... 302
BCM53125S 4-Layer PCB Package Without a Heat Sink ...................................................................... 303
oa
Section 11: Mechanical Information .............................................................................. 304
Br
Section 12: Ordering Information .................................................................................. 307
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BCM53125S Data Sheet
List of Figures
List of Figures
Figure 1: Functional Block Diagram................................................................................................................... 2
Figure 2: QoS Program Flow ........................................................................................................................... 36
Figure 3: VLAN Table Organization ................................................................................................................. 41
Figure 4: ISP Tag Diagram .............................................................................................................................. 41
Figure 5: Trunking............................................................................................................................................ 44
Figure 6: WAN and LAN Domain Separation When WAN Port Is Selected .................................................... 45
Figure 7: Bucket Flow ...................................................................................................................................... 46
Figure 8: Mirror Filter Flow............................................................................................................................... 48
Figure 9: BroadSync HD Shaping and Scheduling .......................................................................................... 53
tia
l
Figure 10: Address Table Organization ........................................................................................................... 58
Figure 11: IMP Packet Encapsulation Format ................................................................................................. 79
en
Figure 12: TXQ and Buffer Tag Structure ........................................................................................................ 90
Figure 13: RvMII Port Connection.................................................................................................................... 93
fid
Figure 14: Normal SPI Command Byte............................................................................................................ 96
on
Figure 15: Fast SPI Command Byte ................................................................................................................ 96
Figure 16: SPI Serial Interface Write Operation............................................................................................... 97
C
Figure 17: SPI Serial Interface Read Operation .............................................................................................. 97
Figure 18: SPI Interface Without External PHY Device ................................................................................... 97
om
Figure 19: Accessing External PHY Registers................................................................................................. 98
Figure 20: Normal Read Operation................................................................................................................ 100
dc
Figure 21: Normal Read Mode to Check the SPIF Bit of SPI Status Register ............................................... 101
Figure 22: Normal Read Mode to Setup the Accessed Register Page Value................................................ 101
oa
Figure 23: Normal Read Mode to Setup the Accessed Register Address Value (Dummy Read) ................. 102
Br
Figure 24: Normal Read Mode to Check the SPI Status for Completion of Read ......................................... 102
Figure 25: Normal Read Mode to Obtain the Register Content ..................................................................... 103
Figure 26: Fast Read Operation .................................................................................................................... 104
Figure 27: Normal Read Mode to Check the SPIF Bit of SPI Status Register ............................................... 105
Figure 28: Fast Read Mode to Setup New Page Value ................................................................................. 105
Figure 29: Fast Read to Read the Register ................................................................................................... 106
Figure 30: Normal Write Operation ................................................................................................................ 107
Figure 31: Normal Read Mode to Check the SPIF Bit of SPI Status Register ............................................... 108
Figure 32: Normal Write to Setup the Register Page Value .......................................................................... 108
Figure 33: Normal Write to Write the Register Address Followed by Written Data........................................ 109
Figure 34: Serial EEPROM Connection......................................................................................................... 109
Figure 35: EEPROM Programming Example................................................................................................. 110
Broadcom®
March 11, 2016 • 53125S-DS06-R
BROADCOM CONFIDENTIAL
Page 20
BCM53125S Data Sheet
List of Figures
Figure 36: Pseudo-PHY MII Register Definitions ........................................................................................... 112
Figure 37: Pseudo-PHY MII Register 16: Register Set Access Control Bit Definition ................................... 113
Figure 38: Pseudo-PHY MII Register 17: Register Set Read/Write Control Bit Definition ............................. 113
Figure 39: Pseudo-PHY MII Register 18: Register Access Status Bit Definition ........................................... 113
Figure 40: Pseudo-PHY MII Register 24: Access Register Bit Definition ...................................................... 114
Figure 41: Pseudo-PHY MII Register 25: Access Register Bit Definition ...................................................... 114
Figure 42: Pseudo-PHY MII Register 26: Access Register Bit Definition ...................................................... 114
Figure 43: Pseudo-PHY MII Register 27: Access Register Bit Definition ...................................................... 114
Figure 44: Read Access to the Register Set Using the Pseudo-PHY (PHYAD = 11110) MDC/MDIO Path .. 115
Figure 45: Write Access to the Register Set Using the Pseudo-PHY (PHYAD = 11110) MDC/MDIO Path .. 116
Figure 46: LED Interface Register Structure Diagram ................................................................................... 119
tia
l
Figure 47: LED Interface Block Diagram ....................................................................................................... 120
Figure 48: Dual LED Usage Example ............................................................................................................ 121
en
Figure 49: Dual Input Configuration/LED Output Function ............................................................................ 122
Figure 50: Internal Digital Regulator Controller.............................................................................................. 123
fid
Figure 51: Reset and Clock Timing................................................................................................................ 284
on
Figure 52: MII Input Timing ............................................................................................................................ 285
Figure 53: MII Output Timing ......................................................................................................................... 286
C
Figure 54: Reverse MII Input Timing.............................................................................................................. 287
Figure 55: Reverse MII Output Timing ........................................................................................................... 288
om
Figure 56: RGMII Output Timing (Normal Mode) ........................................................................................... 289
Figure 57: RGMII Output Timing (Delayed Mode) ......................................................................................... 290
dc
Figure 58: RGMII Input Timing (Normal Mode).............................................................................................. 291
Figure 59: RGMII Input Timing (Delayed Mode) ............................................................................................ 292
oa
Figure 60: GMII Output Timing ...................................................................................................................... 293
Br
Figure 61: GMII Input Timing ......................................................................................................................... 293
Figure 62: MDC/MDIO Timing (Slave Mode) ................................................................................................. 295
Figure 63: MDC/MDIO Timing (Master Mode) ............................................................................................... 296
Figure 64: Serial LED Interface Timing.......................................................................................................... 297
Figure 65: SPI Timings, SS Asserted During SCK High ................................................................................ 298
Figure 66: EEPROM Timing .......................................................................................................................... 299
Figure 67: JTAG Interface.............................................................................................................................. 300
Figure 68: 186-Pin Package (1 of 3) - Top View............................................................................................ 304
Figure 69: 186-Pin Package (2 of 3) - SectionC-C ........................................................................................ 305
Figure 70: 186-Pin Package (3 of 3) - Bottom View....................................................................................... 306
Broadcom®
March 11, 2016 • 53125S-DS06-R
BROADCOM CONFIDENTIAL
Page 21
BCM53125S Data Sheet
List of Tables
List of Tables
Table 1: TC Decision Tree Summary............................................................................................................... 38
Table 2: Reasons to Forward a Packet to the CPU ......................................................................................... 39
Table 3: Bucket Bit Rate .................................................................................................................................. 47
Table 4: DoS Attacks Detected by BCM53125S.............................................................................................. 51
Table 5: Cable Diagnostic Output .................................................................................................................... 55
Table 6: Unicast Forward Field Definitions ...................................................................................................... 59
Table 7: Address Table Entry for Unicast Address .......................................................................................... 60
Table 8: Address Table Entry for Multicast Address ........................................................................................ 61
Table 9: Behavior for Reserved Multicast Addresses ...................................................................................... 61
tia
l
Table 10: Flow Control Modes ......................................................................................................................... 69
Table 11: 1000BASE-T External Loopback With External Loopback Plug ...................................................... 76
en
Table 12: 1000BASE-T External Loopback Without External Loopback Plug ................................................. 76
Table 13: 100BASE-TX External Loopback With External Loopback Plug...................................................... 76
fid
Table 14: 100BASE-TX External Loopback Without External Loopback Plug................................................. 76
on
Table 15: 10BASE-T External Loopback With External Loopback Plug .......................................................... 77
Table 16: 10BASE-T External Loopback Without External Loopback Plug ..................................................... 77
C
Table 17: Egress Broadcom Tag Format (IMP to CPU) .................................................................................. 80
Table 18: Ingress BRCM Tag (CPU to IMP) .................................................................................................... 81
om
Table 19: Receive-Only Counters (19) ............................................................................................................ 82
Table 20: Transmit-Only Counters (19) ........................................................................................................... 84
dc
Table 21: Transmit or Receive Counters (10) .................................................................................................. 85
Table 22: EEE Counters .................................................................................................................................. 85
oa
Table 23: Directly Supported MIB Counters .................................................................................................... 85
Table 24: Indirectly Supported MIB Counters .................................................................................................. 87
Br
Table 25: BCM53125S Supported MIB Extensions ......................................................................................... 88
Table 26: EEPROM Header Format .............................................................................................................. 110
Table 27: EEPROM Contents ........................................................................................................................ 110
Table 28: MII Management Frame Format .................................................................................................... 117
Table 29: 20 LED Display Mode (GMII_LED_SEL=1) ................................................................................... 118
Table 30: 10 LED Display Mode (GMII_LED_SEL=0) ................................................................................... 118
Table 31: Dual Input Configuration/LED Output Function.............................................................................. 121
Table 32: I/O Signal Type Definitions ............................................................................................................ 124
Table 33: Signal Descriptions ........................................................................................................................ 125
Table 34: Global Page Register Map ............................................................................................................. 142
Table 35: Control Registers (Page 00h) ........................................................................................................ 144
Broadcom®
March 11, 2016 • 53125S-DS06-R
BROADCOM CONFIDENTIAL
Page 22
BCM53125S Data Sheet
List of Tables
Table 36: Port Traffic Control Register Address Summary ............................................................................ 145
Table 37: Port Control Register (Page 00h: Address 00h–05h) .................................................................... 146
Table 38: IMP Port Control Register (Page 00h: Address 08h) ..................................................................... 146
Table 39: Switch Mode Register (Page 00h: Address 0Bh)........................................................................... 147
Table 40: IMP Port State Override Register (Page 00h: Address 0Eh) ......................................................... 147
Table 41: LED Control Register Address Summary ...................................................................................... 148
Table 42: LED Refresh Register (Page 00h: Address 0Fh) ........................................................................... 148
Table 43: LED Function 0 Control Register (Page 00h: Address 10h–11h) .................................................. 149
Table 44: LED Function 1 Control Register (Page 00h: Address 12h–13h) .................................................. 150
Table 45: LED Function Map Register (Page 00h: Address 14h–15h) .......................................................... 150
Table 46: LED Enable Map Register (Page 00h: Address 16h–17h) ............................................................ 150
tia
l
Table 47: LED Mode Map 0 Register (Page 00h: Address 18h–19h)............................................................ 151
Table 48: LED Function Map 1 Control Register (Page 00h: Address 1Ah–1Bh) ......................................... 151
en
Table 49: Port Forward Control Register (Page 00h: Address 21h) .............................................................. 152
Table 50: Protected Port Selection Register (Page 00h: Address 24h–25h) ................................................. 153
fid
Table 51: WAN Port Select Register (Page 00h: Address 26h–27h)............................................................. 153
on
Table 52: Pause Capability Register (Page 00h: Address 28h–2Bh) ............................................................ 153
Table 53: Reserved Multicast Control Register (Page 00h: Address 2Fh) .................................................... 154
C
Table 54: Unicast Lookup Failed Forward Map Register (Page 00h: Address 32h–33h) .............................. 155
Table 55: Multicast Lookup Failed Forward Map Register (Page 00h: Address 34h–35h)............................ 156
om
Table 56: MLF IMPC Forward Map Register (Page 00h: Address 36h–37h) ................................................ 156
Table 57: Pause Pass Through for RX Register (Page 00h: Address 38h–39h) ........................................... 157
dc
Table 58: Pause Pass Through for TX Register (Page 00h: Address 3Ah–3Bh) .......................................... 157
Table 59: Disable Learning Register (Page 00h: Address 3Ch–3Dh) ........................................................... 157
oa
Table 60: Software Learning Control Register (Page 00h: Address 3Eh–3Fh) ............................................. 158
Br
Table 61: Port State Override Register Address Summary ........................................................................... 158
Table 62: Port State Override Register (Page 00h: Address 58h–5Fh)......................................................... 158
Table 63: RGMII Timing Delay Register for IMP Port (Page 00h: Address 60h) ........................................... 159
Table 64: RGMII Timing Delay Register for Port 5 (Page 00h, Address 65h) ............................................... 160
Table 65: MDIO WAN Port Address Register (Page 00h: Address 75h) ....................................................... 160
Table 66: MDIO IMP PORT Address Register (Page 00h: Address 78h)...................................................... 160
Table 67: Software Reset Control Register (Page 00h: Address 79h) .......................................................... 160
Table 68: Pause Frame Detection Control Register (Page 00h: Address 80h) ............................................. 161
Table 69: Fast-Aging Control Register (Page 00h: Address 88h).................................................................. 161
Table 70: Fast-Aging Port Control Register (Page 00h: Address 89h) .......................................................... 161
Table 71: Fast-Aging VID Control Register (Page 00h: Address 8Ah–8Bh) .................................................. 161
Table 72: Status Registers (Page 01h) .......................................................................................................... 163
Broadcom®
March 11, 2016 • 53125S-DS06-R
BROADCOM CONFIDENTIAL
Page 23
BCM53125S Data Sheet
List of Tables
Table 73: Link Status Summary Register (Page 01h: Address 00h–01h) ..................................................... 163
Table 74: Link Status Change Register (Page 01h: Address 02h–03h) ........................................................ 164
Table 75: Port Speed Summary Register (Page 01h: Address 04h–07h) ..................................................... 164
Table 76: Duplex Status Summary Register (Page 01h: Address 08h–09h) ................................................. 164
Table 77: PAUSE Status Summary Register (Page 01h: Address 0Ah–0Dh) ............................................... 165
Table 78: Source Address Change Register (Page 01h: Address 0Eh–0Fh) ................................................ 165
Table 79: Last Source Address Register Address Summary......................................................................... 166
Table 80: Last Source Address (Page 01h: Address 10h–45h)..................................................................... 166
Table 81: Aging/Mirroring Registers (Page 02h)............................................................................................ 167
Table 82: Global Management Configuration Register (Page 02h: Address 00h) ......................................... 168
Table 83: Broadcom Tag Control Register (Page 02h: Address 03h) ........................................................... 168
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Table 84: RMON MIB Steering Register (Page 02h: Address 04h–05h)....................................................... 169
Table 85: Aging Time Control Register (Page 02h: Address 06h–09h) ......................................................... 169
en
Table 86: Mirror Capture Control Register (Page 02h: Address 10h–11h) .................................................... 169
Table 87: Ingress Mirror Control Register (Page 02h: Address 12h–13h) ..................................................... 170
fid
Table 88: Ingress Mirror Divider Register (Page 02h: Address 14h–15h) ..................................................... 171
on
Table 89: Ingress Mirror MAC Address Register (Page 02h: Address 16h–1Bh) .......................................... 171
Table 90: Egress Mirror Control Register (Page 02h: Address 1Ch–1Dh) .................................................... 172
C
Table 91: Egress Mirror Divider Register (Page 02h: Address 1Eh–1Fh) ..................................................... 173
Table 92: Egress Mirror MAC Address Register (Page 02h: Address 20h–25h) ........................................... 173
om
Table 93: Device ID Register (Page 02h: Address 30h–33h) ........................................................................ 173
Table 94: Egress Mirror MAC Address Register (Page 02h: Address 40h) ................................................... 173
dc
Table 95: High-Level Protocol Control Register (Page 02h: Address 50h–53h)............................................ 174
Table 96: Interrupt Status Register (Page 03H: Address 00h-03h) ............................................................... 176
oa
Table 97: Interrupt Enable Register (Page 03H: Address 08h-0Bh) .............................................................. 176
Br
Table 98: IMP Sleep Timer Register (Page 03H: Address 10h-11h) ............................................................. 176
Table 99: WAN Sleep Timer Register (Page 03H: Address 14h-15h) ........................................................... 177
Table 100: Sleep Status Register (Page 03H: Address 18h)......................................................................... 177
Table 101: ARL Control Registers (Page 04h) .............................................................................................. 178
Table 102: Global ARL Configuration Register (Page 04h: Address 00h) ..................................................... 179
Table 103: BPDU Multicast Address Register (Page 04h: Address 04h–09h) .............................................. 179
Table 104: Multiport Control Register (Page 04h: Address 0Eh–0Fh)........................................................... 179
Table 105: Multiport Address Register Address Summary ............................................................................ 181
Table 106: Multiport Address Register (Page 04h: Address 10h–17h, 20h–27h, 30h–37h, 40h–47h, 50h–57h,
60h–67h) ...................................................................................................................................... 181
Table 107: Multiport Vector Register Address Summary ............................................................................... 182
Table 108: Multiport Vector Register (Page 04h: Address 18h–1Bh, 28h–2Bh, 38h–3Bh, 48h–4Bh, 58h–5Bh,
Broadcom®
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BROADCOM CONFIDENTIAL
Page 24
BCM53125S Data Sheet
List of Tables
68h–6Bh) ...................................................................................................................................... 182
Table 109: ARL/VTBL Access Registers (Page 05h) .................................................................................... 182
Table 110: ARL Table Read/Write Control Register (Page 05h: Address 00h) ............................................. 184
Table 111: MAC Address Index Register (Page 05h: Address 02h–07h)...................................................... 184
Table 112: VLAN ID Index Register (Page 05h: Address 08h–09h) .............................................................. 185
Table 113: ARL Table MAC/VID Entry N (N=0-3) Register Address Summary............................................. 185
Table 114: ARL Table MAC/VID Entry N (N=0-3) Register (Page 05h: Address 10h–17h, 20h–27h, 30h–37h,
40h–47h) ...................................................................................................................................... 185
Table 115: ARL Table Data Entry N (N=0-3) Register Address Summary .................................................... 186
Table 116: ARL Table Data Entry N (N=0-3) Register (Page 05h: Address 18h–1Bh, 28h–2Bh, 38h–3Bh,
48h–4Bh) ...................................................................................................................................... 186
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Table 117: ARL Table Search Control Register (Page 05h: Address 50h).................................................... 187
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Table 118: ARL Search Address Register (Page 05h: Address 51h–52h) .................................................... 188
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Table 119: ARL Table Search MAC/VID Result N (N=0-1) Register Address Summary............................... 188
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Table 120: ARL Table Search MAC/VID Result N (N=0-1) Register (Page 05h: Address 60h–67h, 70h–77h) ..
188
Table 121: ARL Table Search Data Result N (N=0-1) Register Address Summary ...................................... 189
on
Table 122: ARL Table Search Data Result N (N=0-1) Register (Page 05h: Address 68h–6Bh, 78h–7Bh)... 189
Table 123: VLAN Table Read/Write/Clear Control Register (Page 05h: Address 80h) ................................. 190
C
Table 124: VLAN Table Address Index Register (Page 05h: Address 81h–82h) .......................................... 191
om
Table 125: VLAN Table Entry Register (Page 05h: Address 83h–86h) ......................................................... 191
Table 126: Internal Regulator Control Register (Page 0Fh: Address 12h) .................................................... 192
Table 127: 10/100/1000 PHY Page Summary............................................................................................... 193
dc
Table 128: Register Map (Page 10h–14h) ..................................................................................................... 193
oa
Table 129: MII Control Register (Page 10h–14h: Address 00h–01h) ............................................................ 195
Table 130: MII Status Register (Page 10h–14h: Address 02h–03h) ............................................................. 196
Br
Table 131: PHY Identifier Register MSB (Page 10h–14h: Address 04–07h)................................................. 196
Table 132: PHY Identifier Register LSB (Page 10h–14h: Address 06h–07h)................................................ 197
Table 133: Auto-Negotiation Advertisement Register (Page 10h–14h: Address 08h–09h) ........................... 197
Table 134: Auto-Negotiation Link Partner Ability Register (Page 10h–14h: Address 0Ah–0Bh) ................... 198
Table 135: Auto-Negotiation Expansion Register (Page 10h–14h: Address 0Ch–0Dh) ................................ 199
Table 136: Next Page Transmit Register (Page 10h–14h: Address 0Eh–0Fh) ............................................. 200
Table 137: Link Partner Received Next Page Register (Page 10h–14h: Address 10h–11h) ........................ 200
Table 138: 1000BASE-T Control Register (Page 10h–14h: Address 12h–13h) ............................................ 201
Table 139: 1000BASE-T Status Register (Page 10h–14h: Address 14h–15h) ............................................. 202
Table 140: IEEE Extended Status Register (Page 10h–14h: Address 1Eh–1Fh) ......................................... 203
Table 141: PHY Extended Control Register (Page 10h–14h: Address 20h–21h) ......................................... 204
Broadcom®
March 11, 2016 • 53125S-DS06-R
BROADCOM CONFIDENTIAL
Page 25
BCM53125S Data Sheet
List of Tables
Table 142: PHY Extended Status Register (Page 10h–14h: Address 22h–23h) ........................................... 205
Table 143: Receive Error Counter Register (Page 10h–14h: Address 24h–25h) .......................................... 206
Table 144: False Carrier Sense Counter Register (Page 10h–14h: Address 26h–27h) ................................ 206
Table 145: 10BASE-T/100BASE-TX/1000BASE-T Transmit Error Code Counter Register (Address 13h) .. 206
Table 146: Receiver NOT_OK Counter Register (Page 10h–14h: Address 28h–29h) .................................. 207
Table 147: CRC Counter Register (Page 10h–14h: Address 28h–29h) ........................................................ 207
Table 148: Auxiliary Control Shadow Values Access Register (Page 10h–14h: Address 30h) ..................... 208
Table 149: Reading Register 30h .................................................................................................................. 208
Table 150: Writing Register 30h .................................................................................................................... 208
Table 151: Auxiliary Control Register (Page 10h–14h: Address 30h, Shadow Value 000) ........................... 208
Table 152: 10BASE-T Register (Page 10h–14h: Address 30h, Shadow Value 001) .................................... 210
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Table 153: Power/MII Control Register (Page 10h–14h: Address 30h, Shadow Value 010)......................... 211
Table 154: Miscellaneous Test Register (Page 10h–14h: Address 30h, Shadow Value 100)....................... 211
en
Table 155: Miscellaneous Control Register (Page 10h–14h: Address 30h, Shadow Value 111) .................. 212
Table 156: Auxiliary Status Summary Register (Page 10h–14h: Address 32h–33h) .................................... 213
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Table 157: Interrupt Status Register (Page 10h–14h: Address 34h–35h) ..................................................... 214
on
Table 158: 10BASE-T/100BASE-TX/1000BASE-T Register 38h Shadow Values ........................................ 215
Table 159: Spare Control 2 Register (Page 10h–14h: Address 38h, Shadow Value 00100) ........................ 216
C
Table 160: Auto Power-Down Register (Page 10h–14h: Address 38h, Shadow Value 01010) .................... 216
Table 161: LED Selector 2 Register (Page 10h–14h: Address 38h, Shadow Value 01110) ......................... 217
om
Table 162: Mode Control Register (Page 10h–14h: Address 38h, Shadow Value 11111) ............................ 219
Table 163: Master/Slave Seed Register (Page 10h–14h: Address 3Ah–3Bh) Bit 15 = 0 .............................. 219
dc
Table 164: HCD Status Register (Page 10h–14h: Address 3Ah–3Bh) Bit 15 = 1.......................................... 220
Table 165: Test Register 1 (Page 10h–14h: Address 3C–3Dh) .................................................................... 222
oa
Table 166: Block Address Number (Page 010h-017h: Address 03Eh-03Fh) ................................................ 222
Br
Table 167: Port MIB Registers Page Summary ............................................................................................. 223
Table 168: Page 20h–28h Port MIB Registers .............................................................................................. 223
Table 169: Page 30h QoS Registers ............................................................................................................. 227
Table 170: QoS Global Control Register (Page 30h: Address 00h) .............................................................. 228
Table 171: QoS.1P Enable Register (Page 30h: Address 04h–05h) ............................................................. 229
Table 172: QoS DiffServ Enable Register (Page 30h: Address 06h–07h) .................................................... 229
Table 173: Port N (N=0-5,8) PCP_To_TC Register Address Summary ........................................................ 229
Table 174: Port N (N=0-5,8) PCP_To_TC Register (Page 30h: Address 10h–2Bh) ..................................... 230
Table 175: DiffServ Priority Map 0 Register (Page 30h: Address 30h–35h).................................................. 230
Table 176: DiffServ Priority Map 1 Register (Page 30h: Address 36h–3Bh) ................................................. 231
Table 177: DiffServ Priority Map 2 Register (Page 30h: Address 3Ch–41h) ................................................. 231
Table 178: DiffServ Priority Map 3 Register (Page 30h: Address 42h–47h).................................................. 232
Broadcom®
March 11, 2016 • 53125S-DS06-R
BROADCOM CONFIDENTIAL
Page 26
BCM53125S Data Sheet
List of Tables
Table 179: TC_To_CoS Mapping Register (Page 30h: Address 62h–63h) ................................................... 233
Table 180: CPU_To_CoS Map Register (Page 30h: Address 64h–67h) ....................................................... 233
Table 181: TX Queue Control Register (Page 30h: Address 80h)................................................................. 234
Table 182: TX Queue Weight Register Queue[0:3] (Page 30h: Address 81h–84h) ...................................... 234
Table 183: Page 31h VLAN Registers ........................................................................................................... 235
Table 184: Port-Based VLAN Control Register Address Summary ............................................................... 235
Table 185: Port VLAN Control Register (Page 31h: Address 00h–11h) ........................................................ 235
Table 186: Page 32h Trunking Registers ...................................................................................................... 236
Table 187: MAC Trunk Control Register (Page 32h: Address 00h) ............................................................... 236
Table 188: Trunk Group 0 Register (Page 32h: Address 10h–11h) .............................................................. 236
Table 189: Trunk Group 1 Register (Page 32h: Address 12h–13h) .............................................................. 237
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Table 190: Page 34h IEEE 802.1Q VLAN Registers ..................................................................................... 237
Table 191: Global IEEE 802.1Q Register (Pages 34h: Address 00h) ........................................................... 238
en
Table 192: Global VLAN Control 1 Register (Page 34h: Address 01h) ......................................................... 239
Table 193: Global VLAN Control 2 Register (Page 34h: Address 02h) ......................................................... 240
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Table 194: Global VLAN Control 3 Register (Page 34h: Address 03h–04h) ................................................. 240
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Table 195: Global VLAN Control 4 Register (Page 34h: Address 05h) ......................................................... 241
Table 196: Global VLAN Control 5 Register (Page 34h: Address 06h) ......................................................... 242
C
Table 197: VLAN Multiport Address Control Register (Page 34h: Address 0Ah–0Bh) .................................. 242
Table 198: Default IEEE 802.1Q Tag Register Address Summary ............................................................... 244
om
Table 199: Default IEEE 802.1Q Tag Register (Page 34h: Address 10h–21h) ............................................. 244
Table 200: Double Tagging TPID Register (Page 34h: Address 30h–31h) ................................................... 244
dc
Table 201: ISP Port Selection Portmap Register (Page 34h: Address 32h–33h) .......................................... 245
Table 202: DoS Prevent Register .................................................................................................................. 246
oa
Table 203: DoS Control Register (Page 36h: Address 00h–03h) .................................................................. 246
Br
Table 204: Minimum TCP Header Size Register (Page 36h: Address 04h) .................................................. 248
Table 205: Maximum ICMPv4 Size Register (Page 36h: Address 08h-0Bh)................................................. 248
Table 206: Maximum ICMPv6 Size Register (Page 36h: Address 0Ch-0Fh) ................................................ 248
Table 207: DoS Disable Learn Register (Page 36h: Address 08h-0Bh) ........................................................ 248
Table 208: Page 40h Jumbo Frame Control Register ................................................................................... 249
Table 209: Jumbo Frame Port Mask Registers (Page 40h: Address 01h–04h) ............................................ 249
Table 210: Standard Max Frame Size Registers (Page 40h: Address 05h–06h) .......................................... 250
Table 211: Broadcast Storm Suppression Register (Page 41h) .................................................................... 250
Table 212: Global Rate Control Register (Page 41h: Address 00h–03h) ...................................................... 251
Table 213: Port Rate Control Register Address Summary ............................................................................ 253
Table 214: Port Rate Control Register (Page 41h: Address 10h–33h) .......................................................... 253
Table 215: Port Egress Rate Control Configuration Register Address Summary.......................................... 256
Broadcom®
March 11, 2016 • 53125S-DS06-R
BROADCOM CONFIDENTIAL
Page 27
BCM53125S Data Sheet
List of Tables
Table 216: Port Egress Rate Control Configuration Registers (Page 41h: Address 80h–91h) ..................... 256
Table 217: IMP Port (IMP/Port5) Egress Rate Control Configuration Register Address Summary ............... 256
Table 218: IMP Port (IMP/Port5) Egress Rate Control Configuration Registers (Page 41h: Address C0h–C1h)
257
Table 219: Using Rate_Index to Configure Different Egress Rates for IMP in pps ....................................... 257
Table 220: Broadcast Storm Suppression Register (Page 42h) .................................................................... 258
Table 221: EAP Global Control Registers (Page 42h: Address 00h)............................................................. 258
Table 222: EAP Multiport Address Control Register (Page 42h: Address 01h) ............................................. 259
Table 223: EAP Destination IP Registers 0 (Page 42h: Address 02h–09h) .................................................. 260
Table 224: EAP Destination IP Registers 1 (Page 42h: Address 0Ah–12h) .................................................. 260
Table 225: Port EAP Configuration Register Address Summary ................................................................... 260
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Table 226: Port EAP Configuration Registers (Page 42h: Address 20h–47h)............................................... 260
Table 227: Broadcast Storm Suppression Register (Page 43h) .................................................................... 261
en
Table 228: MSPT Control Registers (Page 43h: Address 00h–01h) ............................................................. 261
Table 229: MSPT Aging Control Registers (Page 43h: Address 02h–05h) ................................................... 262
fid
Table 230: MSPT Table Register Address Summary .................................................................................... 262
on
Table 231: MSPT Table Registers (Page 43h: Address 10h–2Fh)................................................................ 262
Table 232: SPT Multiport Address Bypass Control Register (Page 43h: Address 50h–51h) ........................ 263
C
Table 233: MIB Snapshot Control Register ................................................................................................... 263
Table 234: MIB Snapshot Control Register (Page 70h: Address 00h) .......................................................... 264
om
Table 235: Port Snapshot MIB Control Register ............................................................................................ 264
Table 236: WAN Interface (Port 5) External PHY MII Registers .................................................................... 264
dc
Table 237: IMP Port External PHY MII Registers Page Summary ................................................................ 265
Table 238: BroadSync HD Register ............................................................................................................... 265
oa
Table 239: BroadSync HD Enable Control Register (Page 90h: Address 00h–01h) ..................................... 266
Table 240: BroadSync HD Time Stamp Report Control Register (Page 90h: Address 02h) ......................... 266
Br
Table 241: BroadSync HD PCP Value Control Register (page 90h: Address 03h) ....................................... 266
Table 242: BroadSync HD Max Packet Size Register (Page 90h: Address 04h) .......................................... 267
Table 243: BroadSync HD Time Base Register (Page 90h: Address 10h–13h)............................................ 267
Table 244: BroadSync HD Time Base Adjustment Register (Page 90h: Address 14h–17h)......................... 267
Table 245: BroadSync HD Slot Number and Tick Counter Register (Page 90h: Address 18h–1Bh) ............ 268
Table 246: BroadSync HD Slot Adjustment Register (Page 90h: Address 1Ch–1Fh) ................................... 268
Table 247: BroadSync HD Class 5 Bandwidth Control Register (Page 90h: Address 30h) .......................... 269
Table 248: BroadSync HD Class 5 Bandwidth Control Register (Page 90h: Address 30h–31h, 32h–33h, 34h–
35h, 36h–37h, 38h–39h) .............................................................................................................. 269
Table 249: BroadSync HD Class 4 Bandwidth Control Register (Page 90h: Address 60h) .......................... 270
Table 250: BroadSync HD Class 4 Bandwidth Control Register (Page 90h: Address 60h–61h, 62h–63h, 64h–
Broadcom®
March 11, 2016 • 53125S-DS06-R
BROADCOM CONFIDENTIAL
Page 28
BCM53125S Data Sheet
List of Tables
65h, 66h–67h, 68h–69h) .............................................................................................................. 270
Table 251: BroadSync HD Egress Time Stamp Register (Page 90h: Address 90h) ..................................... 270
Table 252: BroadSync HD Egress Time Stamp Register (Page 90h: Address 90h–93h, 94h–97h, 98h–9Bh,
9Ch–9Fh, A0h–A3h, A4h–A7h) .................................................................................................... 270
Table 253: BroadSync HD Egress Time Stamp Status Register (Page 90h: Address AFh) ......................... 271
Table 254: BroadSync HD Link Status Register (Page 90h: Address B0h–B1h) ......................................... 271
Table 255: BroadSync HD Egress Time Stamp Status Registers (Page 90h: Address D0h)........................ 271
Table 256: BroadSync HD Link Status Register (Page 90h: Address E0h–E1h) .......................................... 272
Table 257: Traffic Remarking Register .......................................................................................................... 272
Table 258: Traffic Remarking Control Register (Page 91h: Address 00h)..................................................... 272
Table 259: Egress Packet TC to PCP Mapping Register Address Summary ................................................ 273
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Table 260: Egress Packet TC to PCP Mapping Register (Page 91h: Address 10h–17h, 18h–1Fh, 20h–27h,
28h–2Fh, 30h–37h, 38h–3Fh, 50h-57h) ....................................................................................... 273
en
Table 261: EEE Enable Control Register (Page 92h: Address 00h).............................................................. 274
Table 262: EEE LPI Assert Register (Page 92h: Address 02h) ..................................................................... 274
fid
Table 263: EEE LPI Indicate Register (Page 92h: Address 04h) .................................................................. 274
Table 264: EEE RX Idle Symbol Register (Page 92h: Address 06h)............................................................. 275
on
Table 265: EEE Pipeline Timer Register (Page 92h: Address 0Ch) .............................................................. 275
C
Table 266: EEE Sleep Timer Gig Register (Page 92h: Address 10h) ........................................................... 275
Table 267: EEE Sleep Timer G Register (Page 92h: Address 10h–33h) ...................................................... 276
om
Table 268: EEE Sleep Timer FE Register (Page 92h: Address 34h) ............................................................ 276
Table 269: EEE Sleep Timer FE Register (Page 92h: Address 34h–57h) .................................................... 276
dc
Table 270: EEE Min LP Timer Gig Register (Page 92h: Address 58h) ......................................................... 276
Table 271: EEE Min LP timer G Register (Page 92h: Address 58h–7Bh) ..................................................... 277
oa
Table 272: EEE Min LP Timer FE Register (Page 92h: Address 7Ch) .......................................................... 277
Table 273: EEE Min LP timer FE Register (Page 92h: Address 7Ch–9Fh) ................................................... 277
Br
Table 274: EEE Wake Timer G Register (Page 92h: Address A0h) .............................................................. 277
Table 275: EEE Wake timer G Register (Page 92h: Address A0h–B1h)....................................................... 278
Table 276: EEE Wake Timer FE Register (Page 92h: Address B2h) ............................................................ 278
Table 277: EEE Min LP timer FE Register (Page 92h: Address B2h–C3h)................................................... 278
Table 278: EEE Global Congestion Threshold Register (Page 92h: Address C4h) ...................................... 278
Table 279: EEE TXQ Congestion Threshold Register (Page 92h: Address C6h) ......................................... 279
Table 280: EEE TXQ Congestion Threshold Register (Page 92h: Address C6h–D1h)................................. 279
Table 281: Global Registers (Maps to All Pages) ......................................................................................... 279
Table 282: SPI Data I/O Register (Maps to All Registers, Address F0h–F7h) .............................................. 280
Table 283: SPI Status Register (Maps to All Registers, Address FEh) ......................................................... 280
Table 284: Page Register (Maps to All Registers, Address FFh) .................................................................. 280
Broadcom®
March 11, 2016 • 53125S-DS06-R
BROADCOM CONFIDENTIAL
Page 29
BCM53125S Data Sheet
List of Tables
Table 285: Absolute Maximum Ratings ......................................................................................................... 281
Table 286: Recommended Operating Conditions .......................................................................................... 281
Table 287: Electrical Characteristics.............................................................................................................. 282
Table 288: Internal Voltage Regulator Electrical Characteristics ................................................................... 282
Table 289: Reset and Clock Timing............................................................................................................... 284
Table 290: MII Input Timing ........................................................................................................................... 285
Table 291: TMII Input Timing ......................................................................................................................... 285
Table 292: MII Output Timing ........................................................................................................................ 286
Table 293: TMII Output Timing ...................................................................................................................... 286
Table 294: Reverse MII Input Timing ............................................................................................................. 287
Table 295: Reverse TMII Input Timing........................................................................................................... 287
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Table 296: Reverse MII Output Timing .......................................................................................................... 288
Table 297: Reverse TMII Output Timing........................................................................................................ 288
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Table 298: RGMII Output Timing (Normal Mode) .......................................................................................... 289
Table 299: RGMII Output Timing (Delayed Mode) ........................................................................................ 290
fid
Table 300: RGMII Input Timing (Normal Mode) ............................................................................................. 291
on
Table 301: RGMII Input Timing (Delayed Mode) ........................................................................................... 292
Table 302: GMII Output Timing...................................................................................................................... 293
C
Table 303: GMII Input Timing ........................................................................................................................ 294
Table 304: MDC/MDIO Timing (Slave Mode) ................................................................................................ 295
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Table 305: MDC/MDIO Timing (Master Mode) .............................................................................................. 296
Table 306: Serial LED Interface Timing ......................................................................................................... 297
dc
Table 307: SPI Timings.................................................................................................................................. 298
Table 308: EEPROM Timing.......................................................................................................................... 299
oa
Table 309: JTAG Interface............................................................................................................................ 300
Br
Table 310: BCM53125S 2-Layer PCB Package With a Heat Sink ................................................................ 301
Table 311: BCM53125S 2-Layer PCB Package Without Heat Sink .............................................................. 302
Table 312: BCM53125S 4-Layer PCB Package Without a Heat Sink ........................................................... 303
Broadcom®
March 11, 2016 • 53125S-DS06-R
BROADCOM CONFIDENTIAL
Page 30
BCM53125S Data Sheet
About This Document
Purpose and Audience
This document describes the Broadcom® BCM53125S, a highly integrated, cost-effective smart-managed
Gigabit switch. The switch design is based on the field-proven, industry-leading ROBO architecture.
This document is for designers interested in integrating the BCM53125S switches into their hardware designs
and for others who need specific data about the physical characteristics and operation of the BCM53125S
switches.
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In most cases, acronyms and abbreviations are defined on first use.
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Acronyms and Abbreviations
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For a comprehensive list of acronyms and other terms used in Broadcom documents, go to:
http://www.broadcom.com/press/glossary.php.
fid
Notational Conventions
on
The following notational conventions are used in this document:
Signal names are shown in uppercase letters (such as DATA).
•
A bar over a signal name indicates that it is active-low (such as CE).
•
In register and signal descriptions, [n:m] indicates a range from bit n to bit m. For example, [7:0] indicates
bits 7 through 0, inclusive.
•
The use of R or Reserved indicates that a bit or a field is reserved by Broadcom for future use. Typically, R
is used for individual bits and Reserved is used for fields.
•
Numerical modifiers such as K or M follow traditional usage. For example, 1 KB means 1,024 bytes,
100 Mbps (referring to fast Ethernet speed) means 100,000,000 bps, and 133 MHz means
133,000,000 Hz).
Br
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dc
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C
•
Broadcom®
March 11, 2016 • 53125S-DS06-R
BROADCOM CONFIDENTIAL
Page 31
BCM53125S Data Sheet
Document Conventions
The following conventions may be used in this document:
Convention
Description
Bold
User input and actions: for example, type exit, click OK, press Alt+C
Monospace
Code: #include
HTML:
Command line commands and parameters: wl [-l]
Placeholders for required elements: enter your or wl
[]
Indicates optional command-line parameters: wl [-l]
Indicates bit and byte ranges (inclusive): [0:3] or [7:0]
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References
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The references in this section may be used in conjunction with this document.
fid
Note: Broadcom provides customer access to technical documentation and software through its
Customer Support Portal (CSP) and Downloads & Support site (see Technical Support).
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on
For Broadcom documents, replace the “xx” in the document number with the largest number available in the
repository to ensure that you have the most current version of the document.
Broadcom Items
Energy Efficient Ethernet™
[2]
Layout and Design Guidelines
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[1]
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Other Items
Motorola SPI spec
Number
Source
53125-AN2xx-R
CSP
53125-AN100-R
CSP
MC68HC08AS20-Rev. 4.0.
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[3]
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Document (or Item) Name
Technical Support
Broadcom provides customer access to a wide range of information, including technical documentation,
schematic diagrams, product bill of materials, PCB layout information, and software updates through its
customer support portal (https://support.broadcom.com). For a CSP account, contact your Sales or Engineering
support representative.
In addition, Broadcom provides other product support through its Downloads & Support site
(http://www.broadcom.com/support/).
Broadcom®
March 11, 2016 • 53125S-DS06-R
BROADCOM CONFIDENTIAL
Page 32
BCM53125S Data Sheet
Introduction
Se c t i o n 1 : I n t ro d u c t i o n
Overview
The BCM53125S is a single-chip, seven-port Gigabit Ethernet (GbE) switch device. It provides the following:
A seven-port nonblocking 10/100/1000 Mbps switch controller
•
Five ports with 1000Base-T/100Base-TX/10Base-T-compatible transceivers
•
Seven integrated gigabit MACs (GMACs)
•
One GMII/RGMII/MII/RvMII/TMII/RvTMII port for PHY-less connection to the management agent (only
available in full duplex mode)
•
One GMII/RGMII/MII/RvMII/TMII/RvTMII interface for a WAN management port (only available in fullduplex mode)
•
An integrated Motorola SPI-compatible interface
•
A high-performance, integrated packet buffer memory
•
An address resolution engine
•
A set of management information base (MIB) statistics registers
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•
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The GMACs support full-duplex and half-duplex modes for 10 Mbps and 100 Mbps and full-duplex for
1000 Mbps. Flow control is supported in the half-duplex mode with backpressure. In full-duplex mode,
IEEE 802.3x frame-based flow control is supported. The GMACs are IEEE 802.3™-compliant and support
maximum frame sizes of 9720 bytes.
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An integrated address management engine provides address learning and recognition functions at maximum
frame rates. The address table provides capacity for learning up to 4K unicast addresses. Addresses are added
to the table after receiving error-free packets.
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The MIB statistics registers collect receive and transmit statistics for each port and provide direct hardware
support for the Etherlike MIB, MIB II (interfaces), and the first four groups of the RMON MIB. All nine groups of
RMON can be supported by using additional capabilities, such as port mirroring/snooping, together with an
external microcontroller to process some MIB attributes. The MIB registers can be accessed through the Serial
Peripheral Interface (SPI) port by an external microcontroller.
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Features and Operation
S e c t i o n 2 : F e a t u re s a n d O p e ra t i o n
Overview
The BCM53125S switches include the following features:
“Quality of Service” on page 35
•
“Port-Based VLAN” on page 40
•
“IEEE 802.1Q VLAN” on page 40
•
“Double Tagging” on page 41
•
“Jumbo Frame Support” on page 44
•
“Port Trunking/Aggregation” on page 44
•
“WAN Port” on page 45
•
“Rate Control” on page 46
•
“Protected Ports” on page 48
•
“Port Mirroring” on page 48
•
“IGMP Snooping” on page 50
•
“MLD Snooping” on page 50
•
“IEEE 802.1x Port-Based Security” on page 50
•
“DoS Attack Prevention” on page 51
•
“MSTP Multiple Spanning Tree” on page 52
•
“Software Reset” on page 52
•
“BroadSync™ HD” on page 52
•
“CableChecker™” on page 55
•
“Egress PCP Remarking” on page 57
•
“Address Management” on page 57
•
“Power Savings Modes” on page 64
•
“Interrupt” on page 66
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•
The following sections discuss each feature in detail.
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March 11, 2016 • 53125S-DS06-R
Page 34
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Quality of Service
Quality of Service
“Port-Based QoS” on page 37 (ingress port ID)
•
“IEEE 802.1p QoS” on page 37
•
“MACDA-Based QoS” on page 37
•
“ToS/DSCP QoS” on page 38
•
“TC Decision Tree” on page 38
•
“Queuing Class (COS) Determination” on page 39
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The Quality of Service (QoS) feature provides up to six internal queues per port to support eight different traffic
classes (TCs). The traffic classes can be programmed so that higher-priority TCs in the switch experiences less
delay than lower-priority TCs under congested conditions. This can be important in minimizing latency for delaysensitive traffic. The BCM53125S switches can assign the packet to one of the six egress transmit queues
according to information in:
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The “TC Decision Tree” on page 38 identifies which priority system is used based on three programmable
register bits, which are detailed in Table 1: “TC Decision Tree Summary,” on page 38. The corresponding traffic
class is then assigned to one of the six queues on a port-by-port basis.
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 35
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Quality of Service
Figure 2: QoS Program Flow
Port-Based Traffic Class Mapping
IEEE 802.1p Traffic Class Mapping
MACDA-Based Traffic Class Mapping
Incoming
Packet
TC
Decision Tree
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DiffServ priority
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ACL
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COS 5
BroadSync HD
traffic only
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Traffic Class
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PCP/DSCP
Remarking
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Outgoing
Packet
SP/WRR Algorithm
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COS 4
BroadSync HD
traffic only
COS 3
COS 2
COS
Queue
ID
COS
Mapping
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COS 1
COS 0
Egress Transmit Queues
Each Ethernet egress port has six transmit queues (COS0–COS5). The COS4 and COS5 queues are dedicated
to BroadSync HD traffic only and cannot be shared with other traffic. Each COS queue has its own dedicated
counter to measure the buffer occupancy of the queue for congestion management purposes. Every Ethernet
(ingress) port has its own set of counters to measure the buffer occupancy and the arrival rate of traffic received
from the port.
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March 11, 2016 • 53125S-DS06-R
Page 36
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Quality of Service
The IMP (egress) port serves four queues (COS0–COS3) and the traffic generated by the Local Management
Packet Generator which generate management report messages back to CPU, e.g., the Time Sync TX time
stamp packets.
Each COS queue has its own dedicated counter to measure the buffer occupancy of the queue for congestion
management purpose. The IMP (ingress) port also has its own set of counters to measure the buffer occupancy
and the arrival rated to the traffic received from the port, but should be used only if it is configured as a regular
Ethernet port.
All incoming frames are assigned to an egress transmit queue depending on their assigned TC. Each egress
transmit queue is a list specifying an order for packet transmission. The corresponding egress port transmits
packets from each of the queues according to a programmable algorithm, with the higher TC queues being given
greater access than the lower TC queues. Queue 0 is the lowest-TC queue.
•
1SP, 3WRR
•
2SP, 2WRR
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4SP, 4WRR
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The COS0–COS3 queues are dedicated to non-BroadSync HD traffic only. The BCM53125S uses strict priority
(SP) and a weighted round robin (WRR) algorithm for COS0–COS3 queues scheduling. The scheduling is
configurable as one of the following combination of SP and WRR:
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The WRR algorithm weights for each queue can be programmed using registers.
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Port-Based QoS
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IEEE 802.1p QoS
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The TC of a packet received from an Ethernet (or IMP) port is assigned with the TC configured for the
corresponding port. The mapping mechanism is globally enabled and disabled using register programming.
When disabled, the TC that results from this mapping is 000.
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The TC of a packet received from an Ethernet (or IMP) port is assigned with TC configured for the corresponding
IEEE 802.1p priority code point (PCP). When disabled, or if the incoming packet is not tagged, the TC that
results from this mapping is 000.
MACDA-Based QoS
MAC destination address (MACDA)-based QoS is enabled when IEEE 802.1p QoS is disabled using the
802_1P_EN bit. When using MACDA-based QoS, the destination address and VLAN ID is used to index the
address resolution logic (ARL) table, as described in “Address Management” on page 57. The matching ARL
entry contains a 3-bit TC field as shown in Table 7 on page 60. These bits set the MACDA-based TC for the
frame. The MACDA-based TC is assigned to the TC bits depending on the result shown in Table 1 on page 38.
The TC bits for a learned ARL entry default to 0. For more information about the egress transmit queues, see
“Egress Transmit Queues” on page 36.
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 37
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Quality of Service
ToS/DSCP QoS
The TC of a packet received from an Ethernet (or IMP) port is assigned with TC configured for the corresponding
IP ToS/DSCP. When disabled or the incoming packet is not of IPv4/v6 type, the TC resulted from this mapping
is 000.
TC Decision Tree
Non-BroadSync HD Frame
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The TC decision tree determines which priority system is assigned to TC-mapping bits for the given frame. As
summarized in the preceding sections, the TC bits for the frame can be determined according to the ingress
port-based TC, IEEE 802.1p TC, MACDA-based TC, or DiffServ TC. The decision of which TC mapping to use
is based on the Port_QoS_En bit and the QoS_Layer_Sel bits. Table 1 summarizes how these programmable
bits affect the derived TC. The DiffServ and IEEE 802.1p QoS TC are available only if the respective QoS is
enabled and the received packet has the appropriate tagging.
Table 1: TC Decision Tree Summary
QoS_Layer_Sel
Value of TC Bits
0
00
IEEE 802.1p TC mapping if available; otherwise, MACDA-based TC
mapping.
0
01
DiffServ TC mapping if available; otherwise, TC = 000.
0
10
DiffServ TC mapping for IP frame; otherwise, IEEE 802.1p TC
mapping if available; otherwise, MACDA-based TC mapping.
0
11
Highest available TC of the following: IEEE 802.1p TC mapping,
DiffServ TC mapping, or MACDA-based TC mapping.
1
00
1
01
1
10
1
11
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Port_QoS_En
Port-based TC mapping.
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Port-based TC mapping.
Highest available TC of the following: Port-based TC mapping, IEEE
802.1p TC mapping, DiffServ TC mapping, or MACDA-based TC
mapping.
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Port-based TC mapping.
For the packets received from an Ethernet port when the ACL rules generate a TC-change request, the ACL
derived TC overwrites the priority generated by the Table 1 TC-mapping mechanisms.
BroadSync HD Frame
For the BroadSync HD packet from an Ethernet port, the TC is determined directly from the explicit IEEE
802.1Q/P tag carried in the BroadSync HD packets (BroadSync HD packets are expected to always be tagged),
which is independent of the Table 1 TC mapping (including ACL-based mapping). The conditions that determine
whether an incoming packet is a BroadSync HD packet are as follows:
•
The port from which the packet is received is configured as AV-enabled.
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March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Quality of Service
•
The packet received is either VLAN-tagged or priority-tagged. The priority value can be any value as long
as it matches the programmed value. The switch default setting of BroadSync HD priority values are 4 for
class 4 and 5 for class 5.
•
The MACDA can be either a multicast or unicast address as long as the MAC address matches the
configured (registered) BroadSync HD MAC addresses in the switch.
Note: BroadSync HD cannot be received from the IMP port.
Queuing Class (COS) Determination
The BCM53125S supports the COS mapping through the following mapping mechanisms:
TC to COS mapping: The queuing class to forward a packet to an Ethernet port is mapped from the TC
determined for the packet.
•
BroadSync HD to COS mapping: The queuing class to forward a BroadSync HD packet to an AV-enabled
Ethernet port is mapped from the PCP carried by the packet. PCP5 is mapped to COS5 and PCP4 is
mapped to COS4.
•
CPU to COS mapping: The queuing class to forward a packet to the external CPU through the IMP port is
determined based on the reasons to forward (copy or trap) the packet to CPU.
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Note: When the BCM53125S is configured in the aggregation mode where the IMP operates as the
uplink port to the upstream network processor, the COS is decided from the TC based on the normal
packet classification flow. Otherwise, the IMP operates as the interface to the management CPU, and
the COS is decided based on the reasons for forwarding the packet to the CPU.
Table 2 shows the reasons for forwarding a packet to the CPU.
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Table 2: Reasons to Forward a Packet to the CPU
Mirroring
SA Learning
Description
ToCPU
COS
The packet is forwarded (copied) through the IMP port because it must be 0
mirrored to the CPU as the capturing device.
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ToCPU Reason
0
The packet is forwarded (copied) through the IMP port because its SA
must be learned by the CPU. The SW_LEARN_CNTL bit of the Software
Learning register must be enabled.
Switching
The packet is forwarded through the IMP port either because the CPU is 0
one of the intended destination hosts of the packet.
Protocol Termination
The packet is forwarded (trapped) through the IMP port because it implies 0
an IEEE 802.1 defined L2 protocol that must be terminated by the CPU.
Protocol Snooping
The packet is forwarded (copied) through the IMP port because it implies 0
an L3 or application level protocol that must be monitored by the CPU for
network security or operation efficiency.
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 39
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Port-Based VLAN
Table 2: Reasons to Forward a Packet to the CPU (Cont.)
ToCPU
COS
ToCPU Reason
Description
Exception
Processing/Flooding
The packet is forwarded (trapped) through the IMP port for some special 0
processing even though the CPU is not the intended destination, or
because the switch makes the flooding decision to reach all potential
destinations.
The ToCPU COS values listed in Table 2 are the default setting and are configurable. In order to prevent out of
order delivery of the same packet flow to the CPU, the COS for the mirroring and SA learning reasons must be
programmed with a value that is lower than or equal to the value of the other reasons.
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A packet could be forwarded to the CPU for more than one reason, therefore the COS selection is based on the
highest COS values among all the reasons for the packet.
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Port-Based VLAN
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The port-based virtual LAN (VLAN) feature partitions the switching ports into virtual private domains designated
on a per port basis. Data switching outside of the port’s private domain is not allowed. The BCM53125S provide
flexible VLAN configuration for each ingress (receiving) port.
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The port-based VLAN feature works as a filter, filtering out traffic destined to nonprivate domain ports. For each
received packet, the ARL resolves the destination address (DA) and obtains a forwarding vector (list of ports to
which the frame will be forwarded). The ARL then applies the VLAN filter to the forwarding vector, effectively
masking out the nonprivate domain ports. The frame is only forwarded to those ports that meet the ARL table
criteria, as well as the port-based VLAN criteria.
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IEEE 802.1Q VLAN
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The BCM53125S support IEEE 802.1Q VLAN and up to approximately 4000 VLAN table entries that reside in
the internal embedded memory. Once the VLAN table is programmed and maintained by the microcontroller,
the BCM53125S autonomously handles all operations of the protocol. These actions include the stripping or
adding of the IEEE 802.1Q tag, depending on the requirements of the individual transmitting port. It also
performs all the necessary VLAN lookups, in addition to MAC L2 lookups.
IEEE 802.1Q VLAN Table Organization
Each VLAN table entry, also referred to as a VLAN ID, has untag map and a forward map.
•
The untag map controls whether the egress packet is tagged or untagged.
•
The forward map defines the membership within a VLAN domain.
•
The FWD_MODE indicates whether packet forwarding should be based on VLAN membership or on ARL
flow.
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Double Tagging
The untag map and forward map include bit-wise representation of all the ports.
Figure 3: VLAN Table Organization
Entry 0
FWD_MODE MSTP_Index
UNTAG_MAP[8:0]
FORWARD_ MAP[8 :0]
Entry 1
Entry 2
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Entry 4095
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Note: If the MII port is configured as a management port, then the tag is not stripped even if the untag
bit is set.
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Double Tagging
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The BCM53125S provides a double-tagging feature, which is useful for ISP applications. When the ISP
aggregates incoming traffic from each individual customer, the extra tag (double tag) can provide an additional
layer of tagging to the existing IEEE 802.1Q VLAN. The ISP tag (extra tag) is a way of distinguishing one
customer from another. Using the IEEE 802.1Q VLAN tag, an individual customer’s traffic can be identified on
a per-port basis.
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When the double-tagging feature is enabled (register page 34h, address 05h, bits [3:2]) and IEEE 802.1Q is
enabled (register page 34h, address 00h, bit 7), users can expect two VLAN tags in a frame: The tag close to
MAC_SA is the ISP tag and the one that follows it is the customer tag, as shown in Figure 4.
MAC_DA
Figure 4: ISP Tag Diagram
MAC_SA ISP_TAG Customer_ tag Ty/Len
TPID
Payload
VID
The switch uses the ISP tag for ARL and VLAN table accesses and uses the customer tag as an IEEE 802.1Q
tag. There is a per-chip programmable Double Tagging TPID register for the ISP tag (default = 9100'h). All ISP
tags are qualified by this Tag Protocol ID (TPID) value.
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 41
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Double Tagging
When the double-tagging feature is enabled, all switch ports are separated into two groups: ISP ports and
customer ports. The BCM53125S performs the normalization process for all ingress frames in both IDT and DT
modes, whether from the ISP port or the customer port. The normalization process inserts an ISP tag, customer
tag, or ISP + customer tag (depending whether the ingress frame is without tags or with one tag) to allow all
ingress frames with double tags. But if the ingress frames have double tags (ISP + customer tag) and the ISP
tag TPID matches the TPID specified in the Double Tagging TPID register, the normalization process is not
performed. The ISP ports are defined in the ISP Port Selection Portmap register. When the port(s)
corresponding bit(s) are set, that port(s) should be connected to the ISP; otherwise it should be connected to
customers. Each switch device can have multiple ports assigned as ISP ports, and each ISP is uniquely
identified using different VLAN forward maps or the port-based VLAN feature.
ISP Port
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It is possible for the ISP port to receive three different types of frames: untagged, ISP-tagged, and ISP +
customer-tagged frames.
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When the double-tagging feature is enabled and the received frame is untagged (or the TPID does not match
with ISP TPID specified in Double Tagging TPID register, the default ISP tag and customer tag are added, and
VLAN ID of ISP tag receives it from the port default VID. The frames are forwarded according to the VLAN table.
However, if the Port-Based VLAN Control register is enabled, the egress ports specified in the port-VLAN control
register override the VLAN table settings. If the received frame is ISP-tagged (its TPID matches the ISP tag
VLAN ID specified in the double-tagging TPID register), the following occurs:
1. The default customer tag (8100 + default PVID) is added.
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2. The ISP VID is used to access the ARL table.
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3. The ISP tag can be stripped on the way out according to the untagged bit setting in the VLAN table.
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In addition, the ISP port frame can be forwarded to the destination port directly based on the forward port map
of the VLAN table, by setting the FWD_MODE bit to 1 in the VLAN Table Entry register.
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The VLAN ID is generated from the ISP tag, and TC is generated from the ingress frame outer tag.
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Customer Port
It is also possible for the customer port to receive two different types of frames: untagged and customer-tagged
frames.
When the double-tagging feature is enabled, all the ingress frames preform the normalization process to insert
a ISP tag or ISP + Customer tag (depending whether the ingress frame is without tags or with one tag) to allow
all ingress frames with double tags. The VLAN ID of ISP tag receives it from the port default VID.
The VLAN ID is generated from the ISP tag, and the TC is generated from the ingress frame outer tag.
Note: It is illegal to strip out the ISP tag on the ISP egress port by using the untagged bit setting in the
VLAN table.
Broadcom®
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Double Tagging
Note: Only VLAN-tagged or untagged packets are expected for the ingress of the customer ports. The
customer does not add the ISP tags.
There are two possible traffic scenarios: one from a customer port to an ISP port and one from an ISP port to a
customer port.
Uplink Traffic (from Customer Port to ISP)
Data traffic is traffic received from the customer port without tags or a customer tag, and the frame is destined
for an ISP port. The customer ingress port performs a normalization process to allow ingress frames with double
tags (ISP + Customer tag), and the ISP tag VID is based on the port default VID tag.
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However, if the ingress frame is with an 802.1p tag, the VID of 802.1p tag is changed by the VID of port default
VID tag after the customer port normalization process. The TC do not change.
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Control traffic frames can be forwarded to the CPU first and then the CPU forwards to the ISP port if the switch
management mode is enabled and if the RESV_MCAST_FLOOD bit=0 in the Global VLAN Control 4 register.
In this case, an ISP tag is added to the control frame by the ingress port and the frame is forwarded to the CPU.
The CPU can then forward it to the ISP port with or without the ISP tag by using the egress-direct feature.
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Downlink Traffic (from ISP to Customer Port)
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Data traffic frame received from ISP port may or may not have an ISP tag attached. When the received frame
does not have an ISP tag and customer tag, the ISP ingress port does a normalization process to insert double
tags (ISP + Customer tag), and the ISP tag VID is based on the port default VID tag. All ARL and VID table
access should be based on the new tag. The traffic is then forwarded to the customer port through proper VLAN
configuration. Usually, the software configures so the customer Egress port continuously removes the ISP tag.
However, it is based on how the untagged map is configured.
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Moreover, if the ingress frame is with an 802.1p tag, the VID of 802.1p tag is changed by the VID of port default
VID tag after the ISP port normalization process. The TC will not change.
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The Control traffic is forwarded to the CPU when the switch management mode is enable and if the
RESV_MCAST_FLOOD bit=0 in the Global VLAN Control 4 register. The BCM53125S can also support multiple
ISP port configurations by enabled the FWD_MODE bit of VLAN Table Entry register.
There are also two ways to separate traffic that belongs to two different ISP customers:
1. Each group (ISP and customer) is assigned to the same VLAN group, so that traffic does not leak to other
ISPs.
2. The Port-based VLAN features is used to separate traffic that belongs to a different ISP.
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Jumbo Frame Support
Jumbo Frame Support
The BCM53125S can receive and transmit frames of extended length on ports linked at gigabit speed. Referred
to as jumbo frames, these packets are longer than the standard maximum size, but shorter than 9720 bytes.
Jumbo packets can only be received or forwarded to 1000BASE-T linked ports that are jumbo-frame enabled.
Up to 38 buffer memory pages are required for storing the longest allowed jumbo frame. While there is no
physical limitation to the number of ports that can be jumbo-enabled, it is recommended that no more than two
be enabled simultaneously to maintain acceptable system performance. There is no performance penalty for
enabling additional jumbo ports beyond the potential strain on memory resources that can occur due to
accumulated jumbo packets at multiple ports.
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Port Trunking/Aggregation
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The BCM53125S supports MAC-based trunking. The trunking feature allows up to four ports to be grouped
together as a single-link connection between two switch devices. This increases the effective bandwidth through
a link and provides redundancy. The BCM53125S allow up to two trunk groups. Trunks are composed of
predetermined ports and can be enabled using the Trunking Group 0 register. Ports within a trunk group must
be of the same link speed. By performing a dynamic hashing algorithm on the MAC address, each packet
destined for the trunk is forwarded to one of the valid ports within the trunk group. This method has several key
advantages. By dynamically performing this function, the traffic patterns can be more balanced across the ports
within a trunk. In addition, the MAC-based algorithm provides dynamic failover. If a port within a trunking group
fails, the other port within the trunk automatically assumes all traffic designated for the trunk. It allows for a
seamless, automatic redundancy scheme. This hashing function can be performed using DA, SA, or DA/SA.
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Figure 5: Trunking
Switch 2
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Switch 1
Frame Y
Port X
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Frame Z
Frame X
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Port Y
Port 0
One Pipe
Port Z
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March 11, 2016 • 53125S-DS06-R
Port 1
Port 2
Page 44
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
WAN Port
WAN Port
The BCM53125S offers a programmable WAN port feature: It has a WAN Port Select register (page 00h,
address 26h). Select a port as a WAN port, then all that port’s traffic is forwarded to the CPU port only. The nonWAN port traffic from all other local ports does not flood to the WAN port. Figure 6 shows the WAN and LAN
domain separation when WAN port is selected.
Figure 6: WAN and LAN Domain Separation When WAN Port Is Selected
LAN domain
LAN Y
LAN Z
WAN
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LAN X
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WAN domain
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IMP/ISP
LAN X
IMP/ISP
IMP2 (P5)
LAN domain
WAN domain
LAN Y
LAN Z
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March 11, 2016 • 53125S-DS06-R
WAN
Page 45
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Rate Control
Rate Control
Ingress Rate Control
Forwarding broadcast traffic consumes switch resources, which can negatively impact the forwarding of other
traffic. The rate-based broadcast storm suppression mechanism is used to protect regular traffic from an
overabundance of broadcast or multicast traffic. This feature monitors the rate of ingressed traffic of
programmable packet types. If the rates of these packet types exceed the programmable maximum rate, the
packets are dropped.
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The broadcast storm suppression mechanism works on a credit-based rate system that figuratively uses a
bucket to track the bandwidth of each port (see Figure 7 on page 46). Credit is continually added to the bucket
at a programmable bucket bit rate. Credit is decremented from the bucket whenever one of the programmable
packet types is ingressed at the port. If no packets are ingressed for a considerable length of time, the bucket
credit continues to increase up to a programmable maximum bucket size. If a heavy burst of traffic is suddenly
ingressed at the port, the bucket credit becomes drained. When the bucket is emptied, incoming traffic is
constrained to the bucket bit rate (the rate at which credit is added to the bucket). At this point, excess packets
are either dropped or deterred using flow control, depending upon the Suppression Drop mode.
on
Figure 7: Bucket Flow
Ingress Packet Rate
assigned to Bucket 2
C
Ingress Packet Rate
assigned to Bucket 1
Bucket 2 Bit Rate
dc
om
Bucket 1 Bit Rate
Br
oa
Accumulated Credit
BUCKET 1
Accumulated Credit
BUCKET 2
If there is no accumulated credit available,
the switch does not accept input packets .
Two-Bucket System
For added flexibility, the BCM53125S employs two buckets to track the rate of ingressed packets. Each of the
two buckets (Bucket 0 and Bucket 1) can be programmed to monitor different packet types. For example, Bucket
0 could monitor broadcast packets while Bucket 1 monitors multicast packets. Multiple packet types can be
monitored by each bucket, and a packet type can be monitored by both buckets.
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Rate Control
The rates of each bucket can be individually programmed. For example, the broadcast packets of Bucket 0 could
have a maximum rate of 3 Mbps, whereas the multicast packets of Bucket 1 could be allowed up to 80 Mbps.
The size of each bucket can be programmed. This determines the maximum credit than can accumulate in each
bucket. The Rate Count and Bucket Size can be individually programmed for each port, providing another level
of flexibility. Suppression control can be enabled or disabled on a per-port basis. This system allows the user to
control dual packet-type rates on a per-port basis.
Egress Rate Control
The BCM53125S monitor the rate of egress traffic per port. Unlike the Ingress traffic rate control, the Egress
Rate Control provides only the per-port rate control regardless of traffic types. This feature only uses one bucket
to track the rate of egressed packets. The Egress Rate Control feature only support absolute bit rate mode (Bit
Rate Mode = 0) and the bucket bit rate calculation is shown in Table 3.
tia
l
Bucket Bit Rate
C
on
fid
en
The relative ingress rates of each bucket can be programmed on a per-port basis. Each port has a
programmable Rate Count value for Bucket 0 and Bucket 1. Additionally, the bit rate mode is programmed on a
chip basis. If this bit is 1, the packet rate is automatically scaled according to the port link speed. Ports operating
at 1000 Mbps would be allotted a 100 times higher ingress rate than ports linked at 10 Mbps. Together, the Rate
Count value and the bit rate mode determine the bucket bit rate, which is a reflection of how quickly data can
be ingressed (Kbps) at the given port for a given bucket. The Rate Count values are specified in Table 3. Values
outside these ranges are not valid entries.
Table 3: Bucket Bit Rate
Bucket Bit Rate
Link Speed Equation
Approximate Computed
Bucket Bit Rate
Values (as a function of RC)
1–28
0
Any
= (RC x 8 x 1M)/125
64 KB, 128 KB, 192 KB, …1.792 MB
29–127
0
Any
= (RC – 27) x 1M
2 MB, 3 MB, 4 MB, …100 MB
128–240
0
Any
= (RC – 115) x 1M x 8
104 MB, 112 MB, 120 MB, …1000 MB
1–125
1
10 Mbps
= (RC x 8 x 1M)/100
0.08 MB, 0.16 MB, 0.24 MB, …10 MB
100 Mbps
= (RC x 8 x 1M)/10
dc
oa
1
Br
1–125
1–125
om
Bit Rate
Rate Count (RC) Mode
1
1000 Mbps = RC x 8 x 1M
0.8 MB, 1.6 MB, 2.4 MB, …100 MB
8 MB, 16 MB, 24 MB, …1000 MB
Note: 1M represents 1 x 106.
IMP Port Egress Rate Control
The IMP port egress is configurable of rate limiting at packet-per-second (PPS) granularity, in addition to bitsper-second (BPS) granularity.
Broadcom®
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Protected Ports
Protected Ports
The Protected Ports feature allows certain ports to be designated as protected. All other ports are unprotected.
Traffic between protected port group members is blocked. However, protected ports are able to send traffic to
unprotected ports. Unprotected ports can send traffic to any port. Several applications that can benefit from
protected ports:
Aggregator: For example, all the available ports are designated as protected ports except a single
aggregator port. No traffic incoming to the protected ports is sent within the protected ports group. Any
flooded traffic is forwarded only to the aggregator port.
•
To prevent unsecured ports from monitoring important information on a server port, the server port and
unsecured ports are designated as protected. The unsecured ports will not be able to receive traffic from
the server port.
tia
l
•
en
Port Mirroring
on
fid
The BCM53125S support Port Mirroring, allowing ingress and/or egress traffic to be monitored by a single port
designated as the mirror capture port. The BCM53125S can be configured to mirror the ingress traffic and/or
egress traffic of any other port (s). Mirroring multiple ports is possible, but can create congestion at the mirror
capture port. Several filters are used to decrease congestion.
C
Enabling Port Mirroring
om
Port Mirroring is enabled by setting the Mirror Enable bit.
dc
Figure 8: Mirror Filter Flow
oa
Port mask filter
Ingress mirror filter
Port divider filter
Ingress mirror divider
Br
Ingress mirror mask
Port address filter
All packets
Egress mirror mask
Capture port
Egress mirror filter
Egress mirror divider
Destination port(s)
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Port Mirroring
Capture Port
The capture port is capable of monitoring other specified ports. Frames transmitted and received at the other
ports are forwarded to the Capture port according to the mirror filtering rules described in the next section.
Mirror Filtering Rules
Mirror filtering rules consist of a set of three filter operations (Port Mask, Packet Address, and Packet Divider)
that are applied to traffic ingressed and/or egressed at a switch port.
Port Mask Filter
l
The IN_MIRROR_MASK bits define the receive ports that are monitored. The OUT_MIRROR_MASK bits define
the transmit ports that are monitored.
en
tia
Any number of ingress/egress ports can be programmed to be mirrored, but bandwidth restrictions on the onemirror capture port should be taken into account to avoid congestion or packet loss.
fid
Packet Address Filter
•
Mirror received frames with DA = x
•
Mirror received frames with SA = x
C
Mirror all received frames
om
•
on
The type of filtering that is applied to frames received on the mirrored ports is configurable. The
IN_MIRROR_FILTER bits select among the following:
oa
Packet Divider Filter
dc
where x is the 48-bit MAC address. Likewise, The type of filtering that is applied to frames transmitted on the
egressed mirrored ports.
Br
The IN_DIV_EN bit allows further statistical sampling. When IN_DIV_EN = 1, the receive frames passing the
initial filter are divided by the value IN_MIRROR_DIV, which is a 10-bit value. Only one out of every n frames is
forwarded to the mirror capture port, where n = IN_MIRROR_DIV +1. This allows the following additional
capabilities:
•
Mirror every nth received frame.
•
Mirror every nth received frame with DA = x.
•
Mirror every nth received frame with SA = x.
Note: When multiple ingress ports have been enabled in the IN_MIRROR_MASK, the cumulative total
packet count received from all ingress ports is divided by the value of IN_MIRROR_DIV to deliver the
nth receive frame to the mirror capture port. Egressed frames are governed by the
OUT_MIRROR_MASK bit and the OUT_MIRROR_DIV bit.
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
IGMP Snooping
IGMP Snooping
The BCM53125S supports IP-layer IGMP Snooping, which includes IGMP unknown, query, report, and leave
messages.
An IGMP frame has a value of 2 in the IP header protocol field. These frames are forwarded to the CPU port.
The management CPU can then determine from the IGMP control packets which port should participate in the
multigroup session. The management CPU proactively programs the multicast address in the ARL table or the
multiport address entries. If the IGMP_UKN_FWD_MODE, IGMP_QRY_FWD_MODE,
IGMP_RPTLVE_FWD_MODE is enabled, IGMP frames are trapped to the CPU port only.
l
MLD Snooping
on
IEEE 802.1x Port-Based Security
fid
en
tia
The BCM53125S supports IP layer MLD Snooping includes MLD query, report and done message. For each of
the query and report/done message types, four options are available: discard, forward normally, forward to CPU,
or forward normally and copy to CPU. The CPU is then expected to interpret those messages and configure the
address table accordingly.
oa
dc
om
C
IEEE 802.1x is a port-based authentication protocol. By receiving and extracting special frames, the CPU can
control whether the ingress and egress ports should forward packets or not. If a user port wants service from
another port (authenticator), it must get approved by the authenticator. EAPOL is the protocol used by the
authentication process. The BCM53125S detect EAPOL frames by checking the destination address of the
frame. The Destination addresses should be either a multicast address as defined in IEEE 802.1x (01-80-C200-00-03) or a user-predefined MAC (unicast or multicast) address. When EAPOL frames are detected, the
frames are forwarded to the CPU so it can send them to the authenticator server. Eventually, the CPU
determines whether the requestor is qualified based on its MAC_Source addresses, and frames are either
accepted or dropped. The per-port EAP can be programmed in the register.
Br
BCM53125S provides three modes for implementing the IEEE 802.1x feature. Each mode can be selected by
setting the appropriate bits in the register.
The Basic Mode (when EAP Mode = 00'b) is the standard mode, where the EAP_BLK_MODE bit is set before
authentication to block all incoming packets. Upon authentication, the EAP_BLK_MODE bit is cleared to allow
all incoming packets. In this mode, the Source Address of incoming packets is not checked.
In Extended Mode (when EAP Mode = 10'b), an extra filtering mechanism is implemented after the port is
authenticated. If the Source MAC address is unknown, the incoming packets are dropped and the unknown SA
is not learned. However if the incoming packet is an IEEE 802.1x packet, or special frames, the incoming
packets are forwarded. The definition of the Unknown SA in this case is when the switch cannot match the
incoming Source MAC address to any of the addresses in ARL table, or the incoming Source MAC address
matches the address in ARL table but the port number is mismatched.
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BCM53125S Data Sheet
DoS Attack Prevention
The third mode is Simplified Mode (when EAP Mode = 11'b). In this mode, the unknown Source MAC address
packets are forwarded to the CPU rather than dropped. Otherwise, it is same as the Extended Mode operation.
Note: The BCM53125S check only the destination addresses to qualify EAPOL frames. Ethernet type
fields, packet type fields, and non-IEEE 802.1Q frames are not checked.
DoS Attack Prevention
The BCM53125S supports the detection of the following DoS (Denial of Service) attack types based on a
register setting, which can be programmed to drop or not to drop each type of DoS packet.
Table 4: DoS Attacks Detected by BCM53125S
Description
IP_LAND
IPDA = IPSA in an IPv4/IPv6 datagram.
TCP_BLAT
DPort = SPort in a TCP header carried in an unfragmented IP datagram or in the first
fragment of a fragmented IP datagram.
UDP_BLAT
DPort = SPort in a UDP header carried in an unfragmented IP datagram or in the first
fragment of a fragmented IP datagram.
TCP_NULLScan
Seq_Num = 0 and all TCP_FLAGs = 0 in a TCP header carried in an unfragmented IP
datagram or in the first fragment of a fragmented IP datagram.
TCP_XMASScan
Seq_Num = 0, FIN = 1, URG = 1, and PSH = 1 in a TCP header carried in an
unfragmented IP datagram or in the first fragment of a fragmented IP datagram.
TCP_SYNFINScan
SYN = 1 and FIN = 1 in a TCP header carried in an unfragmented IP datagram or in the
first fragment of a fragmented IP datagram.
TCP_SYNError
SYN = 1, ACK = 0, and SRC_Port Prohibit Access (RO/LH), for Page Number = 8'h1X, which are PHY MII registers.
Broadcom®
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Programming Interfaces
Figure 40: Pseudo-PHY MII Register 24: Access Register Bit Definition
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit #
Access register bits [15:0]
Reg 24
bits [15:0] => Access register bits [15:0] (RW)
Figure 41: Pseudo-PHY MII Register 25: Access Register Bit Definition
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit #
tia
l
15
Reg 25
fid
en
Access register bits [31:16]
on
bits [15:0] => Access register bits [31:16] (RW)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
om
15
C
Figure 42: Pseudo-PHY MII Register 26: Access Register Bit Definition
Reg 26
oa
dc
Access register bits [47:32]
Bit #
Br
bits [15:0] => Access register bits [47:32] (RW)
Figure 43: Pseudo-PHY MII Register 27: Access Register Bit Definition
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Access register bits [63:48]
1
0
Bit #
Reg 27
bits [15:0] => Access register bits [63:48] (RW)
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Programming Interfaces
Figure 44: Read Access to the Register Set Using the Pseudo-PHY (PHYAD = 11110) MDC/MDIO Path
Write MII register 16:
Set bit 0 as 1
Set Page Number to bits [15:8]
Write MII register 17:
Set Operation Code as 10
Set register address to bits [15:8]
Read MII register 17:
Check op_code = 00?
en
tia
l
No
fid
Yes
C
on
Read MII register 24:
for Access register bits [15:0]
dc
om
Read MII register 25:
for Access register bits [31:16]
Br
oa
Read MII register 26:
for Access register bits [47:32]
No
Read MII register 27:
for Access register bits [63:48]
New Page Access?
Yes
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Programming Interfaces
Figure 45: Write Access to the Register Set Using the Pseudo-PHY (PHYAD = 11110) MDC/MDIO Path
Write MII register 16:
Set bit 0 as 1
Set Page Number to bits [15:8]
Write MII register 24:
for Access register bits [15:0]
en
fid
Write MII register 26:
for Access register bits [47:32]
tia
l
Write MII register 25:
for Access register bits [31:16]
C
on
Write MII register 27:
for Access register bits [63:48]
Read MII register 17:
Check op_code = 00?
No
Br
oa
dc
om
Write MII register 17:
Set Operation Code as 01
Set register address to bits [15:8]
Yes
No
New Page Access?
Yes
Table 28 summarizes the complete management frame format.
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
LED Interfaces
Table 28: MII Management Frame Format
Operation
PRE
ST
OP
PHYAD
REGAD
TA
Data
Direction
Read
1 ... 1
01
10
AAAAA
RRRRR
ZZ
Z0
Z ... Z
D ... D
Driven by master
Driven by slave
Write
1 ... 1
01
01
AAAAA
RRRRR
10
D ... D
Driven to master
See “MDC/MDIO Interface” on page 111 for more information regarding the timing requirements.
LED Interfaces
The following options are available for the LED display:
fid
en
tia
l
The BCM53125S provides flexible programmable per-port status of various functions. The user can select
predefined LED displays per port by setting the LED_MODE strap pins, or the user can program different display
functions for different ports by programming the LED Control registers. When the GMII (port 5) port is not used,
the BCM53125S offers a total of 20 LED displays, four functions per port. When the GMII interface is used, the
BCM53125S offers a total of 10 LED displays, two functions per port. The LED interface offers options to display
different functions.
Number of displays per port based on the GMII_LED_SEL strap pin option
•
GMII_LED_SEL = 1: Total of 20 LED displays, four display functions per port
•
GMII_LED_SEL = 0: Total of 10 LED displays, two display functions per port
C
on
•
dc
om
Note: This mode is forced when the GMII (port 5) is used for the data interface.
When the GMII (port 5) is used, the 20 LED display option is not available.
oa
The LED[xx] signal allocation for each port is shown in Table 29 and Table 30 on page 118.
Different function displays per port
•
Default display settings using strap pins LED_MODE[1:0]
Br
•
The different display-per-LED_MODE settings are shown in Table 29 and Table 30 on page 118. Each
LED[xx] signal is assigned to a specific port. For example, if port 4, port 3, and port 2 LED displays are
disabled (register page 00h, address 16h = 0003), port 0 and port 1 LED display are still from LED pins
LED[16:19] (port 0), LED[12:15] (port 1), just as if all five ports were used. If port 1 and port 0 LED displays
are disabled (register page 00h, address 16h = 001C), port 2, port 3, and port 4 are still from LED pins
LED[8:11] (port 2), LED[4:7] (port 3), and LED[0:3] (port 4), again as if all five ports were used.
All ports display the same set of functions based on the strap pin settings. The display is fixed per port and
per pin as shown in Table 29 and Table 30 on page 118.
•
Displaying one of two different display settings by programming the LED configuration registers
Enable LED display per port using register page 00h, address 16h).
Two sets of display options can be set using the LED Function Control register 0 and 1 (register page 00h,
address 10h, and 12h).
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
LED Interfaces
Each port can select one of two display functions (register page 00h, address 14h).
Note: Refer to 53125-AN100-R, Layout and Design Guidelines, for a more detailed description of how
to program LED-related registers.
•
Different LED lighting behavior (register page 00h, address 18h, and 1Ah)
•
Automatic mode: All mode indicators are in steady state, except for the activity indicator, which is blinking.
•
Blink mode: All status indicators are blinking. The blinking rate can be set using register page 00h, address
0Fh, bit [2:0].
•
ON mode: Forces the LED to be on
tia
l
The status of enabled ports is sent out from a higher port number to the lowest port number. The output order
in the shift-out is from LED[0], LED[1], LED[2], …LED[19]. The output port order for LED is from high port
number to low port number, and the output bit order within the port LED is from MSB to LSB.
en
Table 29: 20 LED Display Mode (GMII_LED_SEL=1)
Port
LED_Function Reg 1 (Default)
1
2
3
4
'b11
'b10
'b01
LED[16]
LED[12]
LED[08]
LED[04]
LED[00]
1G/ACT
SPD1G
1G/ACT
SPD1G
LED[17]
LED[13]
LED[09]
LED[05]
LED[01]
10_100/ACT
SPD100M
LED[18]
LED[14]
LED[10]
LED[06]
LED[02]
10M/ACT
LNK/ACT
DPX/COL
LNK/ACT
LED[19]
LED[15]
LED[11]
LED[07]
LED[03]
DPX
DPX
PHYLED4
PHYLED4
fid
0
om
C
on
100M/ACT SPD100M
Table 30: 10 LED Display Mode (GMII_LED_SEL=0)
1
2
3
4
LED[08]
LED[06]
LED[09]
LED[07]
LED[04]
LED[02]
LED[00]
LED[05]
LED[03]
LED[01]
LED_Function Reg 1 (Default)
'b11
'b10
'b01
'b00
1G/ACT
SPD1G
1G/ACT
SPD1G
100M/ACT SPD100M 10/100M/ACT SPD100M
Br
oa
0
dc
Port
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March 11, 2016 • 53125S-DS06-R
Page 118
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
LED Interfaces
Figure 46 shows the LED Interface register structure.
Figure 46: LED Interface Register Structure Diagram
LED Function Control Register 0
Available Functions
LED Function Control Register 1
Selected Functions
Available Functions
15 : PHYLED3
15 : PHYLED3
14 : BroadSync HD Link
14 : BroadSync HD Link
13 : 1G/ACT
12 : 10 /100 M/ACT
13 : 1G/ACT
12 : 10/100 M/ACT
11 : 100M/ACT
9 : SPD1G
10 : 10M/ACT
9 : SPD1G
LNKL/ACTG
DPX/COL
LNKG/ACTL
6 : DPX/COL
6 : DPX/COL
SPD100M
5 : LNK/ACT
5 : LNK/ACT
4 : COL
4 : COL
3 : ACT
2 : DPX
3 : ACT
2 : DPX
1 : LNK
1 : LNK
0 : PHYLED4
0 : PHYLED4
fid
en
tia
8 : SPDI00M
7 : SPD10M
LNK
C
on
8 : SPDI00M
7 : SPD10M
11 : 100M/ACT
1G/ACT
l
10 : 10M/ACT
Selected Functions
1 1
0
0
LED Function Map Register
1
1 1
0
0
LED Enable Map Register
0
1 0
1
1 Port Mode Map 0 Register 0 1 0 1
1
1 1
0
0 Port Mode Map 1 Register 0 0 1 1
oa
dc
Reserved
0
om
Reserved
Note:
Br
Reserved
4 3
2 1
0
PHYLED3 and PHYLED4 are the output of the
functions that are selected in the LED Selector 2
Register (Page10h– 14h: Address 38P Shadow
value 01110'b)
Port / Bit #
LED AUTO
LED BLINK
LED ON
LED OFF
The BCM53125S offer two LED Interfaces, parallel LED interface and serial interface. As shown in Figure 47,
the source of LED status stream is the same for both interfaces; the status bit stream is based on the
programmed register settings. The Parallel LED Interface provides all the shifting and storing of the status
internally, so that it does not require any external shift registers, but it requires more I/O pins to be connected
on the part. The active level of the LED DATA signal can be low or high depending on the strap pin configuration
of the each LED signal in the parallel LED interface output. The determination of the active state is shown in
“Dual-Input Configuration/LED Output Function” on page 121.
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
LED Interfaces
The serial LED interface is being output through two pins (LEDDATA, LEDCLK). This approach minimizes the
number of I/O pins but requires the user to design using the external shift registers. The serial LED interface
provides the LED display of ports 0–5. The active level of the LEDDATA signal is low for all status in the serial
LED interface output.
Figure 47: LED Interface Block Diagram
LED I/O Block
LED Control Block
LEDCLK
LEDDATA
Q
D
LED[1]
Q
D
LED[3]
Q
D
om
C
on
fid
en
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l
LED[0]
LED[19]
D
Br
oa
dc
Q
Dual LED is used for displaying more than one status using one LED cell. By packing two different colors LED
into one holder, dual LED can display more than two states in one cell. Figure 48 shows a typical dual LED
usage. Green LED is to display LNKG/ACT status, while Yellow LED is to display LNKF/ACT status.
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BCM53125S Data Sheet
LED Interfaces
Figure 48: Dual LED Usage Example
Green LED
LNKF/ACT
LNKG/ACT
Yellow LED
l
Dual-Input Configuration/LED Output Function
on
fid
en
tia
There are 10 LED pins that have secondary functions. These pins serve as input pins during the power-on/reset
sequence. The logic level of the pin is sampled at reset and configures the secondary function. After the reset
process is completed, the pin acts as an output LED during normal operation. The polarity of the output LED is
determined based on the latched input value at reset. For example, if the value at the pin is high during reset,
the LED output during normal operation is active-low. The user must first decide, based on the individual
application, the values of the input configuration pin shown in Table 31 to provide the correct device
configuration. The LED circuit must then be configured to accommodate either an active-low or active-high LED
output.
C
Table 31: Dual Input Configuration/LED Output Function
Internal Default
Input Configuration Pins Pull Up/Down
Active State
LED [0]
MII_DUMB_FWDG_EN
Pull up
Opposite of strap pin state.
LED [1]
No configuration
Pull up
Active low.
LED [2]
LED_MODE[1]
Pull up
Opposite of strap pin state.
LED [3]
SYSFREQ[1]
Pull up
Opposite of strap pin state.
GMII_MODE[0]
Pull up
Opposite of strap pin state.
GMII_MODE[1]
Pull up
Opposite of strap pin state.
IMP_MODE[0]
Pull up
Opposite of strap pin state.
LED [6]
dc
oa
LED [5]
Br
LED [4]
om
LED Output Pins
LED [7]
IMP_MODE[1]
Pull up
Opposite of strap pin state.
LED [8]
CPU_EEPROM_SEL
Pull up
Opposite of strap pin state.
LED [9]
HW_FWDG_EN
Pull up
Opposite of strap pin state.
LED [10]
GMII_RXD[0]
Pull down
LED Active state is always low.
LED [11]
GMII_RXD[1]
Pull down
LED Active state is always low.
LED [12]
GMII_RXD[2]
Pull down
LED Active state is always low.
LED [13]
GMII_RXD[3]
Pull down
LED Active state is always low.
LED [14]
GMII_RXD[4]
Pull down
LED Active state is always low.
LED [15]
GMII_RXD[5]
Pull down
LED Active state is always low.
LED [16]
GMII_RXD[6]
Pull down
LED Active state is always low.
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
LED Interfaces
Table 31: Dual Input Configuration/LED Output Function (Cont.)
LED Output Pins
Internal Default
Input Configuration Pins Pull Up/Down
Active State
LED [17]
GMII_RXD[7]
Pull down
LED Active state is always low.
LED [18]
GMII_RXDV
Pull down
LED Active state is always low.
LED [19]
GMII_RXER
Pull down
LED Active state is always low.
Note: For LEDs whose active state is “opposite of strap pin state,” if the signal is pulled up/down, the LED is
active low/high.
Figure 49: Dual Input Configuration/LED Output Function
switch
switch
3.3v
3.3v
3.3v
en
tia
l
3.3v
Low active
LED signal
High active
LED signal
dc
om
C
High active
LED signal
on
fid
Low active
LED signal
oa
Note: When LED signal pins are pulled up or down through an external or an internal termination due
to the strap pin configuration, the active states of LED signals are:
If the signal is pulled up, the LED is active low.
•
If the signal is pulled low, the LED is active high.
Br
•
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Internal Digital Regulator Controller
Internal Digital Regulator Controller
The BCM53125S has an Internal Digital Regulator Controller. You can use Regulator Controller to control an
external regulator to generate 1.2V power supply. This feature can help to avoid extra circuitry required to
generate 1.2V power supply if only required by the BCM53125S in the system. The internal digital regulator
block involves three I/O signals. All other necessary signals are internally connected.
•
NDRIVE: External NMOS gate control
•
PDRIVE: External PMOS gate control
•
VFB: External target voltage feedback
Figure 50 on page 123 shows how these signals can be used to generate a 1.2V power supply.
BCM53125S
BCM53115
FDC6327C
Internal Digital
Regulator Controller
S2
S1
NDRIVE
G1
D1
PDRIVE
on
fid
VFB
en
3.3V (MOSFET)
tia
l
Figure 50: Internal Digital Regulator Controller
D2
1.2 V
0.1 µF
Br
oa
dc
om
C
G2
L=3.3uH
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Hardware Signal Definition Table
Section 5: Hardware Signal Definition
Ta bl e
I/O Signal Types
The following conventions are used to identify the I/O types shown in the following table. The I/O pin type is
useful in referencing the DC-pin characteristics.
Table 32: I/O Signal Type Definitions
Active low signal
3T
3.3V tolerant
A
Analog pin type
B
Bias pin type
en
XYZ
l
Description
tia
Abbreviation
Continuously sampled
D
Digital pin type
DNC
Do not connect
GND
Ground
on
fid
CS
Input
C
I
I/O
Bidirectional
Input with internal pull-up
om
IPU
O3S
SOR
PWR
PU
XT
dc
PD
oa
O
Open-drain output
Br
ODO
Tristated Signal
Output
Internal pull-down
Sample on reset
Power pin supply
Internal pull-up
Crystal pin type
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Signal Descriptions
Signal Descriptions
Table 33: Signal Descriptions
Signal Name
Type
Description
TRD0_0±
–
TRD1_0±
–
TRD2_0±
–
TRD3_0±
–
TRD0_1±
–
Transmit/Receive Pairs. In TRD [pair number]_[port number]±
1000BASE-T mode, differential data from the media is transmitted and
received on all four signal pairs. In auto-negotiation and 10BASE-T and
100BASE-TX modes, the BCM53125S normally transmits on
TRD[0]_[port number]± and receives on TRD[1]_{port number}±. AutoMDIX operation can reverse the pairs TRD[0]_{4:0}± and TRD[1]_{4:0}±.
TRD1_1±
–
TRD2_1±
–
TRD3_1±
–
TRD0_2±
–
TRD1_2±
–
TRD2_2±
–
TRD3_2±
–
TRD0_3±
–
TRD1_3±
–
TRD2_3±
–
TRD3_3±
–
TRD0_4±
–
TRD1_4±
–
TRD2_4±
–
TRD3_4±
–
XTALI
XTALO
tia
en
fid
on
C
om
dc
I,Pu
Hardware Reset Input. Active low Schmitt-triggered input. Resets the
BCM53125S.
I,XT
25 MHz Crystal Oscillator Input/Output. A continuous 25 MHz reference
clock must be supplied to the BCM53125S by connecting a 25 MHz crystal
between these two pins or by driving XTALI with an external 25 MHz oscillator
clock. When using a crystal, connect a loading capacitor from each pin to
GND. When using an oscillator, leave XTALO unconnected. The maximum
XTALI input voltage is 3.3V.
Br
RESET
oa
Clock/Reset
l
PHY Interface
O,XT
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Signal Descriptions
Table 33: Signal Descriptions (Cont.)
Signal Name
Type
Description
IMP_TXCLK
I,O Pd
MII/TMII Transmit Clock. This is an input pin in MII mode, or GMII mode but
speed is 100Mbps/10Mbps. It synchronizes the TXD[3:0] and connects to the
PHY Entity TXC. In 100 Mbps mode, this is 25 MHz, and in 10 Mbps mode,
this is 2.5 MHz. In 200 Mbps mode (TMII), this is 50 MHz.
RvMII/RvTMII Receive Clock. This is an output pin in RvMII mode. It
synchronizes the TXD[3:0] in RvMII mode and connects to the MAC/
Management Entity RXC. In 100 Mbps mode, this is 25 MHz, and in 10 Mbps
mode, this is 2.5 MHz. This output pin has an internal 25Ω series termination
resistor. In 200 Mbps mode (TMII), this is 50 MHz.
This clock is not use in the other conditions.
IMP_TXD[0]
O,Pd
IMP_TXD[1]
O,Pd
IMP_TXD[2]
O,Pd
IMP_TXD[3]
O,Pd
GMII Transmit Data Output (first nibble). Data bits TXD[3:0] are clocked on
the rising edge of TXCLK.
RGMII Transmit Data Output. For 1000 Mbps operation, data bits TXD[3:0]
are clocked on the rising edge of TXCLK, and data bits TXD[7:4] are clocked
on the falling edge of TXCLK. For 10 Mbps and 100 Mbps, data bits TXD[3:0]
are clocked on the rising edge of TXCLK.
RvMII/RvTMII Receive Data Output. Clocked on the rising edge of TXCLK
and connected to the RXD pins of the external MAC/Management entity.
MII/TMII Transmit Data Output. Clocked on the rising edge of TXCLK
supplied by MAC/Management entity.
These output pins have internal 25Ω series termination resistor.
IMP_TXD[4]
O,Pd
IMP_TXD[7]
O,Pd
IMP_TXEN
I Pd
C
O,Pd
om
O,Pd
IMP_TXD[6]
GMII Transmit Data Output (second nibble). Data bits [7:4] are clocked on
the rising edge of TXCLK. These output pins have internal 25Ω series
termination resistor.
GMII/MII/TMII Transmit Enable. Active high. TXEN indicates the data on the
TXD pins are encoded and transmitted.
RGMII Transmit Control. On the rising edge of TXCLK, TXEN indicates that
a transmit frame is in progress, and the data present on the TXD[3:0] output
pins is valid. On the falling edge of TXCLK, TXEN is a derivative of GMII mode
TXEN and TXER signals.
RvMII/RvTMII Receive Data Valid. Active high. Connected to RXDV pin of
MAC/Management entity. Indicates that a receive frame is in progress, and the
data present on the TXD[3:0] output pins is valid.
This output pin has an internal 25Ω series termination resistor.
Br
oa
dc
IMP_TXD[5]
on
fid
en
tia
l
IMP Interface
IMP_TXER
O,Pd
GMII/MII/TMII Transmit Error. Active high. Asserting TXER when TXEN is
high indicates a transmission error. TXER is also used to indicate Carrier
Extension when operating in half-duplex mode. This output pin has an internal
25Ω series termination resistor.
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Signal Descriptions
Table 33: Signal Descriptions (Cont.)
Type
Description
IMP_RXCLK
I, Pd
GMII Receive Clock. 125 MHz for 1000 Mbps operation.
RGMII Receive Clock. 125 MHz for 1000 Mbps operation, 25 MHz for 100
Mbps operation, and 2.5 MHz for 10 Mbps operation. Data bits RXD[3:0] are
clocked in on the rising edge of the RXCLK, and data bits RXD[7:4] are
clocked in on the falling edge of the RXCLK.
MII Receive Clock. 25 MHz for 100 Mbps operation, and 2.5 MHz for 10 Mbps
operation.
TMII Receive Clock. 50 MHz for 200 Mbps operation.
O
RvMII/RvTMII Transmit Clock. Synchronizes the RXD[3:0] in RvMII mode
and connects to the MAC/Management entity TXC. 25 MHz for 100 Mbps
mode, and 2.5 MHz for 10 Mbps mode. This output pin has an internal 25Ω
series termination resistor.
RvMII Transmit Clock. 25 MHz for 100 Mbps operation, and 2.5 MHz for 10
Mbps operation.
RvTMII Transmit Clock. 50 MHz for 200 Mbps operation.
IMP_RXD[0]
I,Pd
IMP_RXD[1]
I,Pd
IMP_RXD[2]
I,Pd
IMP_RXD[3]
I,Pd
GMII Receive Data Inputs (first nibble). Data bits RXD[3:0] are clocked on
the rising edge of RXCLK.
RGMII Receive Data Inputs. For 1000 Mbps operation, data bits RXD[3:0]
are clocked-out on the rising edge of RXCLK, and data bits RXD[7:4] are
clocked on the falling edge of RXCLK. In 10 Mbps and 100 Mbps modes, data
bits RXD[3:0] are clocked on the rising edge of RXCLK.
RvMII/RvTMII Transmit Data Inputs. Clocked on the rising edge of RXCLK
and connected to the TXD pins of the external MAC/Management entity.
MII/TMII Receive Data Input. Data bits RXD[3:0] are clocked on the rising
edge of RXCLK.
IMP_RXD[7:4]/
I,O,Pd
GMII Receive Data Inputs (second nibble). Data bits RXD[7:4] are clocked
out on the rising edge of RXCLK.
IMP_RXDV
I,Pd
GMII/MII/TMII Receive Data Valid. Active high. RXDV indicates that a
receive frame is in progress, and the data present on the RXD output pins is
valid.
RGMII Receive Data Valid. Functional equivalent of GMII RXDV on the rising
edge of RXCLK and functional equivalent of a logical derivative of GMII RXDV
and RXER on the falling edge of RXCLK.
RvMII/RvTMII Transmit Enable. Active high. Indicates the data on the
RXD[3:0] pins are encoded and transmitted. Connects to the TXEN of the
external MAC/Management entity.
Br
oa
dc
om
C
on
fid
en
tia
l
Signal Name
IMP_RXER
I,Pd
GMII/MII/TMII Receive Error. Indicates an error during the receive frame.
IMP_GTXCLK
O,Pd
GMII Transmit Clock. This clock is driven to synchronize the transmit data in
1000 Mbps speed in GMII mode.
RGMII Transmit Clock. This clock is driven to synchronize the transmit data
in RGMII mode(125 MHz for 1000 Mbps operation, 25 MHz for 100 Mbps
operation, and 2.5 MHz for 10 Mbps operation). In RGMII mode, both edges
of the clock are used to align with TXD[3:0].
IMP_GTXCLK is used in RGMII and 1000 Mbps speed in GMII mode.
IMP_TXCLK is used for MII mode, and 10/100 Mbps speed in GMII mode.
This output pin has an internal 25Ω series termination resistor.
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Signal Descriptions
Table 33: Signal Descriptions (Cont.)
Type
Description
IMP_VOL_SEL[1]
I,Pd
IMP_VOL_SEL[1] is used to set the voltage level of the IMP port (port 8)
RGMII interface.
0 = 2.5V (default)
1 = 1.5V
Note: IMP_VOL_SEL signal is to set the voltage level of the IMP port (port 8)
RGMII interface.
GMII_GTXCLK/NC
O,Pd
When GMII_LED_SEL =1b'0 (2 x PHY-less ports are used).
GMII Transmit Clock. This clock is driven to synchronize the transmit data in
1000 Mbps speed in GMII mode.
RGMII Transmit Clock. This clock is driven to synchronize the transmit data
in RGMII mode (125 MHz for 1000 Mbps operation, 25 MHz for 100 Mbps
operation, and 2.5 MHz for 10 Mbps operation). In RGMII mode, both edges
of the clock are used to align with TXD[3:0].
• GMII_GTXCLK is used in RGMII and 1000 Mbps speed in GMII mode.
GMII_TXCLK is used for MII mode, and 10/100 Mbps speed in GMII
mode.
en
•
tia
l
Signal Name
When GMII_LED_SEL =1b'0 (2 x PHY-less ports are used).
MII/TMII Transmit Clock. This is an input pin in MII mode, or GMII mode but
speed is 100 Mbps/10 Mbps. It synchronizes the TXD[3:0] and connects to the
PHY Entity TXC. In 100 Mbps mode, this is 25 MHz, and in 10 Mbps mode,
this is 2.5 MHz.
RvMII/RvTMII Receive Clock. This is an output pin in RvMII mode. It
synchronizes the TXD[3:0] in RvMII mode and connects to the MAC/
Management Entity RXC. In 100 Mbps mode, this is 25 MHz, and in 10 Mbps
mode, this is 2.5 MHz. This output pin has an internal 25Ω series termination
resistor, and in 200 Mbps mode (RvTMII), this is 50 MHz.
This clock is not uses in the other conditions.
When GMII_LED_SEL =1b'1 (1 x PHY-less port (IMP) is used). No
connect.
on
O,Pd
GMII_TXEN/NC
Br
oa
dc
om
C
GMII_TXCLK/NC
fid
This output pin has an internal 25Ω series termination resistor.
When GMII_LED_SEL =1b'1 (1 x PHY-less port (IMP) is used). No
connect.
O,Pd
When GMII_LED_SEL =1b'0 (2 x PHY-less ports are used).
GMII/MII/TMII Transmit Enable. Active high. TXEN indicates the data on the
TXD pins are encoded and transmitted.
RvMII/RvTMII Receive Data Valid. Active high. Connected to RXDV pin of
MAC/Management entity. Indicates that a receive frame is in progress, and the
data present on the TXD[3:0] output pins is valid. This output pin has an
internal 25Ω series termination resistor.
When GMII_LED_SEL =1b'1 (1 x PHY-less port (IMP) is used). No
connect.
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Signal Descriptions
Table 33: Signal Descriptions (Cont.)
Type
Description
GMII_TXER/NC/
I,O,Pd
When GMII_LED_SEL =1b'0 (2 x PHY-less ports are used).
GMII/MII/TMII Transmit Error. Active high. Asserting TXER when TXEN is
high indicates a transmission error. TXER is also used to indicate Carrier
Extension when operating in half-duplex mode. This output pin has an internal
25Ω series termination resistor.
When GMII_LED_SEL =1b'1 (1 x PHY-less port (IMP) is used). No
connect.
GMII_TXD[0]/NC
O,Pd
GMII_TXD[1]/NC
O,Pd
GMII_TXD[2]/NC
O,Pd
GMII_TXD[3]/NC
O,Pd
When GMII_LED_SEL =1b'0 (2 x PHY-less ports are used).
GMII Transmit Data Output (first nibble). Data bits TXD[3:0] are clocked on
the rising edge of TXCLK.
RGMII Transmit Data Output. For 1000 Mbps operation, data bits TXD[3:0]
are clocked on the rising edge of TXCLK, and data bits TXD[7:4] are clocked
on the falling edge of TXCLK. For 10 Mbps and 100 Mbps, data bits TXD[3:0]
are clocked on the rising edge of TXCLK.
RvMII/RvTMII Receive Data Output. Clocked on the rising edge of TXCLK
and connected to the RXD pins of the external MAC/Management entity.
MII/TMII Transmit Data Output. Clocked on the rising edge of TXCLK
supplied by MAC/Management entity.
These output pins have internal 25Ω series termination resistor.
When GMII_LED_SEL =1b'1 (1 x PHY-less port (IMP) is used). No
connect.
GMII_TXD[7]/NC
O,Pd
GMII_RXCLK
I,Pd
C
O,Pd
om
GMII_TXD[6]/NC
When GMII_LED_SEL =1b'0 (2 x PHY-less ports are used).
GMII Transmit Data Output (second nibble). Data bits [7:4] are clocked on
the rising edge of TXCLK. These output pins have internal 25Ω series
termination resistor.
When GMII_LED_SEL =1b'1 (1 x PHY-less port (IMP) is used). No
connect.
GMII Receive Clock. 125 MHz for 1000 Mbps operation.
RGMII Receive Clock. 125 MHz for 1000 Mbps operation, 25 MHz for
100Mbps operation, and 2.5 MHz for 10 Mbps operation. Data bits RXD[3:0]
are clocked in on the rising edge of the RXCLK, and data bits RXD[7:4] are
clocked in on the falling edge of the RXCLK.
MII/TMII Receive Clock. 25 MHz for 100 Mbps operation, and 2.5 MHz for 10
Mbps operation. 50 MHz input for 200 Mbps TMII operation.
dc
O,Pd
O,Pd
Br
oa
GMII_TXD[4]/NC
GMII_TXD[5]/NC
on
fid
en
tia
l
Signal Name
O
RvMII/RvTMII Transmit Clock. Synchronizes the RXD[3:0] in RvMII mode
and connects to the MAC/Management entity TXC. 25 MHz for 100 Mbps
mode, and 2.5 MHz for 10 Mbps mode. This output pin has an internal 25Ω
series termination resistor and 50 MHz for 200 Mbps mode (RvTMII).
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Signal Descriptions
Table 33: Signal Descriptions (Cont.)
Type
Description
GMII_RXDV/LED[18]
I,O Pd
When GMII_LED_SEL =1b'0 (2 x PHY-less ports are used).
GMII/MII/TMII Receive Data Valid. Active high. RXDV indicates that a
receive frame is in progress, and the data present on the RXD output pins is
valid.
RGMII Receive Data Valid. Functional equivalent of GMII RXDV on the rising
edge of RXCLK and functional equivalent of a logical derivative of GMII RXDV
and RXER on the falling edge of RXCLK.
RvMII/RvTMII Transmit Enable. Active high. Indicates the data on the
RXD[3:0] pins are encoded and transmitted. Connects to the TXEN of the
external MAC/Management entity.
When GMII_LED_SEL =1b'1 (1 x PHY-less port (IMP) is used).
GMII_RXDV is used as LED[18]
GMII_RXER/LED[19]
I,O Pd
When GMII_LED_SEL =1b'0 (2 x PHY-less ports are used). GMII/MII/TMII
Receive Error. Indicates an error during the receive frame.
When GMII_LED_SEL =1b'1 (1 x PHY-less port (IMP) is used).
GMII_RXER is used as LED[19].
GMII_RXD[0]/LED[10] I,O Pd
When GMII_LED_SEL =1b'0 (2 x PHY-less ports are used).
GMII Receive Data Inputs (first nibble). Data bits RXD[3:0] are clocked on
the rising edge of RXCLK.
RGMII Receive Data Inputs. For 1000 Mbps operation, data bits RXD[3:0]
are clocked-out on the rising edge of RXCLK, and data bits RXD[7:4] are
clocked on the falling edge of RXCLK. In 10 Mbps and 100 Mbps modes, data
bits RXD[3:0] are clocked on the rising edge of RXCLK.
RvMII/RvTMII Transmit Data Inputs. Clocked on the rising edge of RXCLK
and connected to the TXD pins of the external MAC/Management entity.
MII/TMII Receive Data Input. Data bits RXD[3:0] are clocked on the rising
edge of RXCLK.
When GMII_LED_SEL =1b'1 (1 x PHY-less port (IMP) is used).
GMII_RXD[3:0] are used as LED[13:10].
dc
om
C
GMII_RXD[3]/LED[13] I,O Pd
fid
GMII_RXD[2]/LED[12] I,O Pd
on
GMII_RXD[1]/LED[11] I,O Pd
en
tia
l
Signal Name
When GMII_LED_SEL =1b'0 (2 x PHY-less ports are used).
GMII Receive Data Inputs (second nibble). Data bits RXD[7:4] are clocked
out on the rising edge of RXCLK.
When GMII_LED_SEL =1b'1 (1 x PHY-less port (IMP) is used).
GMII_RXD[7:4] are used as LED[17:14].
oa
GMII_RXD[4]/LED[14] I,O Pd
GMII_RXD[5]/LED[15] I,O Pd
Br
GMII_RXD[6]/LED[16] I,O Pd
GMII_RXD[7]/LED[17] I,O Pd
RGMII_VOL_SEL[1]
Pd,
SOR
RGMII_VOL_SEL[1] is used to select RGMII Interface voltage.
0 = 2.5V (default)
1 = 1.5V
Note: RGMII_VOL_SEL signal is set to set the voltage level of the WAN port
(port 5) RGMII interface.
GMII_LED_SEL
I,Pd
Select signals to be selected for LED output, or WAN (GMII) interface.
Enable WAN port used as LED output.
1 = GMII interface signals of WAN port used as LED output
0 = Used as original WAN port (default)
MDC/MDIO Interface
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March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Signal Descriptions
Table 33: Signal Descriptions (Cont.)
Signal Name
Type
Description
MDIO
I/O,Pd
Management Data I/O.
In master mode, this serial input/output data signal is used to read from and
write to the MII registers of the external transceivers.
In slave mode, it is used by an external entity to read/write to the switch
registers using the pseudo-PHY. See “MDC/MDIO Interface” on page 111 for
more information.
MDC
I/O,Pd
Management Data Clock.
In master mode, this 2.5 MHz clock sourced by BCM53125S to the external
PHY device.
In slave mode, it is sourced by an external entity.
TCK
I,Pu
JTAG Test Clock Input. Clock Input used to synchronize JTAG control and
data transfers. If unused, may be left unconnected.
TDI
I,Pu
JTAG Test Data Input. Serial data input to the JTAG TAP Controller.
Sampled on the rising edge of TCK. If unused, may be left unconnected.
TDO/EN_8051
O,Pu
SOR
JTAG Test Data Output.
TDO is used for the strap pin for EN_8051. Enable the embedded
BCM8051 microcontroller. The embedded BCM8051 microcontroller is
enabled by default.
0 = Disabled.
1 = Enable (default).
TMS
I,Pu
JTAG Mode Select Input.
TRST
I,Pd
JTAG Test Reset. Active low. Resets the JTAG controller. This signal must be
pulled low during normal operation.
Br
oa
dc
om
C
on
fid
en
tia
l
Test Interface
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Signal Descriptions
Table 33: Signal Descriptions (Cont.)
Signal Name
Type
Description
LED Interface
O,Pu
LED[0]/
MII_DUMB_FWDG_E SOR
N
LED[1]
Parallel LED Indicators.
• LED[19:0]: Five ports x 4 LEDs = 20 (exclude IMP)
•
O,Pu
SOR
O,Pu
SOR
LED[4]/
GMII_MODE[0]
O,Pu
SOR
LED[5]/
GMII_MODE[1]
O,Pu
SOR
tia
LED[3]/SYSFREQ[1]
en
LED[6]/IMP_MODE[0] O,Pu
SOR
fid
LED[7]/IMP_MODE[1] O,Pu
SOR
on
LED[8]/
O,Pu
CPU_EEPROM_SEL SOR
O,Pu
SOR
C
LED[9]/
HW_FWDG_EN
LED[0] is used for the strap pin for MII_DUMB_FWDG_EN. IMP port in
blocking state for managed mode.
0 = Blocking for managed mode
1 = Forwarding for dumb mode (unmanaged mode)
When this pin is pulled up, the IMP port is not in management mode, the IMP
port is in a regular port. No Broadcom header is required for ingress, and
egress.
LED[1] is not used for a configuration.
LED[2] is used for the strap pin for LED_MODE[1]. See detailed
description for LEDCLK/LED_MODE[0] on the following page.
LED[3] is used for the strap pin for SYSFREQ[1]. See detailed description
in LEDDATA//SYSFREQ[0] on the following page.
LED[5:4] are used for the strap pin for GMII_MODE[1:0]. GMII Port mode.
Sets the mode of the GMII port based on the value of the pins at power-on
reset.
00 = RGMII mode
01 = MII/TMII mode
10 = RvMII/RvTMII mode
11 = GMII mode (default)
LED[7:6] are used for the strap pin for IMP_MODE[1:0]. IMP Port mode.
Sets the mode of the IMP port based on the value of the pins at power-on
reset.
00 = RGMII mode
01 = MII/TMII mode
10 = RvMII/TMII mode
11 = GMII mode (default)
LED[8] is used for the strap pin for CPU_EEPROM_SEL. CPU or
EEPROM interface selection.
• CPU_EEPROM_SEL = 0: Enable EEPROM interface
l
LED[2]/LED_MODE[1] O,Pu
SOR
LED[9:0]: Five ports x 2 LEDs = 10 (when port5(GMII port) is connected to
an external entity.) LED[19:10] are used for GMII interface.
Br
oa
dc
om
LED[19:10]: see GMII –
RXDV, GMII RXER,
and GMII RXD signals
•
CPU_EEPROM_SEL = 1: Enable SPI Interface (default)
The SPI interface must be selected (CPU_EEPROM_SEL=1) for Pseudo-PHY
accesses through the MDC/MDIO Interface. See “Programming Interfaces” on
page 94 for more information.
LED[9] is used for the strap pin for HW_FWDG_EN. Forwarding enable.
Active high.
• When this pin is pulled high (default) at power-up, traffic is forwarded
without any register settings, based on default register settings.
•
When this pin is pulled low at power-up, frame forwarding is disabled.
Traffic forwarding is enabled through Software Register bit set.
Broadcom®
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BCM53125S Data Sheet
Signal Descriptions
Table 33: Signal Descriptions (Cont.)
Type
Description
LEDCLK/
LED_MODE[0]
O,Pd,
SOR
LEDDATA//
SYSFREQ[0]
O,Pd,
SOR
LEDCLK is LED Shift Clock. This clock is periodically active to enable
LEDDATA to shift into external registers.
LEDDATA is Serial LED Data Output. Serial LED data for all ports is shifted
out when LEDCLK is active. LEDMODE[1:0] pins set the serial data content.
See “LED Interfaces” on page 117 for a functional description of this signal.
LED[2] and LEDCLK are used for the strap pin for LED MODE[1:0].
Users can select predefined functions to be displayed for each port by setting
the bits accordingly.
Note: When GMII_LED_SEL =0, GMII port is connected to an external CPU
entity, only 2 LED function displays are available. The functions in bold, italic
fonts are the ones will be displayed when GMII_LED_SEL = 0.
• When LED MODE[1:0] = 00:
GbE Configuration
SPD1G
SPD100M
LNK/ACT
PHYLED4
• When LED MODE[1:0] = 01:
GbE Configuration
1G/ACT
10/100M/ACT
DPX/COL
PHYLED4
• When LED MODE[1:0] = 10 (default):
GbE Configuration
SPD1G
SPD100M
LNK/ACT
DPX
• When LED MODE[1:0] = 11:
FE Configuration GbE Configuration
100M/ACT
1G/ACT
10M/ACT
100M/ACT
DPX
10M/ACT
DPX
LED[3] and LEDDATA are used for the strap pin for SYS_FREQ[1:0].
System clock selection.
Determines rate of system clock:
00 = 83 MHz
01 = 91 MHZ
10 = 100 MHz (normal operation)
11 = 111 MHz
Br
oa
dc
om
C
on
fid
en
tia
l
Signal Name
Broadcom®
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Signal Descriptions
Table 33: Signal Descriptions (Cont.)
Signal Name
Type
Description
Serial Flash Interface
FCK
O,Pd
Flash Memory Serial Clock. The clock output for serial Flash memory.
FCS_B
I,Pd
Flash Memory Chip Select. Active low signal. Chip select to serial Flash
memory device.
FSI
I,Pd
Serial Data Input. Serial data input from serial Flash memory.
FSO
O,Pd
Serial Data Output. Serial data output to drive serial Flash memory.
SPI/EEPROM Programming Interfaces
I,O Pd
SPI Serial Clock. The clock input to the BCM53125S SPI interface is supplied
by the SPI master, which supports up to 25 MHz, and is enabled if
CPU_EPROM_SEL is high during power-on reset.
EEPROM Serial Clock. The clock output to an external EEPROM device, and
is enabled if CPU_EPROM_SEL is low during power-on reset.
See “Programming Interfaces” on page 94 for more information.
SS/CS
I,O Pu
SPI Slave Select. Active low signal which enables an SPI interface read or
write operation. Enable if CPU_EPROM_SEL is high during power-on reset.
EEPROM Chip Select. Active high control signal that enables a read
operation from an external EEPROM device. Enable if CPU_EPROM_SEL is
low during power-on reset.
See “Programming Interfaces” on page 94 for more information.
MOSI/DI
I,O Pu
SPI Master-Out/Slave-In. Input signal which receives control and address
information for the SPI interface, as well as serial data during write operations.
Enabled if CPU_EPROM_SEL is high during power-on reset.
EEPROM Data In. Serial data input to an external EEPROM device. Enabled
if CPU_EPROM_SEL is low during power-on reset.
See “Programming Interfaces” on page 94 for more information.
MISO/DO/EN_EEE
I,O,Pu, SPI Master-In/Slave-Out. Output signal which transmits serial data during an
SOR
SPI interface read operations. Enabled if CPU_EPROM_SEL is high during
power-on reset.
EEPROM Data Out. Serial data output to an external EEPROM device.
Enable if CPU_EPROM_SEL is low during power-on reset.
See “Programming Interfaces” on page 94 for more information.
MISO is used for the strap pin for EN_EEE (Energy Efficient Ethernet).
Enable EEE feature for switch MAC:
1 = Enable (default)
0 = Disable
Br
oa
dc
om
C
on
fid
en
tia
l
SCK/SK
Interrupt Pin
INT
O,Pu
Interrupt. This interrupt pin generates an interrupt based on the configuration
in the Interrupt Enable register. It can be programmed to generate based on
link status change of any port, or to generate an interrupt to a CPU entity when
there is a packet(s) queued in the IMP transmit queue.
–
A 1.24 kΩ resistor to GND is required.
Bias
QGPHY1_RDAC
Broadcom®
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Signal Descriptions
Table 33: Signal Descriptions (Cont.)
Signal Name
Type
Description
QGPHY2_RDAC
–
A 1.24 kΩ resistor to GND is required.
EGPHY_RDAC
–
A 1.24K Ω resistor to GND is required.
AVDDL
–
1.2V analog power, power ring 0.
OVDD
–
3.3/2.5/1.5V digital IMP port power, power ring 1.
Power Interfaces
–
3.3/2.5/1.5V digital WAN (port5) port power, power ring 2.
AVDDL
–
1.2V analog power, power ring 4.
OVDD2
–
3.3V digital I/O power, power ring 5.
AVDDH
–
3.3V analog I/O power.
DVDD
–
1.2V digital core power.
OTP_VDD
–
3.3V OTP power.
EGPHY_BVDD
–
3.3V bias power for GPHY.
QGPHY1_BVDD
–
3.3V bias power for GPHY.
3.3V bias power for GPHY.
–
1.2V PLL power for GPHY.
SWREG_VDDO
–
3.3V regulator power.
XTAL_AVDD
–
3.3V XTAL power.
PLL_AVDD
–
1.2V system PLL power.
QGPHY1_PLLVDD
–
1.2V PLL power for GPHY.
QGPHY2_PLLVDD
–
1.2V PLL power for GPHY.
IMP_VOL_REF
–
•
en
–
EGPHY_PLLVDD
C
on
fid
QGPHY2_BVDD
tia
l
OVDD3
om
dc
•
When 3.3V GMII interface is used, IMP_VOL_REF should be connected to
VSSC (Ground).
When 2.5V RGMII interface is used, IMP_VOL_REF should be connected
to VSSC (Ground).
When 1.5V RGMII interface is used, IMP_VOL_REF should be connected
VDDO/2 which is 0.75V.
–
•
Br
GMII_VOL_REF
oa
•
•
•
When 3.3V GMII interface is used, GMII_VOL_REF should be connected
to VSSC (Ground).
When 2.5V RGMII interface is used, GMII_VOL_REF should be connected
to VSSC (Ground).
When 1.5V RGMII interface is used, GMII_VOL_REF should be connected
VDDO/2 which is 0.75V.
Internal Regulator Interface
NDRIVE
O
NMOS gate signal.
PDRIVE
O
PMOS gate signal.
VFB
I
Output voltage feedback signal.
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Pin Assignment
Section 6: Pin Assignment
Pin List by Pin Number
Signal
Pin
Signal
A03
NC
AE10
AVDDH
A05
TDP_2_2
AE12
QGPHY2_RDAC
A07
TDN_0_2
AE14
AVDDH
A09
QGPHY1_PLLVDD
AE18
DVDD
A11
TDN_0_1
AE20
GMII_RXD[5]/LED[15]
A13
TDP_2_1
AE22
GMII_RXER/LED[19]
A15
TDN_3_1
AE24
GMII_VOL_REF
A17
EGPHY_PLLVDD
AE27
GMII_TXD[7]/NC
A19
TDN_0_0
AE29
GMII_TXD[2]/NC
A21
TDP_2_0
AF02
A23
TDN_3_0
AF28
A25
NC
AG01
NC
A27
NC
AG05
NC
AA01
DVDD
AG07
TDP_2_3
AA03
LED[4]/GMII_MODE[0]
AG09
NC
AA27
GMII_TXCLK/NC
AG11
QGPHY2_PLLVDD
AG13
TDN_1_4
AG15
AVDDH
en
tia
l
Pin
RESET
om
C
on
fid
GMII_TXD[3]/NC
GMII_GTXCLK/NC
AB02
LED[5]/GMII_MODE[1]
AB05
LED[8]/CPU_EEPROM_SEL
AG17
NC
AB25
GMII_TXD[1]/NC
AG19
GMII_RXD[7]/LED[17]
AG21
GMII_RXD[6]/LED[16]
dc
AA29
GMII_TXD[4]/NC
AC01
LED[6]/IMP_MODE[0]
AG23
GMII_RXD[4]/LED[14]
AC03
LED[7]/IMP_MODE[1]
AG25
DVDD
AC27
GMII_TXD[5]/NC
AG29
NC
AC29
GMII_TXD[0]/NC
AH04
TDP_3_3
AD02
LED[9]/HW_FWDG_EN
AH06
TDN_2_3
AD05
NC
AH08
TDN_1_3
AD17
PLL_AVDD
AH10
TDP_0_3
AD25
GMII_TXER/NC
AH12
TDP_0_4
AD28
GMII_TXD[6]/NC
AH14
TDP_1_4
AE01
MDC
AH16
TDN_2_4
AE03
MDIO
AH18
TDP_3_4
AE06
NC
AH20
GMII_RXD[3]/LED[13]
AE08
AVDDH
AH22
GMII_RXD[1]/LED[11]
Br
oa
AB28
Broadcom®
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Pin List by Pin Number
Signal
Pin
Signal
AH24
GMII_RXCLK
C29
NC
AH26
NC
D02
NC
AJ03
NC
D28
NC
AJ05
TDN_3_3
E01
IMP_VOL_SEL[1]
AJ07
TDP_1_3
E03
RGMII_VOL_SEL[1]
AJ09
TDN_0_3
E08
AVDDH
AJ11
QGPHY2_BVDD
E10
AVDDH
AJ13
TDN_0_4
E12
NC
AJ15
TDP_2_4
E14
AVDDH
AJ17
TDN_3_4
E16
EGPHY_RDAC
AJ19
NC
E18
AVDDH
AJ21
GMII_RXD[2]/LED[12]
E20
DVDD
AJ23
GMII_RXD[0]/LED[10]
E22
NC
AJ25
GMII_RXDV/LED[18]
E27
IMP_TXD[4]
AJ27
NC
E29
B04
TDN_2_2
ePAD
B06
TDP_1_2
ePAD
B08
TDP_0_2
ePAD
B10
QGPHY1_RDAC
B12
TDN_1_1
B14
TDN_2_1
B16
TDP_3_1
B18
TDP_0_0
B20
TDP_1_0
B22
TDN_2_0
en
tia
l
Pin
IMP_TXD[0]
on
fid
PLL_VSS
QGPHY1_BGND
ePAD
QGPHY1_PLLGND
ePAD
QGPHY2_BGND
C
om
dc
PLL_VSS
ePAD
QGPHY2_PLLGND
ePAD
VSS
ePAD
XTAL_AVSS
ePAD
SWREG_AVSS
ePAD
SWREG_VSSO
F02
NC
F05
NC
F21
SWREG_VDDO
F23
VFB
TDP_3_0
B26
NC
C01
NC
C03
TDP_3_2
C05
TDN_3_2
F25
NC
C07
TDN_1_2
F28
IMP_TXD[5]
C09
QGPHY1_BVDD
G01
LEDCLK/LED_MODE[0]
C11
TDP_0_1
G03
VSS
C13
TDP_1_1
G06
NC
C15
EGPHY_BVDD
G27
IMP_TXD[1]
C17
NC
G29
IMP_TXD[6]
C19
TDN_1_0
H02
GMII_LED_SEL
C21
NC
H05
LEDDATA/SYS_FREQ[0]
C23
PDRIVE
H25
NC
C25
NDRIVE
H28
IMP_TXD[2]
Br
oa
B24
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Pin List by Pin Number
Signal
Pin
Signal
J01
FCLK
U29
IMP_RXD[6]
J03
NC
V02
SCK
J27
IMP_TXD[7]
V05
LED[0]/MII_DUMB_FWDG_EN
J29
IMP_GTXCLK
V25
DVDD
K02
FCS_B
V28
IMP_RXD[3]
K05
FSI
W01
MOSI
K25
IMP_TXD[3]
W03
LED[1]
K28
IMP_TXEN
W27
OTP_VDD
L01
INT
W29
IMP_RXD[7]
L03
FSO
Y02
LED[2]/LED_MODE[1]
L27
IMP_TXER
Y05
LED[3]/SYS_FREQ[1]
L29
IMP_TXCLK
Y25
NC
M02
NC
Y28
GMII_TXEN/NC
M28
DVDD
N01
TRST
tia
IMP_VOL_REF
en
DVDD
M25
N29
IMP_RXDV
P02
TDO/EN_8051
P05
TDI
P25
IMP_RXCLK
P28
IMP_RXD[4]
PWRing0
AVDDL
PWRing1
OVDD
PWRing2
OVDD3
PWRing4
AVDDL
PWRing5
OVDD2
C
IMP_RXER
om
TMS
N27
Br
oa
dc
N03
on
fid
M05
l
Pin
R01
TCK
R03
XTAL_O
R27
IMP_RXD[1]
R29
IMP_RXD[0]
T02
XTAL_I
T05
XTAL_AVDD
T25
NC
T28
IMP_RXD[5]
U01
SS
U03
MISO/EN_EEE
U27
IMP_RXD[2]
Broadcom®
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Pin List by Signal Name
Pin List by Signal Name
Pin
Signal
Pin
AVDDH
AE08
GMII_RXER/LED[19]
AE22
AVDDH
AE10
GMII_TXCLK/NC
AA27
AVDDH
AE14
GMII_TXD[0]/NC
AC29
AVDDH
AG15
GMII_TXD[1]/NC
AB25
AVDDH
E08
GMII_TXD[2]/NC
AE29
AVDDH
E10
GMII_TXD[3]/NC
AF28
AVDDH
E14
GMII_TXD[4]/NC
AB28
AVDDH
E18
GMII_TXD[5]/NC
AC27
AVDDL
PWRing0
GMII_TXD[6]/NC
AD28
AVDDL
PWRing4
GMII_TXD[7]/NC
AE27
DVDD
AA01
GMII_TXEN/NC
Y28
DVDD
AE18
GMII_TXER/NC
AD25
DVDD
AG25
GMII_VOL_REF
AE24
DVDD
E20
RGMII_VOL_SEL[1]
E03
DVDD
M05
IMP_GTXCLK
J29
DVDD
M28
IMP_RXCLK
P25
DVDD
V25
EGPHY_PLLVDD
A17
EGPHY_RDAC
E16
tia
en
fid
on
C15
IMP_RXD[0]
R29
IMP_RXD[1]
R27
C
EGPHY_BVDD
l
Signal
U27
IMP_RXD[3]
V28
C17
IMP_RXD[4]
P28
F02
IMP_RXD[5]
T28
J01
IMP_RXD[6]
U29
K02
IMP_RXD[7]
W29
K05
IMP_RXDV
N29
L03
IMP_RXER
N27
AA29
IMP_TXCLK
L29
H02
IMP_TXD[0]
E29
AH24
IMP_TXD[1]
G27
GMII_RXD[0]/LED[10]
AJ23
IMP_TXD[2]
H28
GMII_RXD[1]/LED[11]
AH22
IMP_TXD[3]
K25
GMII_RXD[2]/LED[12]
AJ21
IMP_TXD[4]
E27
GMII_RXD[3]/LED[13]
AH20
IMP_TXD[5]
F28
GMII_RXD[4]/LED[14]
AG23
IMP_TXD[6]
G29
GMII_RXD[5]/LED[15]
AE20
IMP_TXD[7]
J27
GMII_RXD[6]/LED[16]
AG21
IMP_TXEN
K28
GMII_RXD[7]/LED[17]
AG19
IMP_TXER
L27
AJ25
IMP_VOL_REF
M25
om
IMP_RXD[2]
NC
NC
FCS_B
FSI
FSO
GMII_LED_SEL
Br
GMII_GTXCLK/NC
oa
dc
FCLK
GMII_RXCLK
GMII_RXDV/LED[18]
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Pin List by Signal Name
Pin
Signal
Pin
IMP_VOL_SEL[1]
E01
NC
G06
INT
L01
NC
H25
NC
M02
NC
T25
LED[0]/MII_DUMB_FWDG_EN
V05
NC
Y25
LED[1]
W03
PDRIVE
C23
LED[2]/LED_MODE[1]
Y02
OTP_VDD
W27
LED[3]/SYS_FREQ[1]
Y05
OVDD
PWRing1
LED[4]/GMII_MODE[0]
AA03
OVDD2
PWRing5
LED[5]/GMII_MODE[1]
AB02
OVDD3
PWRing2
LED[6]/IMP_MODE[0]
AC01
NC
E22
LED[7]/IMP_MODE[1]
AC03
PLL_AVDD
AD17
LED[8]/CPU_EEPROM_SEL
AB05
NC
AJ19
LED[9]/HW_FWDG_EN
AD02
PLL_VSS
LEDCLK/LED_MODE[0]
G01
QGPHY1_BGND
LEDDATA/SYS_FREQ[0]
H05
QGPHY1_BVDD
C09
MDC
AE01
QGPHY1_PLLGND
ePAD
MDIO
AE03
QGPHY1_PLLVDD
MISO/EN_EEE
U03
QGPHY1_RDAC
MOSI
W01
NC
A03
NC
A25
NC
A27
NC
tia
en
fid
on
ePAD
A09
B10
E12
QGPHY2_BGND
ePAD
C
NC
QGPHY2_BVDD
AJ11
QGPHY2_PLLGND
ePAD
QGPHY2_PLLVDD
AG11
AE06
QGPHY2_RDAC
AE12
AG01
NC
AG09
dc
NC
ePAD
AD05
om
NC
l
Signal
RESET
AF02
AG17
NC
J03
AG29
SCK
V02
AH26
SS
U01
AJ03
SWREG_VDDO
F21
AJ27
SWREG_AVSS
ePAD
NC
B26
SWREG_VSSO
ePAD
NC
C01
TCK
R01
NC
C21
TDI
P05
NDRIVE
C25
TDN_0_0
A19
NC
C29
TDN_0_1
A11
NC
D02
TDN_0_2
A07
NC
D28
TDN_0_3
AJ09
NC
F05
TDN_0_4
AJ13
NC
F25
TDN_1_0
C19
NC
NC
NC
NC
Br
NC
oa
AG05
NC
Broadcom®
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Pin List by Signal Name
Pin
Signal
Pin
TDN_1_1
B12
VSS
ePAD
TDN_1_2
C07
VSS
ePAD
TDN_1_3
AH08
VSS
ePAD
TDN_1_4
AG13
XTAL_AVDD
T05
TDN_2_0
B22
XTAL_AVSS
ePAD
TDN_2_1
B14
XTAL_I
T02
TDN_2_2
B04
XTAL_O
R03
TDN_2_3
AH06
TDN_2_4
AH16
TDN_3_0
A23
TDN_3_1
A15
TDN_3_2
C05
TDN_3_3
AJ05
TDN_3_4
AJ17
TDO/EN_8051
P02
TDP_0_0
B18
TDP_0_1
C11
TDP_0_2
B08
TDP_0_3
AH10
TDP_0_4
AH12
TDP_1_0
B20
TDP_1_1
C13
TDP_2_3
TDP_2_4
TDP_3_0
tia
en
fid
dc
AH14
A21
oa
TDP_2_2
AJ07
Br
TDP_2_1
on
B06
TDP_1_3
TDP_2_0
C
om
TDP_1_2
TDP_1_4
l
Signal
A13
A05
AG07
AJ15
B24
TDP_3_1
B16
TDP_3_2
C03
TDP_3_3
AH04
TDP_3_4
AH18
TMS
N03
TRST
N01
VSS
G03
VFB
F23
VSS
ePAD
Broadcom®
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Register Definitions
S e c t i o n 7 : R e g is t e r D e f i n i t i o n s
Register Definition
BCM53125S register sets can be accessed through the programming interfaces described on page 94. The
register space is organized into pages, each containing a certain set of registers. Table 34 lists the pages
defined in BCM53125S. To access a page, the page register (0xFF) is written with the page value. The registers
contained in the page can then be accessed by their addresses. See “Programming Interfaces” on page 94 for
more information.
tia
l
Register Notations
•
RO = Read only
•
LH = Latched high
•
LL = Latched low
•
H = Fixed high
•
L = Fixed low
•
SC = Clear on read
fid
R/W = Read or write
om
C
on
•
en
In the register description tables, the following notation in the R/W column is used to describe the ability to read
or to write:
oa
dc
Reserved bits must be written as the default value and ignored when read.
Page
Br
Global Page Register
Table 34: Global Page Register Map
Description
00h
“Page 00h: Control Registers” on page 144
01h
“Page 01h: Status Registers” on page 163
02h
“Page 02h: Management/Mirroring Registers” on page 167
03h
“Page 03h: Interrupt Control Register” on page 176
04h
“Page 03h: Interrupt Control Register” on page 176
05h
“Page 05h: ARL/VTBL Access Registers” on page 182
06h, 07h
Reserved
08h
Reserved
09h
Reserved
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BCM53125S Data Sheet
Global Page Register
Table 34: Global Page Register Map (Cont.)
Page
Description
0Ah
Reserved
0Bh–0Fh
Reserved
10h–14h
“Page 10h–14h: Internal GPHY MII Registers” on page 193
15h
“Block Address Number (Page 010h–017h: Address 03Eh)” on page 222
16h–1Fh
Reserved
“Page 20h–28h: Port MIB Registers” on page 223
29h–2Fh
Reserved
30h
“Page 30h: QoS Registers” on page 227
31h
“Page 31h: Port-Based VLAN Registers” on page 235
32h
“Page 32h: Trunking Registers” on page 236
33h
Reserved
34h
“Page 34h: IEEE 802.1Q VLAN Registers” on page 237
35h
Reserved
en
tia
l
20h–28h
“Page 36h: DoS Prevent Register” on page 246
37h–3Fh
Reserved
40h
“Page 40h: Jumbo Frame Control Register” on page 249
41h
“Page 41h: Broadcast Storm Suppression Register” on page 250
42h
“Page 42h: EAP Register” on page 258
43h
“Page 43h: MSPT Register” on page 261
44h–6Fh
Reserved
70h
“Page 70h: MIB Snapshot Control Register” on page 263
om
C
on
fid
36h
“Page 71h: Port Snapshot MIB Control Register” on page 264
73h–7Fh
Reserved
80h–83h
Reserved
dc
71h
84h
Reserved
“Page 85h: WAN Interface (Port 5) External PHY MII Registers” on page 264
oa
85h
88h
90h
Reserved
Br
86h–87h
“Page 88h: IMP Port External PHY MII Registers Page Summary” on
page 265
Reserved
91h
“Page 91h: Traffic Remarking Register” on page 272
92h–9Fh
“Page 92h: EEE Control Registers” on page 274
A0h
Reserved
A1h
Reserved
A2h–EFh
Reserved
Maps to all pages
“Global Registers” on page 279
Broadcom®
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BCM53125S Data Sheet
Page 00h: Control Registers
Page 00h: Control Registers
Table 35: Control Registers (Page 00h)
Address
Bits
Register Name
00h–05h
8/port
“Port Traffic Control Register (Page 00h: Address 00h)” on page 145
06h–07h
8
Reserved
08h
8
“IMP Port Control Register (Page 00h: Address 08h)” on page 146
09h–0Ah
8
Reserved
8
“Switch Mode Register (Page 00h: Address 0Bh)” on page 147
0Ch–0Dh
16
Reserved
0Eh
8
“IMP Port State Override Register (Page 00h: Address 0Eh)” on page 147
0Fh
8
“LED Refresh Register (Page 00h: Address 0Fh)” on page 148
10h–11h
16
“LED Function 0 Control Register (Page 00h: Address 10h)” on page 149
12h–13h
16
“LED Function 1 Control Register (Page 00h: Address 12h)” on page 150
14h–15h
16
“LED Function Map Register (Page 00h: Address 14h–15h)” on page 150
16h–17h
16
“LED Enable Map Register (Page 00h: Address 16h–17h)” on page 150
18h–19h
16
“LED Mode Map 0 Register (Page 00h: Address 18h–19h)” on page 151
1Ah–1Bh
16
“LED Mode Map 1 Register (Page 00h: Address 1Ah–1Bh)” on page 151
1Ch–1Eh
–
Reserved
1Fh
8
Reserved
20h
–
Reserved
21h
8
“Port Forward Control Register (Page 00h: Address 21h)” on page 152
22h–23h
–
Reserved
24h–25h
16
“Protected Port Selection Register (Page 00h: Address 24h–25h)” on page 153
26h–27h
16
“WAN Port Select Register (Page 00h: Address 26h–27h)” on page 153
28h–2Bh
32
“Pause Capability Register (Page 00h: Address 28h–2Bh)” on page 153
2Ch–2Eh
–
Reserved
2Fh
8
30h
–
31h
8
32h–33h
16
34h–35h
16
“Multicast Lookup Failed Forward Map Register (Page 00h: Address 34h–35h)” on
page 156
36h–37h
16
“MLF IPMC Forward Map Register (Page 00h: Address 36h–37h)” on page 156
38h–39h
16
“Pause Pass Through for RX Register (Page 00h: Address 38h–39h)” on page 157
3Ah–3Bh
16
“Pause Pass Through for TX Register (Page 00h: Address 3Ah–3Bh)” on page 157
3Ch–3Dh
16
“Disable Learning Register (Page 00h: Address 3Ch–3Dh)” on page 157
3Eh–3Fh
16
“Software Learning Register (Page 00h: Address 3Eh–3Fh)” on page 158
40h–49h
–
Reserved
4Ah–4Bh
–
Reserved
oa
dc
om
C
on
fid
en
tia
l
0Bh
“Reserved Multicast Control Register (Page 00h: Address 2Fh)” on page 154
Br
Reserved
Reserved
“Unicast Lookup Failed Forward Map Register (Page 00h: Address 32h)” on
page 155
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BCM53125S Data Sheet
Page 00h: Control Registers
Table 35: Control Registers (Page 00h) (Cont.)
Address
Bits
Register Name
4Ch–57h
–
Reserved
8/port
“Port State Override Register (Page 00h: Address 58h)” on page 158
60h–65h
–
Reserved
66h–74h
–
Reserved
75h
–
“MDIO WAN Port Address Register (Page 00h: Address 75h)” on page 160
78h
–
“MDIO IMP PORT Address Register (Page 00h: Address 78h)” on page 160
79h
–
“Software Reset Control Register (Page 00h: Address 79h)” on page 160
7Ah–7Fh
–
Reserved
80h
8
“Pause Frame Detection Control Register (Page 00h: Address 80h)” on page 161
81h–87h
–
Reserved
88h
8
“Fast-Aging Control Register (Page 00h: Address 88h)” on page 161
89h
8
“Fast-Aging Port Control Register (Page 00h: Address 89h)” on page 161
8Ah–8Bh
16
“Fast-Aging VID Control Register (Page 00h: Address 8Ah–8Bh)” on page 161
F0h–F7h
8
“SPI Data I/O Register (Global, Address F0h)” on page 280, bytes 0-7
F8h–FDh
–
Reserved
8Ch–EFh
–
Reserved
FEh
8
“SPI Status Register (Global, Address FEh)” on page 280
FFh
8
“Page Register (Global, Address FFh)” on page 280
C
on
fid
en
tia
l
58h–5Dh
om
Port Traffic Control Register (Page 00h: Address 00h)
.
01h
02h
03h
04h
05h
oa
00h
Br
Address
dc
Table 36: Port Traffic Control Register Address Summary
Description
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
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BCM53125S Data Sheet
Page 00h: Control Registers
Table 37: Port Control Register (Page 00h: Address 00h–05h)
BIt
Name
Description
Default
7:5
STP_STATE[2:0] R/W
CPU writes the current computed states of its spanning HW_FWDG_EN
tree algorithm for a given port.
(controlled by
000 = No spanning tree (default for unmanaged mode). strap option)
001 = Disabled state (default for managed mode).
010 = Blocking state.
011 = Listening state.
100 = Learning state.
101 = Forwarding state.
110–111 = Reserved.
4:2
Reserved
–
–
1
TX_DISABLE
R/W
0 = Enable the transmit function of the port at the MAC 0
level.
1 = Disable the transmit function of the port at the MAC
level.
0
RX_DISABLE
R/W
0 = Enable the receive function of the port at the MAC
level.
1 = Disable the receive function of the port at the MAC
level.
000
en
tia
l
R/W
on
fid
0
C
IMP Port Control Register (Page 00h: Address 08h)
Name
R/W
7:5
Reserved
R/W
4
RX_UCST_EN
R/W
3
RX_MCST_EN
Description
Default
–
–
dc
Bit
om
Table 38: IMP Port Control Register (Page 00h: Address 08h)
Br
oa
0
Receive unicast enable.
Allow unicast frames to be forwarded to the IMP, when
the IMP is configured as the frame management port,
and the frame was matching address table entry.
When cleared, unicast frames that meet the mirror
ingress/egress rules are forwarded to the frame
management port. Ignored if the IMP is not selected
as the Frame Management Port.
R/W
0
Receive multicast enable.
Allow multicast frames to be forwarded to the IMP,
when the IMP is configured as the Frame
Management Port, and the frame was flooded due to
no matching address table entry.
When cleared, multicast frames that meet the mirror
ingress/egress rules are forwarded to the frame
management port.
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BCM53125S Data Sheet
Page 00h: Control Registers
Table 38: IMP Port Control Register (Page 00h: Address 08h) (Cont.)
Bit
Name
R/W
Description
Default
2
RX_BCST_EN
R/W
0
Receive broadcast enable.
Allow broadcast frames to be forwarded to the IMP,
when the IMP is configured as the Frame
Management Port.
When cleared, multicast frames that meet the mirror
ingress/egress rules are forwarded to the frame
management port.
1:0
Reserved
R/W
–
0
Switch Mode Register (Page 00h: Address 0Bh)
tia
l
Table 39: Switch Mode Register (Page 00h: Address 0Bh)
Name
R/W
Description
7:2
Reserved
RO
–
1
SW_FWDG_EN
R/W
HW_FWDG_EN
Software forwarding enable.
SW_FWDG_EN = 1: Frame forwarding is enabled.
SW_FWDG_EN = 0: Frame forwarding is disabled.
Managed switch implementations should be
configured to disable forwarding on power-on to
allow the processor to configure the internal
address table and other parameters before frame
forwarding is enabled.
0
SW_FWDG_MODE R/W
Default
000001
C
on
fid
en
Bit
HW_FWDG_EN
oa
dc
om
Software forwarding mode.
0 = Unmanaged mode.
1 = Managed mode.
The ARL treats reserved multicast addresses
differently depending on this selection.
Br
IMP Port State Override Register (Page 00h: Address 0Eh)
Table 40: IMP Port State Override Register (Page 00h: Address 0Eh)
Bit
Name
R/W
Description
Default
7
MII_SW_OR
R/W
MII software override.
0 = Use MII hardware pin status.
1 = Use contents of this register.
0
6
Reserved
R/W
Reserved.
0
5
Tx Flow Control Capability RO
Link partner flow control capability.
0 = Not PAUSE capable.
1 = PAUSE capable.
0
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BCM53125S Data Sheet
Page 00h: Control Registers
Table 40: IMP Port State Override Register (Page 00h: Address 0Eh) (Cont.)
Description
Default
RX Flow Control Capability R/W
Link partner flow control capability.
0 = Not PAUSE-capable.
1 = PAUSE-capable.
0
3:2
SPEED
R/W
Speed.
00 = 10 Mbps.
01 = 100 Mbps.
10 = 1000 Mbps.
11 = 200 Mbps.
10
1
FDX
R/W
Full duplex.
0 = Half duplex.
1 = Full duplex.
1
0
LINK
R/W
Link status.
0 = Link fail.
1 = Link pass.
0
l
4
R/W
tia
Name
en
Bit
fid
LED Control Register (Page 00h: Address 0Fh–1Bh)
on
Table 41: LED Control Register Address Summary
Description
C
Address
0Fh
LED refresh control register
LED function 0 control register
om
10h–11h
12h–13h
LED function 1 control register
14h–15h
LED function map control register
dc
16h–17h
18h–19h
oa
1Ah–1Bh
LED enable map register
LED mode map 0 register
LED mode map 1 register
Br
LED Refresh Register (Page 00h: Address 0Fh)
Table 42: LED Refresh Register (Page 00h: Address 0Fh)
Bit
Name
R/W
Description
Default
7
LED_EN
R/W
Enable LED.
1
6
POST_EXEC
R/W
Write 1 to restart POST.
0
5
POST_PSCAN_EN
R/W
When enabled, switch scans the port during the 0
POST period.
4
POSt_Cable_diag_en
R/W
Enable cable diagnostics display during POST
0
3
Normal_Cable_diag_en
R/W
Enable cable diagnostics display in normal
mode.
0
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BCM53125S Data Sheet
Page 00h: Control Registers
Table 42: LED Refresh Register (Page 00h: Address 0Fh) (Cont.)
Name
R/W
Description
Default
2:0
LED_Refresh_rate
R/W
LED refresh count register (that is, LED blinking 3h
rate).
Refresh time = (N + 1) × 10 ms.
• 000 = Reserved.
001 = 20 ms/25 Hz.
•
010 = 30 ms/16 Hz.
•
011 = 40 ms/12 Hz.
•
100 = 50 ms/10 Hz.
•
101 = 60 ms/8 Hz.
•
110 = 70 ms/7 Hz.
•
111 = 80 ms/6 Hz.
tia
•
l
Bit
en
LED Function 0 Control Register (Page 00h: Address 10h)
fid
Table 43: LED Function 0 Control Register (Page 00h: Address 10h–11h)
Name
R/W
Description
15:0
LED_Function
R/W
The following is the list of functions
assigned to each bit:
15 = PHYLED3.
14 = Reserved.
13 = 1G/ACT.
12 = 10/100M/ACT.
11 = 100M/ACT.
10 = 10M/ACT.
9 = SPD1G.
8 = SPD100M.
7 = SPD10M.
6 = DPX/COL.
5 = LNK/ACT.
4 = COL.
3 = ACT.
2 = DPX.
1 = LNK.
0 = PHYLED4.
Default
LED MODE[1:0] = 00: 16'h0121.
LED MODE[1:0] = 01: 16'h0C41.
LED MODE[1:0] = 10: 16'h0124.
LED MODE[1:0] = 11: 16'h0C04.
Br
oa
dc
om
C
on
Bit
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BCM53125S Data Sheet
Page 00h: Control Registers
LED Function 1 Control Register (Page 00h: Address 12h)
Table 44: LED Function 1 Control Register (Page 00h: Address 12h–13h)
Name
R/W
Description
Default
15:0
LED_Function
R/W
The following is the list of functions assigned to
each bit:
15 = PHYLED3.
14 = Reserved.
13 = 1G/ACT.
12 = 10/100M/ACT.
11 = 100M/ACT.
10 = 10M/ACT.
9 = SPD1G.
8 = SPD100M.
7 = SPD10M.
6 = DPX/COL.
5 = LNK/ACT.
4 = COL.
3 = ACT.
2 = DPX.
1 = LNK.
0 = PHYLED4.
LED MODE[1:0] = 00:
16'h0321
LED MODE[1:0] = 01:
16'h3041
LED MODE[1:0] = 10:
16'h0324
LED MODE[1:0] = 11:
16'h2C04
C
on
fid
en
tia
l
Bit
om
LED Function Map Register (Page 00h: Address 14h–15h)
Table 45: LED Function Map Register (Page 00h: Address 14h–15h)
Name
R/W
Description
Default
–
0
dc
BIt
Reserved
LED_FUNC_MAP
R/W
oa
15:9
8:0
Br
R/W
Per port select function bit. Each port LED
1FFh
follows the function table specified for each port.
1 = Select Function 1.
0 = Select Function 0.
Bits [4:0] correspond to ports [4:0].
Bit 5 corresponds to port 5 in serial LED
interface.
LED Enable Map Register (Page 00h: Address 16h–17h)
Table 46: LED Enable Map Register (Page 00h: Address 16h–17h)
BIt
Name
R/W
Description
Default
15:9
Reserved
R/W
–
0
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BCM53125S Data Sheet
Page 00h: Control Registers
Table 46: LED Enable Map Register (Page 00h: Address 16h–17h) (Cont.)
BIt
Name
R/W
Description
Default
8:0
LED_EN_MAP
R/W
Per-port enable bit.
1 = Enable.
0 = Disable.
Bits [4:0] correspond to ports [4:0].
Bit 5 corresponds to port 5 in serial LED
interface.
9'h1F
LED Mode Map 0 Register (Page 00h: Address 18h–19h)
Table 47: LED Mode Map 0 Register (Page 00h: Address 18h–19h)
Name
R/W
Description
15:9
Reserved
R/W
–
8:0
LED_MODE_MAP0
R/W
Combine with LED_MODE_MAP1 to decide
per port LED output mode.
Bits [4:0] correspond to ports [4:0].
Bit 5 corresponds to port 5 in serial LED
interface.
Default
0
1FFh
on
fid
en
tia
l
BIt
C
LED Mode Map 1 Register (Page 00h: Address 1Ah–1Bh)
BIt
Name
om
Table 48: LED Function Map 1 Control Register (Page 00h: Address 1Ah–1Bh)
R/W
Reserved
LED_MODE_MAP1
–
0
R/W
Per port select function bit.
LED_FUNC_MAP[1:0]:
00 = LED off
01 = LED on
10 = LED blinking
11 = LED auto
1FFh
oa
Br
Default
R/W
dc
15:9
8:0
Description
See “LED Interfaces” on page 117 for more information.
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BCM53125S Data Sheet
Page 00h: Control Registers
Port Forward Control Register (Page 00h: Address 21h)
Table 49: Port Forward Control Register (Page 00h: Address 21h)
Name
R/W
Description
Default
7
MCST_DLF_FWD_EN
R/W
Multicast Forward Enable when ARL Miss.
1 = Forward multicast lookup failed packets
according to multicast lookup failed forward map
register (page 00h: address 34h).
0 = Flood multicast lookup failed packets to all the
ports.
0
6
UCST_DLF_FWD_EN
R/W
0
Unicast Forward Enable when ARL Miss.
1 = Forward unicast lookup failed packets according
to multicast lookup failed forward map register (page
00h: address 32h).
0 = Flood unicast lookup failed packets to all the
ports.
5:3
Reserved
R/W
–
2
INRANGE_ERR_DIS
R/W
0
In-Range Error Discard.
When bit = 1, the ingress port will discard the frames
with Length field mismatch the frame length.
Following is the definition of InRangeErrors.
In-Range Errors Frames: The frames received with
good CRC and one of the following:
• The value of μs is between 46 and 1500
inclusive, and does not match the number of
(MAC Client Data + PAD) data octets received.
–
om
C
on
fid
en
tia
l
BIt
dc
•
OUTRANGE_ERR_DIS R/W
0
Reserved
Br
oa
1
R/W
The value of μs is less than 46, and the number
of data octets received is greater than 46(which
does not require padding).
0
Out of Range Error Discard.
When bit =1, the ingress port will discard the frames
with length field between 1500 and 1536 (exclude
1500 and 1536) with good CRC. This option only
controls the length field checking but not the frame
length checking.
–
1
See “Egress PCP Remarking” on page 57 for more information.
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BCM53125S Data Sheet
Page 00h: Control Registers
Protected Port Selection Register (Page 00h: Address 24h–25h)
Table 50: Protected Port Selection Register (Page 00h: Address 24h–25h)
BIt
Name
R/W
Description
Default
15:9
Reserved
RO
–
0
8:0
Port_Select
R/W
Protected port selection.
0
Bit 8 = IMP port.
Bits [4:0] correspond to ports [4:0], respectively.
1 = Port protected. Cannot send/receive to other protected
ports.
0 = Port is not protected.
tia
l
See “Protected Ports” on page 48 for more information.
en
WAN Port Select Register (Page 00h: Address 26h–27h)
fid
Table 51: WAN Port Select Register (Page 00h: Address 26h–27h)
Name
R/W
Description
15:10
Reserved
RO
–
9
Reserved
R/W
–
8:6
Reserved
R/W
–
5:0
WAN_Port_MAP
R/W
Set assigned WAN port to 1.
0
Bits [5:0] correspond to ports [5:0], respectively.
Port 5 can be selected as a WAN port only in
En_IMP_Port = 10 of Global Management Configuration
Register (Page 02h: Address 00h).
Default
0
–
–
dc
om
C
on
BIt
oa
Pause Capability Register (Page 00h: Address 28h–2Bh)
BIt
Name
31:24
Br
Table 52: Pause Capability Register (Page 00h: Address 28h–2Bh)
R/W
Description
Default
Reserved
RO
–
0
23
EN_OVeRIDE
R/W
Forces the content of this register setting to be used
over the auto negotiation result.
0
22:18
Reserved
–
–
–
17:9
EN_RX_PAUSE_CAP
–
Enabling the receive pause capability.
Bit 17 = IMP port.
Bits [14:9] correspond to ports [5:0], respectively.
0h
8:0
EN_TX_PAUSE_CAP
–
Enables the transmit pause capability.
Bit 8 = IMP port.
Bits [5:0] correspond to ports [5:0], respectively.
0h
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BCM53125S Data Sheet
Page 00h: Control Registers
Reserved Multicast Control Register (Page 00h: Address 2Fh)
BIt
Name
R/W
Description
7
Multicast Learning
R/W
Multicast learning enable.
0
0 = Do not learn unicast source addresses of frames
that have a reserved multicast destination address.
1 = Learn unicast source addresses even from frames
that have a reserved multicast destination address.
See “Address Management” on page 57 for more
information.
6:5
Reserved
R/W
–
4
En_Mul_4
R/W
Specifies if packets with the destination addresses in 0
the below range are to be forwarded to the appropriate
port or dropped when operating in unmanaged mode.
01-80-C2-00-00-20–01-80-C2-00-00-2F
0 = Forward.
1 = Drop.
3
En_Mul_3
R/W
Specifies if packets with the destination addresses in 0
the below range are to be forwarded to the appropriate
port or dropped when operating in unmanaged mode.
01-80-C2-00-00-11–01-80-C2-00-00-1F
0 = Forward.
1 = Drop.
2
En_Mul_2
R/W
Specifies if packets with the destination address below 0
are to be forwarded to the appropriate port or dropped
when operating in unmanaged mode.
01-80-C2-00-00-10
0 = Forward.
1 = Drop.
1
En_mul_1
dc
Table 53: Reserved Multicast Control Register (Page 00h: Address 2Fh)
Default
0
En_Mul_0
om
C
on
fid
en
tia
l
0
Specifies if packets with the destination addresses in 1
the below range are to be forwarded to the appropriate
port or dropped when operating in unmanaged mode.
01-80-C2-00-00-02–01-80-C2-00-00-0F
0 = Forward.
1 = Drop.
R/W
Specifies if packets with the destination address below 0
are to be forwarded to the appropriate port or dropped
when operating in unmanaged mode.
01-80-C2-00-00-00
0 = Forward.
1 = Drop.
Br
oa
R/W
See “Multicast Addresses” on page 60 for more information.
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BCM53125S Data Sheet
Page 00h: Control Registers
Unicast Lookup Failed Forward Map Register (Page 00h: Address
32h)
Table 54: Unicast Lookup Failed Forward Map Register (Page 00h: Address 32h–33h)
Name
R/W
Description
Default
15:9
Reserved
RO
–
0
8:0
Uni_DLF_MAP
R/W
Unicast lookup failed forward map.
0
Bit 8 = IMP port.
Bits [7:6] reserved.
Bits [5:0] correspond to ports [5:0], respectively.
When the UCST_DLF_FWD_EN bit in “Port Forward
Control Register (Page 00h: Address 21h)” on
page 152 is enabled and a unicast lookup failure
occurs, the ARL table forwards the frame according
to the contents of this register. If this register remains
in default value, the frame is dropped.
0 = Do not forward a unicast lookup failure to this
port.
1 = Forward a unicast lookup failure to this port.
fid
en
tia
l
BIt
Br
oa
dc
om
C
on
See “Unicast Addresses” on page 59 for more information.
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 155
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 00h: Control Registers
Multicast Lookup Failed Forward Map Register (Page 00h: Address
34h–35h)
Table 55: Multicast Lookup Failed Forward Map Register (Page 00h: Address 34h–35h)
Name
R/W
Description
Default
15:9
Reserved
RO
–
0
8:0
MCST_DLF_MAP
R/W
Multicast lookup failed forward map.
0
Bit 8 = IMP port.
Bits [7:6] reserved.
Bits [5:0] correspond to ports [5:0], respectively.
When the MCST_DLF_FWD_EN bit in port forward
control register (Page 00h:Address 21h) is enabled and
a multicast lookup failure occurs, the ARL table
forwards the frame according to the contents of this
register. If this register remains in default value, the
frame is dropped.
0 = Do not forward a multicast lookup failure to this port.
1 = Forward a multicast lookup failure to this port.
fid
en
tia
l
BIt
on
See “Multicast Addresses” on page 60 for more information.
C
MLF IPMC Forward Map Register (Page 00h: Address 36h–37h)
Name
15:9
Reserved
8:0
MLF_IPMC_FWD_MAP
R/W
Description
Default
RO
–
0
R/W
IPMC forward map.
0
Bit 8 = IMP port.
Bits [5:0] correspond to ports [5:0], respectively.
Note: The received pause frames are forwarded
to all ports (flooded), which can cause a halt of all
inputs to all ports.
Br
oa
dc
BIt
om
Table 56: MLF IMPC Forward Map Register (Page 00h: Address 36h–37h)
Note: IP Multicast (IPMC) packets are multicast with the address range 01-00-5e-xx-xx-xx.
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 156
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 00h: Control Registers
Pause Pass Through for RX Register (Page 00h: Address 38h–39h)
Table 57: Pause Pass Through for RX Register (Page 00h: Address 38h–39h)
BIt
Name
R/W
Description
Default
15:8
Reserved
RO
–
0
7:0
IGNORE_Pause frame _RX
R/W
RX pause pass through map.
1 = Ignore IEEE 802.3x.
0 = Comply with IEEE 802.3x pause frame
receiving.
Bits [5:0] correspond to ports [5:0],
respectively.
0
tia
l
Pause Pass Through for TX Register (Page 00h: Address 3Ah–3Bh)
Table 58: Pause Pass Through for TX Register (Page 00h: Address 3Ah–3Bh)
Name
R/W
Description
Default
15:9
Reserved
RO
–
8:0
IGNORE_Pause frame _Tx
R/W
TX pause pass through map.
0
1 = Ignore IEEE 802.3x.
0 = Comply with IEEE 802.3x pause frame
receiving.
Bit 8 = IMP port.
Bits [5:0] correspond to ports [5:0], respectively.
en
BIt
om
C
on
fid
0
Disable Learning Register (Page 00h: Address 3Ch–3Dh)
dc
Table 59: Disable Learning Register (Page 00h: Address 3Ch–3Dh)
Name
15:9
Reserved
8:0
DIS_LEARNING
Br
oa
BIt
R/W
Description
Default
RO
–
0
R/W
1 = Disable learning.
0
0 = Enable learning.
Bit 8 = IMP port.
Bits [7:6] reserved.
Bits [5:0] correspond to ports [5:0], respectively.
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 157
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 00h: Control Registers
Software Learning Register (Page 00h: Address 3Eh–3Fh)
Table 60: Software Learning Control Register (Page 00h: Address 3Eh–3Fh)
Bit
Name
R/W
Description
Default
Reserved
RO
Reserved
–
8:0
SW_LEARN_CNTL
R/W
1 = Software learning control enabled.
0
The behaviors are as follows.
Forwarding behavior: Incoming packet with
unknown SA will be copied to CPU port.
Learning behavior: Allow S/W to decide whether
incoming packet learn or not. In S/W learning
mode, the H/W learning mechanism will be
disabled automatically.
Refreshed behavior: Allow refreshed
mechanism to operate properly even through
the H/W learning had been disabled.
0 = Software learning control disabled.
Forwarding/Learning/Refreshed behavior to
keep hardware operation.
Bit 8 = IMP port.
Bits [7:6] reserved.
Bits [5:0] correspond to ports [5:0].
on
fid
en
tia
l
15:9
C
Port State Override Register (Page 00h: Address 58h)
.
om
Table 61: Port State Override Register Address Summary
Address
dc
58h
59h
5Ch
5Dh
Port 2
Port 3
Port 4
Br
5Bh
Port 0
Port 1
oa
5Ah
Description
Port 5
Table 62: Port State Override Register (Page 00h: Address 58h–5Fh)
BIt
Name
R/W
Description
Default
–
7
Reserved
R/W
–
6
Software Override
R/W
Writing 1 to this bit allows the values of the bits [5:0] 0
to be written to the external PHY. Writing 0 to this
bit prevents these values from overriding the
present external PHY conditions.
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 158
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 00h: Control Registers
Table 62: Port State Override Register (Page 00h: Address 58h–5Fh) (Cont.)
Name
R/W
Description
Default
5
Tx Flow Control Enable
R/W
The value of this bit overrides the existing
0
conditions of the external PHY port if bit 6 is written
to 1.
0 = Flow control disabled for transmit traffic.
1 = Flow control enabled for transmit traffic.
4
RX Flow Control Enable
R/W
The value of this bit overrides the existing
0
conditions of the external PHY port if bit 6 is written
to 1.
0 = Flow control disabled for receive traffic.
1 = Flow control enabled for receive traffic.
3:2
Speed
R/W
The value of this bit overrides the existing
10
conditions of the external PHY port if bit 6 is written
to 1.
00 = 10 Mbps.
01 = 100 Mbps.
10 = 1000 Mbps.
11 = 200 Mbps (for Port5 only, Register Address
5Dh).
1
Duplex Mode
R/W
The value of this bit overrides the existing
1
conditions of the external PHY port if bit 6 is written
to 1.
0 = Half duplex.
1 = Full duplex.
0
Link State
R/W
C
on
fid
en
tia
l
BIt
oa
dc
om
The value of this bit overrides the existing
1
conditions of the external PHY port if bit 6 is written
1.
1 = Link-up.
0 = Link-down.
Br
RGMII Timing Delay Register for IMP Port (Page 00h: Address 60h)
Table 63: RGMII Timing Delay Register for IMP Port (Page 00h: Address 60h)
Bit
Name
R/W
Description
Default
7:2
Reserved
RO
Reserved
0
1
EN_RGMII_RX_CLK
R/W
1 = RGMII RX_CLK delay.
0 = RGMII RX_CLK no delay.
0
0
EN_RGMII_TX_CLK
R/W
1 = RGMII TX_CLK delay.
0 = RGMII TX_CLK no delay.
0
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 159
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 00h: Control Registers
RGMII Timing Delay Register for Port 5 (Page 00h, Address 65h)
Table 64: RGMII Timing Delay Register for Port 5 (Page 00h, Address 65h)
Bit
Name
R/W
Description
Default
7:2
Reserved
RO
Reserved
0
1
EN_RGMII_RX_CLK
R/W
1 = RGMII RX_CLK delay.
0 = RGMII RX_CLK no delay.
0
0
EN_RGMII_TX_CLK
R/W
1 = RGMII TX_CLK delay.
0 = RGMII TX_CLK no delay.
0
MDIO WAN Port Address Register (Page 00h: Address 75h)
Name
R/W
Description
7:5
Reserved
RO
–
4:0
WAN_MDIO_ADDRESS R/W
en
BIt
tia
l
Table 65: MDIO WAN Port Address Register (Page 00h: Address 75h)
0
15h
fid
WAN port MDIO SCAN address
Default
on
MDIO IMP PORT Address Register (Page 00h: Address 78h)
Name
R/W
7:5
Reserved
RO
4:0
IMP_MDIO_Address
Description
Default
–
0
IMP PORT MDIO address
18h
om
BIt
C
Table 66: MDIO IMP PORT Address Register (Page 00h: Address 78h)
R/W
oa
dc
Software Reset Control Register (Page 00h: Address 79h)
Table 67: Software Reset Control Register (Page 00h: Address 79h)
Name
R/W
Description
7
SW_RST
R/W
Software reset (bit 4 EN_SW_RST must be enabled –
as well).
1 = Activate reset.
0 = Clear reset.
6:5
Reserved
–
–
–
4
EN_SW_RST
R/W
Enable software reset.
0
3:0
Reserved
R/W
–
–
Br
BIt
Default
Note: A software reset samples the strap pin states in the same way as a hardware reset.
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 160
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 00h: Control Registers
Pause Frame Detection Control Register (Page 00h: Address 80h)
Table 68: Pause Frame Detection Control Register (Page 00h: Address 80h)
BIt
Name
R/W
Description
Default
7:1
Reserved
RO
–
0
0
Pause_ignore_Da
R/W
0 = Check DA field on pause frame detection.
1 = Ignore DA field on pause frame detection.
0
Fast-Aging Control Register (Page 00h: Address 88h)
Name
R/W
Description
Default
7
Fast_Age_Start/Done
R/W
Set bit to 1 triggers the fast aging process.
When the fast aging process is done, this bit is
cleared to 0.
0
6
Reserved
–
–
–
5
EN_AGE_MCAST
R/W
Enable Aging Multicast Entry.
0
1 = Aging multicast Entries in ARL Table.
0 = Disable Aging Multicast Entries in ARL Table.
Note: The EN_AGE_MCAST and the EN_AGE_Port
can not enable (set to 1) at the same time.
4
EN_AGE_SPT
R/W
When set, check spanning tree ID.
–
3
EN_AGE_VLAN
R/W
When set, check VLAN ID.
–
2
EN_AGE_Port
R/W
When set, check port ID.
–
1
EN_AGE_Dynamic
R/W
When set, age out dynamic entry.
–
0
EN_AGE_Static
R/W
When set, age out static entry.
–
dc
om
C
on
fid
tia
l
BIt
en
Table 69: Fast-Aging Control Register (Page 00h: Address 88h)
oa
Fast-Aging Port Control Register (Page 00h: Address 89h)
Br
Table 70: Fast-Aging Port Control Register (Page 00h: Address 89h)
Bit
Name
R/W
Description
Default
7:4
Reserved
R/W
–
0
3:0
Fast Age Single Port
R/W
Fast age single port select.
Writing bits [3:0] selects the port to be fast-aged.
0
Fast-Aging VID Control Register (Page 00h: Address 8Ah–8Bh)
Table 71: Fast-Aging VID Control Register (Page 00h: Address 8Ah–8Bh)
Bit
Name
R/W
Description
Default
15:12
Reserved
R/W
–
0
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 161
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 00h: Control Registers
Table 71: Fast-Aging VID Control Register (Page 00h: Address 8Ah–8Bh) (Cont.)
Name
R/W
Description
Default
11:0
Fast Age Single VID
R/W
Fast age single VID select.
0
Writing bits [11:0] selects the VID to be fast-aged.
Br
oa
dc
om
C
on
fid
en
tia
l
Bit
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 162
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 01h: Status Registers
Page 01h: Status Registers
Table 72: Status Registers (Page 01h)
Bits
Register Name
00h–01h
16
“Link Status Summary (Page 01h: Address 00h)” on page 163
02h–03h
16
“Link Status Change (Page 01h: Address 02h)” on page 164
04h–07h
32
“Port Speed Summary (Page 01h: Address 04h)” on page 164
08h–09h
16
“Duplex Status Summary (Page 01h: Address 08h)” on page 164
0Ah–0Dh
32
“Pause Status Summary (Page 01h: Address 0Ah)” on page 165
0Eh–0Fh
16
“Source Address Change Register (Page 01h: Address 0Eh)” on
page 165
10h–45h
48/port
“Last Source Address Register (Page 01h: Address 10h)” on page 166
46h–EFh
–
Reserved
F0h–F7h
8
“SPI Data I/O Register (Global, Address F0h)” on page 280, bytes 0–7
F8h–FDh
–
Reserved
FEh
8
“SPI Status Register (Global, Address FEh)” on page 280
FFh
8
“Page Register (Global, Address FFh)” on page 280
fid
en
tia
l
Address
on
Link Status Summary (Page 01h: Address 00h)
R/W
15:9
Reserved
RO
8:0
LINK_STATUS
RO
Description
Default
–
0
Link status.
Bit 8 = IMP port.
Bits [5:0] correspond to ports [5:0], respectively.
0 = Link fail.
1 = Link pass.
0
om
Name
Br
oa
dc
BIt
C
Table 73: Link Status Summary Register (Page 01h: Address 00h–01h)
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 163
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 01h: Status Registers
Link Status Change (Page 01h: Address 02h)
Table 74: Link Status Change Register (Page 01h: Address 02h–03h)
Name
R/W
Description
Default
15:9
Reserved
RO
–
0
8:0
LINK_STATUS_CHANGE
RO
Link status change.
Bit 8 = IMP port.
Bits [5:0] correspond to ports [5:0], respectively.
Upon change of link status, a bit remains set until
cleared by a read operation.
0 = Link status constant.
1 = Link status change.
0
tia
Port Speed Summary (Page 01h: Address 04h)
l
BIt
en
Table 75: Port Speed Summary Register (Page 01h: Address 04h–07h)
Name
R/W
Description
31:18
Reserved
PO
Reserved
17:0
PORT_SPEED
RO
Port speed.
The speed of each port is reported based on the mapping
below:
• bits [17:16] = IMP port.
Default
0
0
C
on
fid
BIt
bits [15:12] = Reserved.
•
bits [11:10] = Port 5.
•
bits [9:8] = Port 4.
•
bits [7:6] = Port 3.
•
bits [5:4] = Port 2.
•
bits [3:2] = Port 1.
•
bits [1:0] = Port 0.
Br
oa
dc
om
•
The value of the bits are:
• 00 = 10 Mbps.
•
01 = 100 Mbps.
•
10 = 1000 Mbps.
•
11 = 200 Mbps (for IMP and Port5 only).
Duplex Status Summary (Page 01h: Address 08h)
Table 76: Duplex Status Summary Register (Page 01h: Address 08h–09h)
BIt
Name
R/W
Description
Default
15:9
Reserved
RO
–
0
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 164
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 01h: Status Registers
Table 76: Duplex Status Summary Register (Page 01h: Address 08h–09h) (Cont.)
BIt
Name
R/W
Description
Default
8:0
DUPLEX_STATE
RO
Duplex state.
Bit 8 = IMP port.
Bits [5:0] correspond to ports [5:0], respectively.
0 = Half duplex.
1 = Full duplex.
1FFh
Pause Status Summary (Page 01h: Address 0Ah)
Table 77: PAUSE Status Summary Register (Page 01h: Address 0Ah–0Dh)
R/W
Description
Default
31:18
Reserved
RO
17:9
RECEIVE_PAUSE_STATE RO
Pause state. Receive pause capability.
120h
Bit 17 = IMP port.
Bits [14:9] correspond to ports [5:0], respectively.
0 = Disabled.
1 = Enabled.
Reserved
0
8:0
TRANSMIT_PAUSE_STAT RO
E
Transmit pause capability.
Bit 8 = IMP port.
Bits [5:0] correspond to ports [5:0], respectively.
0 = Disabled.
1 = Enabled.
tia
l
Name
om
C
on
fid
en
BIt
dc
Source Address Change Register (Page 01h: Address 0Eh)
oa
Table 78: Source Address Change Register (Page 01h: Address 0Eh–0Fh)
Name
15:9
Reserved
8:0
SRC_ADDR_CHANGE
Br
BIt
R/W
Description
Default
RO
–
0
RC
Source address change.
0
Bit 8 = IMP port.
Bits [4:0] correspond to ports [4:0], respectively.
The value of this bit is 1 if a change in the source
address is detected on the given port.
The bit remains set until cleared by a read
operation.
0 = No change in source address since last read.
1 = Source address has changed since last read.
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 165
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 01h: Status Registers
Last Source Address Register (Page 01h: Address 10h)
.
Table 79: Last Source Address Register Address Summary
Address
Description
10h–15h
Port 0
16h–1Bh
Port 1
1Ch–21h
Port 2
22h–27h
Port 3
28h–2Dh
Port 4
Port 5
34h–39h
Reserved
3Ah–3Fh
Reserved
40h–45h
IMP port
tia
l
2Eh–33h
en
Table 80: Last Source Address (Page 01h: Address 10h–45h)
Name
R/W
Description
Default
47:0
LAST_SOURCE_ADD
RO
The 48-bit source address detected on the last 0
packet ingressed.
Br
oa
dc
om
C
on
fid
BIt
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 166
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 02h: Management/Mirroring Registers
Page 02h: Management/Mirroring Registers
Bits
Register Name
00h
8
“Global Management Configuration Register (Page 02h: Address 00h)”
on page 168
01h–02h
–
Reserved
03h
8
“Broadcom Header Control Register (Page 02h: Address 03h)” on
page 168
04h–05h
16
“RMON MIB Steering Register (Page 02h: Address 04h)” on page 169
06h–09h
32
“Aging Time Control Register (Page 02h: Address 06h)” on page 169
0Ah–0Fh
–
Reserved
10h–11h
16
“Mirror Capture Control Register (Page 02h: Address 10h)” on page 169
12h–13h
16
“Ingress Mirror Control Register (Page 02h: Address 12h)” on page 170
14h–15h
16
“Ingress Mirror Divider Register (Page 02h: Address 14h)” on page 171
16h–1Bh
48
“Ingress Mirror MAC Address Register (Page 02h: Address 16h)” on
page 171
1Ch–1Dh
16
“Egress Mirror Control Register (Page 02h: Address 1Ch)” on page 172
1Eh–1Fh
16
“Egress Mirror Divider Register (Page 02h: Address 1Eh)” on page 173
20h–25h
48
“Egress Mirror MAC Address Register (Page 02h: Address 20h)” on
page 173
26h–EFh
–
Reserved
30h–33h
8
Device ID number
34h–3Fh
–
50h–53h
32
F0h–F7h
8
F8h–FDh
–
FEh
FFh
tia
en
fid
on
C
Revision ID number
Reserved
dc
–
“High-Level Protocol Control Register (Page 02h: Address 50h–53h)” on
page 174
oa
8
41h–4Fh
Reserved
Br
40h
l
Address
om
Table 81: Aging/Mirroring Registers (Page 02h)
“SPI Data I/O Register (Global, Address F0h)” on page 280, bytes 0–7
Reserved
8
“SPI Status Register (Global, Address FEh)” on page 280
8
“Page Register (Global, Address FFh)” on page 280
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 167
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 02h: Management/Mirroring Registers
Global Management Configuration Register (Page 02h: Address 00h)
Table 82: Global Management Configuration Register (Page 02h: Address 00h)
Name
R/W
Description
Default
7:6
En_IMP_Port
R/W
00
IMP port enable.
00 = No frame management port.
01 = Reserved.
10 = Enable IMP port only. All traffic to CPU from LAN
and WAN ports will be forwarded to IMP port.
11 = Enable Dual-IMP ports (both IMP port and Port5).
All traffic to CPU from LAN ports will be forwarded to
IMP port and all traffic from WAN ports will be forwarded
to Port 5.
These bits are ignored when SW_FWD_MODE =
Unmanaged in the “Switch Mode Register (Page 00h:
Address 0Bh)” on page 147.
5.2
Reserved
–
–
1
En_RX_BPDU
R/W
0
Receive BPDU enable.
Enables all ports to receive BPDUs and forwards to the
IMP port. This bit must be set to globally allow BPDUs
to be received.
0
Reset MIB
R/W
0
Reset MIB counters.
Resets all MIB counters for all ports to 0 (pages 20h–
28h). This bit must be set and then cleared in
successive write cycles to activate the reset operation.
–
om
C
on
fid
en
tia
l
Bit
Broadcom Header Control Register (Page 02h: Address 03h)
dc
Table 83: Broadcom Tag Control Register (Page 02h: Address 03h)
Name
R/W
7:2
Reserved
1:0
BRCM_HDR_EN
Description
Default
RO
–
0
R/W
Broadcom tag enable for GMII port.
Bit 1 = Enable BRCM header for GMII port (port 5).
• 1 = Additional header information is inserted into the
original frame, between original SA field and type/
length fields. The tag includes the BRCM tag field.
11
Br
oa
Bit
•
0 = Without additional header information.
Bit 0 = Enable BRCM header for IMP port.
• 1 = Additional header information is inserted into the
original frame, between original SA field and type/
length fields. The tag includes the BRCM tag field.
•
0 = Without additional header information.
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 02h: Management/Mirroring Registers
RMON MIB Steering Register (Page 02h: Address 04h)
Table 84: RMON MIB Steering Register (Page 02h: Address 04h–05h)
Name
R/W
Description
Default
15:9
Reserved
R/W
–
0
8:0
Override RMON
Receive
R/W
0
Override RMON receive.
Forces the RMON packet size bucket counters from the
normal default of snooping on the receive side of the MAC
to the transmit side. This allows the RMON bucket counters
to snoop either transmit or receive, allowing full-duplex
MAC support.
Bit 8 = IMP port.
Bits [5:0] correspond to ports [5:0], respectively.
l
Bit
tia
Aging Time Control Register (Page 02h: Address 06h)
en
Table 85: Aging Time Control Register (Page 02h: Address 06h–09h)
Name
R/W
Description
31:21
Reserved
RO
–
20
Age Change
R/W
Age change enable.
1 = Set age time using bits [19:0].
0 = Age time default 300 seconds.
19:0
AGE_TIME
R/W
300d
Specifies the aging time in seconds for dynamically
learned addresses. Maximum age time is 1,048,575s.
Setting the AGE_TIME to 0 disables the aging process.
For more information on ARL table aging, see “Address
Aging” on page 63.
Default
–
0
dc
om
C
on
fid
BIt
oa
Mirror Capture Control Register (Page 02h: Address 10h)
BIt
Name
15
Br
Table 86: Mirror Capture Control Register (Page 02h: Address 10h–11h)
R/W
Description
Default
Mirror Enable
R/W
Global mirror enable.
0 = Disable mirror capture feature.
1 = Enable mirror capture feature.
0
14
BLK_NOT_MIR
R/W
When enabled, all traffic to MIRROR_CAPTURE_PORT 0
is blocked, except for mirror traffic. Nonmirror traffic is
disabled.
0 = No traffic blocking on mirror capture port.
1 = Traffic to mirror capture port blocked unless mirror
traffic.
13:4
Reserved
RO
–
Broadcom®
March 11, 2016 • 53125S-DS06-R
0
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 02h: Management/Mirroring Registers
Table 86: Mirror Capture Control Register (Page 02h: Address 10h–11h) (Cont.)
BIt
Name
R/W
Description
Default
3:0
Capture Port
R/W
Mirror capture port ID.
Binary value identifies the single unique port that is
designated as the port where all ingress and/or egress
traffic is mirrored.
0
For additional information about port mirroring, see “Port Mirroring” on page 48.
Ingress Mirror Control Register (Page 02h: Address 12h)
Table 87: Ingress Mirror Control Register (Page 02h: Address 12h–13h)
15:14
IN_MIRROR_FILTER R/W
13
IN_DIV_EN
Description
l
R/W
Default
tia
Name
Ingress mirror filter.
0
Filters frames to be forwarded to the mirror capture port,
specified in “Mirror Capture Control Register (Page 02h:
Address 10h)” on page 169.
00 = Mirror all ingress frames.
01 = Mirror all ingress frames with DA =
IN_MIRROR_MAC.
10 = Mirror all ingress frames with SA =
IN_MIRROR_MAC.
11 = Reserved.
IN_MIRROR_MAC is specified in “Ingress Mirror MAC
Address Register (Page 02h: Address 16h)” on page 171.
om
C
on
fid
en
BIt
0
Ingress divider enable.
th
The ingress divider mirrors every n ingress frame that
has passed through the IN_MIRROR_FILTER (n
represents the IN_MIRROR_DIV defined in “Ingress
Mirror Divider Register (Page 02h: Address 14h)” on
page 171).
0 = Disable ingress divider feature.
1 = Enable ingress divider feature.
12:9
Br
oa
dc
R/W
Reserved
R/W
–
8:0
IN_MIRROR_MASK
R/W
0
Ingress mirror port mask.
Bit 8 = IMP port.
Bits [5:0] correspond to ports [5:0], respectively.
Ports with the corresponding bit set to 1 have ingress
frames mirrored to the MIRROR_CAPTURE_PORT. While
multiple ports can be set as an Ingress Mirror port, severe
congestion and/or frame loss may occur if excessive
bandwidth from the ingress mirrored port (s) is directed to
the MIRROR_CAPTURE_PORT. Setting a mirror filter
using bits [15:14] or divider using bit 13 may be helpful.
0
For additional information about port mirroring, see “Port Mirroring” on page 48.
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 02h: Management/Mirroring Registers
Ingress Mirror Divider Register (Page 02h: Address 14h)
Table 88: Ingress Mirror Divider Register (Page 02h: Address 14h–15h)
Name
R/W
Description
Default
15:10
Reserved
RO
–
0
9:0
IN_MIRROR_DIV
R/W
0
Ingress mirror divider.
Receive frames that have passed the
IN_MIRROR_FILTER rule can further be pruned to
reduce the overall number of frames returned to the
MIRROR_CAPTURE_PORT. When the IN_DIV_EN bit
in the “Ingress Mirror Control Register (Page 02h:
Address 12h)” on page 170 is set, frames that pass the
IN_MIRROR_FILTER rule are further divided by n,
where n = IN_MIRROR_DIV + 1.
l
BIt
en
tia
For additional information about port mirroring, see “Port Mirroring” on page 48.
fid
Ingress Mirror MAC Address Register (Page 02h: Address 16h)
Table 89: Ingress Mirror MAC Address Register (Page 02h: Address 16h–1Bh)
Name
R/W
Description
Default
47:0
IN_MIRROR_MAC
R/W
Ingress mirror MAC address.
MAC address that is compared against ingress
frames in accordance with the
IN_MIRROR_FILTER rules in “Ingress Mirror
Control Register (Page 02h: Address 12h)” on
page 170.
0
dc
om
C
on
BIt
Br
oa
For additional information about port mirroring, see “Port Mirroring” on page 48.
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 02h: Management/Mirroring Registers
Egress Mirror Control Register (Page 02h: Address 1Ch)
Table 90: Egress Mirror Control Register (Page 02h: Address 1Ch–1Dh)
Name
R/W
Description
Default
15:14
OUT_MIRROR_FILTE R/W
R
Egress mirror filter.
0
Filters egress frames that are forwarded to the mirror
capture port, specified in “Mirror Capture Control
Register (Page 02h: Address 10h)” on page 169.
00 = Mirror all egress frames.
01 = Mirror all egress frames with DA =
OUT_MIRROR_MAC.
10 = Mirror all egress frames with SA =
OUT_MIRROR_MAC.
11 = Reserved.
OUT_MIRROR_MAC is specified in “Egress Mirror MAC
Address Register (Page 02h: Address 20h)” on
page 173.
13
OUT_DIV_EN
Egress divider enable.
en
R/W
tia
l
BIt
0
th
Reserved
R/W
8:0
OUT_MIRROR_MASK R/W
–
0
om
12:9
C
on
fid
The egress divider mirrors every n egress frame that
has passed through the OUT_MIRROR_FILTER (n
represents the OUT_MIRROR_DIV defined in “Egress
Mirror Divider Register (Page 02h: Address 1Eh)” on
page 173).
0 = Disable egress divider feature.
1 = Enable egress divider feature.
Br
oa
dc
0
Egress mirror port mask.
Bit 8 = IMP port.
Bits [5:0] correspond to ports [5:0], respectively.
Ports with the corresponding bit set to 1 have egress
frames mirrored to the MIRROR_CAPTURE_PORT.
While multiple ports can be set as an egress mirror port,
severe congestion and/or frame loss may occur if
excessive bandwidth from the egress mirrored port (s) is
directed to the MIRROR_CAPTURE_PORT. Setting a
mirror filter using bits [15:14] or a divider using bit 13 may
be helpful.
For additional information about port mirroring, see “Port Mirroring” on page 48.
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 02h: Management/Mirroring Registers
Egress Mirror Divider Register (Page 02h: Address 1Eh)
Table 91: Egress Mirror Divider Register (Page 02h: Address 1Eh–1Fh)
Name
R/W
Description
Default
15:10
Reserved
RO
–
0
9:0
OUT_MIRROR_DIV
R/W
0
Egress mirror divider.
Egressed frames that have passed the
OUT_MIRROR_FILTER rule can further be pruned to
reduce the overall number of frames returned to the
MIRROR_CAPTURE_PORT. When the
OUT_DIV_EN bit in the “Egress Mirror Control
Register (Page 02h: Address 1Ch)” on page 172 is
set, frames that pass the OUT_MIRROR_FILTER
rule are further divided by n, where
n = OUT_MIRROR_DIV + 1.
tia
l
BIt
en
For additional information about port mirroring, see “Port Mirroring” on page 48.
fid
Egress Mirror MAC Address Register (Page 02h: Address 20h)
on
Table 92: Egress Mirror MAC Address Register (Page 02h: Address 20h–25h)
Name
R/W
Description
Default
47:0
OUT_MIRROR_MAC
R/W
0
Egress mirror MAC address.
MAC address that is compared against egress
frames in accordance with the
OUT_MIRROR_FILTER rules defined in “Egress
Mirror Control Register (Page 02h: Address
1Ch)” on page 172.
dc
om
C
BIt
oa
For additional information about port mirroring, see “Port Mirroring” on page 48.
Br
Device ID Register (Page 02h: Address 30h–33h)
Table 93: Device ID Register (Page 02h: Address 30h–33h)
BIt
Name
R/W
Description
Default
31:0
Device_ID
RO
Device ID
32'0005_3125
Revision Number Register (Page 02h: Address 40h)
Table 94: Egress Mirror MAC Address Register (Page 02h: Address 40h)
BIt
Name
R/W
Description
Default
7:0
Revision_ID
RO
Revision number
0
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 02h: Management/Mirroring Registers
High-Level Protocol Control Register (Page 02h: Address 50h–53h)
Table 95: High-Level Protocol Control Register (Page 02h: Address 50h–53h)
BIt
Name
R/W
Description
Default
31:19
Reserved
R/W
Reserved
–
18
MLD_QRY_FWD_MODE
R/W
MLD Query Message Forwarding Mode.
0
1 = MLD Query message frames will be trapped
to CPU port only.
0 = MLD Query message frames will be
forwarded by L2 result and also copied to CPU.
17
MLD_QRY_EN
R/W
MLD Query Message Snooping/Redirect
Enable.
1 = Enable MLD query message snooping/
redirect.
0 = Disable.
16
MLD_RPTDONE_FWD_MO R/W
DE
MLD Report/Done Message Forwarding Mode. 0
1 = MLD report/done message frames will be
trapped to CPU port only.
0 = MLD report/done message frames will be
forwarded by L2 result and also copied to CPU.
15
MLD_RPTDONE_EN
R/W
MLD Report/Done Message Snooping/Redirect 0
Enable.
1 = Enable MLD report/done message snooping/
redirect.
0 = Disable.
14
IGMP_UKN_FWD_MODE
R/W
13
IGMP_UKN_EN
12
11
C
on
fid
en
tia
l
0
dc
om
0
IGMP Unknown Message Forwarding Mode.
1 = IGMP unknown message frames will be
trapped to CPU port only.
0 = IGMP unknown message frames will be
forwarded by L2 result and also copied to CPU.
0
IGMP Unknown Message Snooping/Redirect
Enable.
1 = Enable IGMP unknown message snooping/
redirect.
0 = Disable.
IGMP_QRY_FWD_MODE
R/W
0
IGMP Query Message Forwarding Mode.
1 = IGMP query message frames will be trapped
to CPU port only.
0 = IGMP query message frames will be
forwarded by L2 result and also copied to CPU.
IGMP_QRY_EN
R/W
IGMP Query Message Snooping/Redirect
Enable.
1 = Enable IGMP query message Snooping/
Redirect.
0 = Disable.
Br
oa
R/W
Broadcom®
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BCM53125S Data Sheet
Page 02h: Management/Mirroring Registers
Table 95: High-Level Protocol Control Register (Page 02h: Address 50h–53h) (Cont.)
BIt
Name
Description
Default
10
IGMP_RPTLVE_FWD_MOD R/W
E
IGMP Report/Leave Message Forwarding Mode. 0
1 = IGMP report/leave message frames will be
trapped to CPU port only.
0 = IGMP report/leave message frames will be
forwarded by L2 result and also copied to CPU.
9
IGMP_RPTLVE_EN
R/W
IGMP Report/Leave Message Snooping/
Redirect Enable.
1 = Enable IGMP report/leave message
Snooping/Redirect.
0 = Disable.
8
IGMP_DIP_EN
R/W
0
IGMP L3 DIP checking Enable.
In addition to the IP datagram with a protocol
value of 2, IGMP will be classified by matching its
DIP with the Class D IP address(224.0.0.0–
239.255.255.255).
7:6
Reserved
R/W
Reserved
5
ICMPv6_FWD_MODE
R/W
ICMPv6 (exclude MLD) Forwarding Mode.
0
1 = ICMPv6 frames will be trapped to CPU port
only.
0 = ICMPv6 frames will be forwarded by L2 result
and also copied to CPU.
4
ICMPv6_EN
R/W
0
ICMPv6 (exclude MLD) Snooping/Redirect
Enable.
ICMPv6, with a next header value of 58, will be
classified by IPv6 datagram.
3
ICMPv4_EN
2
DHCP_EN
R/W
DHCP Snooping Enable.
0
1 = DHCP frames will be forwarded by L2 result
and also copied to CPU.
0 = DHCP frames will be forwarded by L2 result.
1
RARP_EN
R/W
RARP Snooping Enable.
0
1 = RARP frames will be forwarded by L2 result
and also copied to CPU.
0 = RARP frames will be forwarded by L2 result.
0
ARP_EN
R/W
ARP Snooping Enable.
1 = ARP frames will be forwarded by L2 result
and also copied to CPU.
0 = ARP frames will be forwarded by L2 result.
0
0
om
C
on
fid
en
tia
l
R/W
Br
oa
dc
R/W
0
ICMPv4 Snooping Enable.
ICMPv6, with a next header value of 0 and
extension header next header value of 58, will be
classified by IPv6 datagram.
1 = ICMPv4 frames will be forwarded by L2 result
and also copied to CPU.
0 = ICMPv4 frames will be forwarded by L2
result.
Broadcom®
March 11, 2016 • 53125S-DS06-R
0
Page 175
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 03h: Interrupt Control Register
Page 03h: Interrupt Control Register
Table 96: Interrupt Status Register (Page 03H: Address 00h-03h)
Name
R/W
Description
Default
31:25
Reserved
–
–
–
24:16
Link Status Change
Interrupt
–
Each bit is set when corresponding port status is
changed.
0 = No link status change.
1 = Link status change.
Bit [24] = IMP port (port8).
Bit [23:22] = Reserved.
Bit [21:16] = Port[5:0].
–
15:2
Reserved
–
–
–
1:0
IMP_Sleep_Timer_Run R/W
tia
l
BIt
fid
en
Each bit set indicates the corresponding port timer –
has been triggered.
Bit [1] = WAN port (port5).
Bit [0] = IMP port (port 8).
on
Table 97: Interrupt Enable Register (Page 03H: Address 08h-0Bh)
Name
R/W
Description
31:25
Reserved
–
–
–
24:16
Link Status Change
Interrupt_Enable
–
Each bit is set when corresponding port status is
changed.
0 = Disable interrupt.
1 = Enable interrupt.
Bit [24] = IMP port (port8).
Bit [23:22] = Reserved.
Bit [21:16] = Port[5:0].
–
15:2
Reserved
–
–
1:0
IMP_Sleep_Timer_Run R/W
_enable
Each bit set enables the corresponding port timer
has been triggered.
Bit [1] = WAN port (port5).
Bit [0] = IMP port (port 8).
–
oa
dc
om
C
BIt
Br
–
Default
Table 98: IMP Sleep Timer Register (Page 03H: Address 10h-11h)
BIt
Name
R/W
Description
Default
15:13
Reserved
–
–
0x0
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BCM53125S Data Sheet
Page 03h: Interrupt Control Register
Table 98: IMP Sleep Timer Register (Page 03H: Address 10h-11h) (Cont.)
BIt
Name
R/W
Description
Default
12:0
IMP_Sleep_Timer
R/W
The configuration value of IMP port (port 8) sleep 0x0
timer to indicate the desired sleep recovery time (i.e.
wake-up time). When the timer is set by the CPU to
a nonzero value, it puts the IMP port to sleep. The
wake-up time is the set value decrease 1.
The unit is in 1 µs.
Table 99: WAN Sleep Timer Register (Page 03H: Address 14h-15h)
Name
R/W
Description
Default
15:13
Reserved
–
–
0x0
12:0
WAN_Sleep_Timer
R/W
The configuration value of WAN port (port 5) sleep 0x0
timer to indicate the desired sleep recovery time (i.e.
wake-up time). When the timer is set by the CPU to
a nonzero value, it puts the IMP port to sleep. The
wake-up time is the set value decrease 1.
The unit is in 1 µs.
fid
en
tia
l
BIt
on
Table 100: Sleep Status Register (Page 03H: Address 18h)
Name
R/W
Description
7:2
Reserved
–
–
1
WAN_Port_Sleep_STS RO
0
IMP_Port_Sleep_STS
C
BIt
Default
0x0
Br
oa
dc
om
WAN Port(port5) Sleep Status.
0x0
0 = WAN port is not in IMP_Sleep mode whenever
either reset or the counter of WAN SLEEP Timer is
equal to zero.
Note: The port is in IMP_SLEEP INIT state.
1 = WAN port is in IMP_Sleep mode when the
counter of WAN Sleep Timer is not equal to zero.
Note: The port is not in IMP_SLEEP INIT state.
RO
IMP Port(port88) Sleep Status.
0x0
0 = IMP port is not in IMP_Sleep mode whenever
either reset or the counter of IMP SLEEP Timer is
equal to zero.
Note: The port is in IMP_SLEEP INIT state.
1 = IMP port is in IMP_Sleep mode when the counter
of IMP Sleep Timer is not equal to zero.
Note: The port is not in IMP_SLEEP INIT state.
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 04h: ARL Control Register
Page 04h: ARL Control Register
Table 101: ARL Control Registers (Page 04h)
Bits
Register Name
00h
8
“Global ARL Configuration Register (Page 04h: Address 00h)” on
page 179
01h–03h
–
Reserved
04h–09h
48
“BPDU Multicast Address Register (Page 04h: Address 04h)” on
page 179
0Ah–0Dh
–
Reserved
0Eh–0Fh
16
“Multiport Control Register (Page 04h: Address 0Eh–0Fh)” on page 179
10h–17h
64
“Multiport Address N (N=0–5) Register (Page 04h: Address 10h)” on
page 181
18h–1Bh
32
“Multiport Vector N (N=0–5) Register (Page 04h: Address 18h)” on
page 182
1Ch–1Fh
–
Reserved
20h–27h
64
“Multiport Address N (N=0–5) Register (Page 04h: Address 10h)” on
page 181
28h–2Bh
32
“Multiport Vector N (N=0–5) Register (Page 04h: Address 18h)” on
page 182
2Ch–2Fh
–
Reserved
30h–37h
64
“Multiport Address N (N=0–5) Register (Page 04h: Address 10h)” on
page 181
38h–3Bh
32
“Multiport Vector N (N=0–5) Register (Page 04h: Address 18h)” on
page 182
3Ch–3Fh
–
40h–47h
64
48h–4Bh
32
4Ch–4Fh
–
en
fid
on
C
om
Reserved
dc
“Multiport Address N (N=0–5) Register (Page 04h: Address 10h)” on
page 181
“Multiport Vector N (N=0–5) Register (Page 04h: Address 18h)” on
page 182
oa
Br
50h–57h
tia
l
Address
Reserved
64
“Multiport Address N (N=0–5) Register (Page 04h: Address 10h)” on
page 181
32
“Multiport Vector N (N=0–5) Register (Page 04h: Address 18h)” on
page 182
5Ch–5Fh
–
Reserved
60h–67h
64
“Multiport Address N (N=0–5) Register (Page 04h: Address 10h)” on
page 181
68h–6Bh
32
“Multiport Vector N (N=0–5) Register (Page 04h: Address 18h)” on
page 182
6Ch–FEh
–
Reserved
F0h–F7h
8
“SPI Data I/O Register (Global, Address F0h)” on page 280, bytes 0–7
F8h–FDh
–
Reserved
FEh
8
“SPI Status Register (Global, Address FEh)” on page 280
58h–5Bh
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 04h: ARL Control Register
Table 101: ARL Control Registers (Page 04h) (Cont.)
Address
Bits
Register Name
FFh
8
“Page Register (Global, Address FFh)” on page 280
Global ARL Configuration Register (Page 04h: Address 00h)
Table 102: Global ARL Configuration Register (Page 04h: Address 00h)
Name
R/W
Description
Default
7:5
Reserved
RO
–
0
4
Reserved
–
–
–
3
Reserved
RO
–
0
2
AGE_Accelerate
R/W
When enabled, the aging time is reduced by 1/128. –
1 = Accelerate the aging 128 times.
0 = Keep the original age process.
1
Reserved
RO
–
0
Hash Disable
R/W
Hash function disable.
0
Disables the hash function of the ARL table so that
entries are directly mapped to the table instead of
being hashed to an index.
1 = Disable hash function.
0 = Enable hash function.
For more information see “Address Table
Organization” on page 57.
1
om
C
on
fid
en
tia
l
BIt
dc
BPDU Multicast Address Register (Page 04h: Address 04h)
Table 103: BPDU Multicast Address Register (Page 04h: Address 04h–09h)
Name
47:0
BPDU_MC_ADDR
R/W
Description
R/W
01-80-c2BPDU multicast address 1.
00-00-00
Defaults to the IEEE 802.1 defined reserved
multicast address for the bridge group address.
Programming to an alternate value allows support
of proprietary protocols in place of the normal
spanning tree protocol. Frames with a matching DA
to this address are forwarded to the designated
management port.
Br
oa
Bit
Default
Multiport Control Register (Page 04h: Address 0Eh–0Fh)
Table 104: Multiport Control Register (Page 04h: Address 0Eh–0Fh)
Bit
Name
R/W
Description
Default
15
Reserved
R/W
Reserved
0
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 04h: ARL Control Register
Table 104: Multiport Control Register (Page 04h: Address 0Eh–0Fh) (Cont.)
Name
R/W
Description
Default
14:12
Reserved
RO
Reserved
0
11:10
MPORT_CTRL5
R/W
Multiport 5 Control.
00
00 = Disable Multiport 5 Forward.
10 = Compare MPORT_ADD5 only; Forward based
on MPORT_Vector 5 if matched.
01 = Compare MPORT_ETYPE5 only; Forward
based on MPORT_Vector 5 if matched.
11 = Compare MPORT_ETYPE5 and
MPORT_ADD5; Forward based on MPORT_Vector
5 if matched.
9:8
MPORT_CTRL4
R/W
Multiport 4 Control.
00
00 = Disable Multiport 4 Forward.
10 = Compare MPORT_ADD4 only; Forward based
on MPORT_Vector 4 if matched.
01 = Compare MPORT_ETYPE4 only; Forward
based on MPORT_Vector 4 if matched.
11 = Compare MPORT_ETYPE4 and
MPORT_ADD4; Forward based on MPORT_Vector
4 if matched.
7:6
MPORT_CTRL3
R/W
Multiport 3 Control.
00
00 = Disable Multiport 3 Forward.
10 = Compare MPORT_ADD3 only; Forward based
on MPORT_Vector 3 if matched.
01 = Compare MPORT_ETYPE3 only; Forward
based on MPORT_Vector 3 if matched.
11 = Compare MPORT_ETYPE3 and
MPORT_ADD3; Forward based on MPORT_Vector
3 if matched.
5:4
MPORT_CTRL2
3:2
MPORT_CTRL1
dc
om
C
on
fid
en
tia
l
Bit
Br
oa
R/W
R/W
00
Multiport 2 Control.
00 = Disable Multiport 2 Forward.
10 = Compare MPORT_ADD2 only; Forward based
on MPORT_Vector 2 if matched.
01 = Compare MPORT_ETYPE2 only; Forward
based on MPORT_Vector 2 if matched.
11 = Compare MPORT_ETYPE2 and
MPORT_ADD2; Forward based on MPORT_Vector
2 if matched.
00
Multiport 1 Control.
00 = Disable Multiport 1 Forward.
10 = Compare MPORT_ADD1 only; Forward based
on MPORT_Vector 1 if matched.
01 = Compare MPORT_ETYPE1 only; Forward
based on MPORT_Vector 1 if matched.
11 = Compare MPORT_ETYPE1 and
MPORT_ADD1; Forward based on MPORT_Vector
1 if matched.
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 04h: ARL Control Register
Table 104: Multiport Control Register (Page 04h: Address 0Eh–0Fh) (Cont.)
Bit
Name
R/W
Description
Default
1:0
MPORT_CTRL0
R/W
Multiport 0 Control.
00
00 = Disable Multiport 0 Forward.
10 = Compare MPORT_ADD0 only; Forward based
on MPORT_Vector 0 if matched.
01 = Compare MPORT_ETYPE0 only; Forward
based on MPORT_Vector 0 if matched.
11 = Compare MPORT_ETYPE0 and
MPORT_ADD0; Forward based on MPORT_Vector
0 if matched.
Multiport Address N (N=0–5) Register (Page 04h: Address 10h)
l
.
tia
Table 105: Multiport Address Register Address Summary
Description
10h–17h
Multiport ETYPE Address 0
20h–27h
Multiport ETYPE Address 1
30h–37h
Multiport ETYPE Address 2
40h–47h
Multiport ETYPE Address 3
on
fid
en
Address
50h–57h
Multiport ETYPE Address 4
Multiport ETYPE Address 5
om
C
60h–67h
Table 106: Multiport Address Register (Page 04h: Address 10h–17h, 20h–27h, 30h–37h, 40h–47h, 50h–
57h, 60h–67h)
64:48
MPORT_ETYPE
47:0
MPORT_ADDR
R/W
Description
R/W
0000
Multiport Ethernet Type.
Allows a frames with a matching
MPORT_ETYPE to this Length Type field to be
forwarded to any programmable group of ports
on the chip, as defined in the bit map in the
Multiport Vector Register.
Must be enabled using the MPORT_CTRL bit in
the Multiport Control Register.
R/W
0000000
Multiport Address.
00000
Allows a frames with a matching DA to this
address to be forwarded to any programmable
group of ports on the chip, as defined in the bit
map in the Multiport Vector Register.
Must be enabled using the MPORT_CTRL bit in
the Multiport Control Register.
dc
Name
Br
oa
BIt
Broadcom®
March 11, 2016 • 53125S-DS06-R
Default
Page 181
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 05h: ARL/VTBL Access Registers
Multiport Vector N (N=0–5) Register (Page 04h: Address 18h)
.
Table 107: Multiport Vector Register Address Summary
Address
Description
18h–1Bh
Multiport Vector 0
28h–2Bh
Multiport Vector 1
38h–3Bh
Multiport Vector 2
48h–4Bh
Multiport Vector 3
58h–5Bh
Multiport Vector 4
68h–6Bh
Multiport Vector 5
tia
l
Table 108: Multiport Vector Register (Page 04h: Address 18h–1Bh, 28h–2Bh, 38h–3Bh, 48h–4Bh, 58h–
5Bh, 68h–6Bh)
Name
R/W
Description
31:9
Reserved
R/O
–
8:0
MPORT_VCTR_N
R/W
Multiport Vector.
0
A bit mask corresponding to the physical ports on
the chip.
A frame with a DA matching the content of the
Multiport Address Register will be forwarded to
each port with a bit set in the Multiport Vector bit
map.
Bits [5:0] correspond to ports[5:0].
Bit 8 = Management Port (MII Management).
Default
0
dc
om
C
on
fid
en
BIt
oa
Page 05h: ARL/VTBL Access Registers
Address
Br
Table 109: ARL/VTBL Access Registers (Page 05h)
Bits
Register Name
8
“ARL Table Read/Write Control Register (Page 05h: Address 00h)” on
page 184
01h–0Fh
–
Reserved
02h–07h
48
“MAC Address Index Register (Page 05h: Address 02h)” on page 184
08h–09h
16
“VLAN ID Index Register (Page 05h: Address 08h)” on page 185
0Ah–0Fh
–
Reserved
10h–17h
64
“ARL Table MAC/VID Entry N (N=0-3) Register (Page 05h: Address 10h)” on
page 185
18h–1Bh
16
“ARL Table Data Entry N (N=0-3) Register (Page 05h: Address 18h)” on
page 186
1Ch–1Fh
–
Reserved
00h
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 05h: ARL/VTBL Access Registers
Table 109: ARL/VTBL Access Registers (Page 05h) (Cont.)
Bits
Register Name
20h-27h
64
“ARL Table MAC/VID Entry N (N=0-3) Register (Page 05h: Address 10h)” on
page 185
28h-2Bh
32
“ARL Table Data Entry N (N=0-3) Register (Page 05h: Address 18h)” on
page 186
2Ch-2Fh
–
Reserved
30h-37h
64
“ARL Table MAC/VID Entry N (N=0-3) Register (Page 05h: Address 10h)” on
page 185
38h-3Bh
32
“ARL Table Data Entry N (N=0-3) Register (Page 05h: Address 18h)” on
page 186
3Ch-3Fh
–
Reserved
40h-47h
64
“ARL Table MAC/VID Entry N (N=0-3) Register (Page 05h: Address 10h)” on
page 185
48h-4Bh
32
“ARL Table Data Entry N (N=0-3) Register (Page 05h: Address 18h)” on
page 186
4Ch-4Fh
–
Reserved
50h
8
“ARL Table Search Control Register (Page 05h: Address 50h)” on page 187
51h–52h
16
ARL Search Address
60h–77h
64
“ARL Table Search MAC/VID Result N (N=0-1) Register (Page 05h: Address
60h)” on page 188
68h–7Bh
32
“ARL Table Search Data Result N (N=0-1) Register (Page 05h: Address 68h)”
on page 189
7Ch–7Fh
–
Reserved
80h
8
“VLAN Table Read/Write/Clear Control Register (Page 05h: Address 80h)” on
page 190
81h–82h
16
“VLAN Table Address Index Register (Page 05h: Address 81h)” on page 191
83h–86h
32
67h–EFh
–
F0h–F7h
8
F8h–FDh
–
FEh
8
tia
en
fid
on
C
om
dc
“VLAN Table Entry Register (Page 05h: Address 83h–86h)” on page 191
Reserved
oa
“SPI Data I/O Register (Global, Address F0h)” on page 280, bytes 0–7
Reserved
“SPI Status Register (Global, Address FEh)” on page 280
Br
FFh
l
Address
8
“Page Register (Global, Address FFh)” on page 280
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 05h: ARL/VTBL Access Registers
ARL Table Read/Write Control Register (Page 05h: Address 00h)
Table 110: ARL Table Read/Write Control Register (Page 05h: Address 00h)
Name
R/W
Description
Default
7
START/DONE
R/W
(SC)
0
Start/done command.
Write as 1 to initiate a read/write command to the
ARL table. The bit returns to 0 to indicate that a read/
write operation is complete.
6:1
Reserved
RO
–
–
0
ARL_R/W
R/W
ARL table read/write bit.
Specifies whether the ARL command is a read or
write operation.
1 = Read.
0 = Write.
0
tia
l
BIt
en
For more information, see “Accessing the ARL Table Entries” on page 62.
fid
MAC Address Index Register (Page 05h: Address 02h)
on
Table 111: MAC Address Index Register (Page 05h: Address 02h–07h)
Name
R/W
Description
Default
47:0
MAC_ADDR_INDX
R/W
0
MAC address index.
The ARL table read/write command uses this 48-bit
address to index the ARL table. When IEEE 802.1Q
is enabled, the ARL table is indexed by a combined
hash of the MAC_ADDR_INDX and the
VID_TBL_INDX, defined in the “VLAN ID Index
Register (Page 05h: Address 08h)” on page 185.
For more information, see “Accessing the ARL Table
Entries” on page 62.
Br
oa
dc
om
C
BIt
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 05h: ARL/VTBL Access Registers
VLAN ID Index Register (Page 05h: Address 08h)
Table 112: VLAN ID Index Register (Page 05h: Address 08h–09h)
BIt
Name
R/W
Description
Default
15:12
Reserved
R/W
–
0
11:0
VID_INDX
R/W
0
VLAN ID index.
When IEEE 802.1Q is enabled, the VLAN ID Index
is used with the MAC_ADDR_INDX, defined in the
“MAC Address Index Register (Page 05h: Address
02h)” on page 184, to form the hash index for which
status is to be read or written.
For more information, see “Accessing the ARL
Table Entries” on page 62.
en
tia
l
ARL Table MAC/VID Entry N (N=0-3) Register (Page 05h: Address
10h)
.
fid
Table 113: ARL Table MAC/VID Entry N (N=0-3) Register Address Summary
Description
10h–17h
ARL Table MAC/VID Entry 0
on
Address
20h–27h
ARL Table MAC/VID Entry 1
ARL Table MAC/VID Entry 2
C
30h–37h
ARL Table MAC/VID Entry 3
om
40h–47h
dc
Table 114: ARL Table MAC/VID Entry N (N=0-3) Register (Page 05h: Address 10h–17h, 20h–27h, 30h–
37h, 40h–47h)
Name
63:60
Reserved
59:48
VID_N
47:0
MACADDR_N
R/W
Description
Default
R/O
–
0
R/W
VID entry N.
0
The VID field is either read from or written to the
ARL table entry N.
The VID is a “don’t-care” field when IEEE 802.1Q
is disabled.
R/W
MAC address entry N.
The 48-bit MAC Address field to be either read
from or written to the ARL table entry N.
Br
oa
BIt
0
Note: Together, the “ARL Table MAC/VID Entry N (N=0-3) Register (Page 05h: Address 10h)” on
page 185 and the “ARL Table Data Entry N (N=0-3) Register (Page 05h: Address 18h)” on page 186
compose a complete entry in the ARL table. For more information, see “Accessing the ARL Table Entries”
on page 62.
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 05h: ARL/VTBL Access Registers
ARL Table Data Entry N (N=0-3) Register (Page 05h: Address 18h)
.
Table 115: ARL Table Data Entry N (N=0-3) Register Address Summary
Address
Description
18h–1Bh
ARL Table Data Entry 0
28h–2Bh
ARL Table Data Entry 1
38h–3Bh
ARL Table Data Entry 2
48h–4Bh
ARL Table Data Entry 3
Table 116: ARL Table Data Entry N (N=0-3) Register (Page 05h: Address 18h–1Bh, 28h–2Bh, 38h–3Bh,
48h–4Bh)
Name
R/W
Description
Default
31:17
Reserved
RO
–
16
VALID_N
R/W
Valid bit entry N.
Write this bit to 1 to indicate that a valid MAC
address is stored in the MACADDR_N field
defined in the “ARL Table MAC/VID Entry N
(N=0-3) Register (Page 05h: Address 10h)” on
page 185, and that the entry has not aged out.
Reset when an entry is empty.
This information is read from or written to the
ARL table during a read/write command.
15
STATIC_N
R/W
14
AGE_N
0
0
C
on
fid
en
tia
l
BIt
Br
oa
dc
om
0
Static bit entry N.
Write this bit to 1 to indicate that the entry is
controlled by the external register control. When
cleared, the internal learning and aging process
controls the validity of the entry.
This information is read from or written to the
ARL table during a read/write command.
R/W
0
Age bit entry N.
Write this bit to 1 to indicate that an address entry
has been learned or accessed. This bit is set to
0 by the internal aging algorithm. If the internal
aging process detects that a valid entry has
remained unused for the period set by the
AGE_TIME (defined in the “Aging Time Control
Register (Page 02h: Address 06h)” on page 169)
and the entry has not been marked as static, the
entry has the valid bit cleared.
The age bit is ignored if the entry has been
marked as Static.
This information is read from or written to the
ARL table during a read/write command.
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 05h: ARL/VTBL Access Registers
Table 116: ARL Table Data Entry N (N=0-3) Register (Page 05h: Address 18h–1Bh, 28h–2Bh, 38h–3Bh,
48h–4Bh) (Cont.)
Name
R/W
Description
Default
13:11
TC_N
R/W
TC bit for MAC-based QoS entry N.
These bits define the TC field for MAC-based
QoS packets.
This information is read from or written to the
ARL table during a read/write command.
0
10:9
Reserved
R/W
–
–
8:0
FWD_PRT_MAP_N
R/W
Multicast Group Forward portmap entry N.
0
For multicast entries, these bits define the
forward port map.
Bit 8 = CPU port/MII port.
Bits [5:0] correspond to ports [5:0], respectively.
l
BIt
0
Unicast Forward PortID entry N.
For unicast entries, these bits define the port
number associated with the entry of the ARL
table.
Bits [8:4] = Reserved.
Bits [3:0] = Port ID/Port Number which identifies
where the station with unique MACADDR_N is
connected.
on
fid
en
tia
PORTID_N
C
ARL Table Search Control Register (Page 05h: Address 50h)
om
Table 117: ARL Table Search Control Register (Page 05h: Address 50h)
BIt
Name
R/W
Description
Default
7
START/DONE
R/W
(SC)
6:1
Reserved
RO
–
0
ARL_SR_VALID
RC
0
ARL search result valid.
Set by BCM53125S to indicate that an ARL entry is found by
the ARL table search. The found entry is available in the “ARL
Table Search Data Result N (N=0-1) Register (Page 05h:
Address 68h)” on page 189.
This bit automatically returns to 0 after the ARL Search Result
register is read.
Br
oa
dc
0
Start/done.
Write as 1 to initiate a sequential search of the ARL table.
Each entry found by the search is returned to the “ARL Table
Search Data Result N (N=0-1) Register (Page 05h: Address
68h)” on page 189 and the “ARL Table Search MAC/VID
Result N (N=0-1) Register (Page 05h: Address 60h)” on
page 188. Reading the “ARL Table Search Data Result N
(N=0-1) Register (Page 05h: Address 68h)” on page 189
allows the ARL table search to continue.
BCM53125S clears this bit when the ARL table search is
complete.
0
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 05h: ARL/VTBL Access Registers
For more information, see “Accessing the ARL Table Entries” on page 62.
ARL Search Address Register (Page 05h: Address 51h)
Table 118: ARL Search Address Register (Page 05h: Address 51h–52h)
Name
15
14:0
R/W
Description
Default
ARL_ADDR_VALID R/W
(SC)
ARL address valid.
Indicates the lower 15 bits of this register contain a valid
internal representation of the ARL entry that is currently
being accessed. Intended for factory test/diagnostic use
only.
0
ARL_ADDR
0
ARL address.
14-bit internal representation of the address of the ARL
entry currently being accessed by the ARL search routine.
This is not a direct address of the ARL location and is
intended for factory test/diagnostic use only.
–
en
tia
l
Bit
.
fid
ARL Table Search MAC/VID Result N (N=0-1) Register (Page 05h:
Address 60h)
on
Table 119: ARL Table Search MAC/VID Result N (N=0-1) Register Address Summary
Description
C
Address
60h–67h
ARL Table Search MAC/VID Result 0
om
70h–77h
ARL Table Search MAC/VID Result 1
R/W
Description
Default
63:60
Reserved
RO
–
0
59:48
ARL_SR_VID_N
RO
ARL search VID result.
These bits store the VID of the ARL table entry
found by the ARL table search function.
0
47:0
ARL_SR_MAC_N
RO
ARL search MAC address result.
These bits store the MAC address of the ARL
table entry found by the ARL table search
function.
N/A
oa
Name
Br
BIt
dc
Table 120: ARL Table Search MAC/VID Result N (N=0-1) Register (Page 05h: Address 60h–67h, 70h–
77h)
For more information, see “Accessing the ARL Table Entries” on page 62.
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 05h: ARL/VTBL Access Registers
ARL Table Search Data Result N (N=0-1) Register (Page 05h: Address
68h)
.
Table 121: ARL Table Search Data Result N (N=0-1) Register Address Summary
Address
Description
68h–6Bh
ARL Table Search Data Result 0
78h–7Bh
ARL Table Search Data Result 1
Table 122: ARL Table Search Data Result N (N=0-1) Register (Page 05h: Address 68h–6Bh, 78h–7Bh)
Name
R/W
Description
Default
31:17
Reserved
RO
–
0
16
ARL_SR_VALID_N
RO
0
ARL search valid bit result.
This bit stores the valid bit of the ARL table entry
found by the ARL table search function. Reading
this register clears the data from the register and
allows the ARL table search function to continue
searching.
15
ARL_SR_STATIC_N
RO
N/A
ARL search static bit result.
This bit stores the static bit of the ARL table entry
found by the ARL table search function. Reading
this register clears the data from the register and
allows the ARL table search function to continue
searching.
14
ARL_SR_AGE_N
RO
13:11
ARL_SR_TC_N
10:9
Reserved
C
on
fid
en
tia
l
BIt
RO
–
ARL search TC bits result.
These bits store the TC bits of the ARL table
entry found by the ARL table search function.
Reading this register clears the data from the
register and allows the ARL table search function
to continue searching.
RO
–
Br
oa
dc
om
–
ARL search age bit result.
This bit stores the Age bit of the ARL table entry
found by the ARL table search function. Reading
this register clears the data from the register and
allows the ARL table search function to continue
searching.
Broadcom®
March 11, 2016 • 53125S-DS06-R
0
Page 189
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 05h: ARL/VTBL Access Registers
Table 122: ARL Table Search Data Result N (N=0-1) Register (Page 05h: Address 68h–6Bh, 78h–7Bh)
BIt
Name
R/W
Description
Default
8:0
FWD_PRT_MAP_N
R/W
Multicast Group Forward portmap entry N.
For multicast entries, these bits define the
forward port map.
Bit 8 = CPU port/MII port.
Bits [5:0] correspond to ports [5:0].
0
0
Unicast Forward PortID entry N.
For unicast entries, these bits define the port
number associated with the entry of the ARL
table.
Bits [8:4] = Reserved.
Bits [3:0] = Port ID/Port Number which identifies
where the station with unique MACADDR_N is
connected.
tia
l
PORTID_N
en
For more information, see “Accessing the ARL Table Entries” on page 62.
on
fid
VLAN Table Read/Write/Clear Control Register (Page 05h: Address
80h)
C
Table 123: VLAN Table Read/Write/Clear Control Register (Page 05h: Address 80h)
Name
R/W
Description
7
START/DONE
R/W
(SC)
0
Start/done command.
Write as 1 to initiate a read or write or clear-table
command to the VLAN table. The bit returns to 0 to
indicate that the read or write or clear-table operation is
complete.
6:2
Reserved
1:0
VTBL_R/W/Clr
dc
oa
R/W
Br
R/W
Default
om
BIt
–
–
Read/Write/Clear-table.
Specifies whether the current VLAN table read/write/
clear-table
command is a read or write or clear-table operation.
11 = Reserved.
10 = Clear-table.
01 = Read.
00 = Write.
0
See “Double Tagging” on page 41 for more information.
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 05h: ARL/VTBL Access Registers
VLAN Table Address Index Register (Page 05h: Address 81h)
Table 124: VLAN Table Address Index Register (Page 05h: Address 81h–82h)
BIt
Name
R/W
Description
Default
15:12
Reserved
RO
–
0
11:0
VTBL_ADDR_INDX
R/W
VLAN table address index.
–
The current VLAN table read/write uses this 12-bit
address to index the VLAN table.
See “Double Tagging” on page 41 for more information.
l
VLAN Table Entry Register (Page 05h: Address 83h–86h)
Name
Description
31:22
Reserved
RO
–
21
FWD_MODE
R/W
0
This indicates whether the packet forwarding
should be based on VLAN membership or based
on ARL flow.
1 = Based on VLAN membership (excluding
Ingress port).
0 = Based on ARL flow.
Note that the VLAN membership based
forwarding mode is only used for certain ISP
Tagged packets received from ISP port when
BCM53125S is operating in Double-Tag mode.
20:18
MSPT_INDEX
17:9
UNTAG_MAP
Default
0
C
on
fid
en
BIt
om
R/W
tia
Table 125: VLAN Table Entry Register (Page 05h: Address 83h–86h)
Br
oa
dc
R/W
R/W
Index for 8 spanning trees.
0
Untagged port map.
–
Bit 17 = CPU Port/MII Port.
Bits [14:9] correspond to ports [5:0], respectively.
Ports written to 1 are designated as untagged
VLAN ports.
VLAN-tagged frames destined for these ports
are untagged before they are forwarded.
When the IEEE 802.1Q feature is enabled,
frames sent using the CPU (MII port configured
as a management port) are tagged.
Note that the packet forwarded to IMP port
should always be VLAN tagged.
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 191
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 05h: ARL/VTBL Access Registers
Table 125: VLAN Table Entry Register (Page 05h: Address 83h–86h) (Cont.)
BIt
Name
R/W
Description
Default
8:0
FWD_MAP
R/W
Forward PORT MAP.
–
The VLAN-tagged Frame is allowed to be
forwarded to the destination ports corresponding
bits set in the Map Ports written to 1 are
designated as capable of receiving VLAN-tagged
frames.
Bit 8 = CPU Port/MII Port.
Bits [7:6] = Reserved.
Bits [5:0] correspond to Ports [5:0], respectively.
l
See “Double Tagging” on page 41 for more information.
tia
Internal Regulator Control Register (Page 0Fh: Address 12h)
en
Table 126: Internal Regulator Control Register (Page 0Fh: Address 12h)
Name
R/W
Description
7:4
Reserved
RO
–
3:0
Voltage Setting
R/W
0000 – 1.2V
0001 – 0.975V
0010 – 1.000
0011 – 1.025
0100 – 1.050
0101 – 1.075
0110 – 1.100
0111 – 1.125
1000 – 1.150
1001 – 1.175
1010 – 1.225
1011 – 1.250
1100 – 1.275
1101 – 1.300
1110 – 1.325
1111 – 1.350
Default
0x0
0000
Br
oa
dc
om
C
on
fid
BIt
Broadcom®
March 11, 2016 • 53125S-DS06-R
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BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 10h–14h: Internal GPHY MII Registers
Page 10h–14h: Internal GPHY MII Registers
Table 127: 10/100/1000 PHY Page Summary
Page
Description
10h
Port 0 Internal PHY MII Registers
11h
Port 1 Internal PHY MII Registers
12h
Port 2 Internal PHY MII Registers
13h
Port 3 Internal PHY MII Registers
14h
Port 4 Internal PHY MII Registers
l
Table 128: Register Map (Page 10h–14h)
en
tia
Numb
er of
SPI Offset MII
Address Address Bits
Register Table
00h
16
Table 129: “MII Control Register (Page 10h–14h: Address 00h–01h),” on
page 195
02h
01h
16
Table 130: “MII Status Register (Page 10h–14h: Address 02h–03h),” on
page 196
04h–06h
02h
32
Table 131: “PHY Identifier Register MSB (Page 10h–14h: Address 04–07h),” on
page 196
08h
04h
16
Table 133: “Auto-Negotiation Advertisement Register (Page 10h–14h: Address
08h–09h),” on page 197
0Ah
05h
16
Table 134: “Auto-Negotiation Link Partner Ability Register (Page 10h–14h:
Address 0Ah–0Bh),” on page 198
0Ch
06h
16
0Eh
07h
16
Table 136: “Next Page Transmit Register (Page 10h–14h: Address 0Eh–0Fh),”
on page 200
10h
08h
16
Table 137: “Link Partner Received Next Page Register (Page 10h–14h: Address
10h–11h),” on page 200
12h
09h
16
Table 138: “1000BASE-T Control Register (Page 10h–14h: Address 12h–13h),”
on page 201
14h
0Ah
16
Table 139: “1000BASE-T Status Register (Page 10h–14h: Address 14h–15h),”
on page 202
16h–1Dh
–
16
Reserved (Do not read from or write to a reserved register.)
1Eh
0Fh
16
Table 140: “IEEE Extended Status Register (Page 10h–14h: Address 1Eh–
1Fh),” on page 203
20h
10h
16
Table 141: “PHY Extended Control Register (Page 10h–14h: Address 20h–
21h),” on page 204
22h
11h
16
Table 142: “PHY Extended Status Register (Page 10h–14h: Address 22h–23h),”
on page 205
om
C
on
fid
00h
dc
10BASE-T/100BASE-TX/1000BASE-T Registers
Br
oa
Table 134: “Auto-Negotiation Link Partner Ability Register (Page 10h–14h:
Address 0Ah–0Bh),” on page 198
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 193
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 10h–14h: Internal GPHY MII Registers
Table 128: Register Map (Page 10h–14h) (Cont.)
Numb
er of
SPI Offset MII
Address Address Bits
Register Table
24h
12h
16
Table 143: “Receive Error Counter Register (Page 10h–14h: Address 24h–
25h),” on page 206
26h
13h
16
Table 144: “False Carrier Sense Counter Register (Page 10h–14h: Address
26h–27h),” on page 206
28h
14h
16
Table 146: “Receiver NOT_OK Counter Register (Page 10h–14h: Address 28h–
29h),” on page 207
2Ah–2Ch
15h–16h
2Eh
17h
16
Reserved
30h
18h
16
Table 151: “Auxiliary Control Register (Page 10h–14h: Address 30h, Shadow
Value 000),” on page 208
Table 152: “10BASE-T Register (Page 10h–14h: Address 30h, Shadow Value
001),” on page 210
Table 153: “Power/MII Control Register (Page 10h–14h: Address 30h, Shadow
Value 010),” on page 211
Table 154: “Miscellaneous Test Register (Page 10h–14h: Address 30h, Shadow
Value 100),” on page 211
Table 155: “Miscellaneous Control Register (Page 10h–14h: Address 30h,
Shadow Value 111),” on page 212
32h
19h
16
Table 156: “Auxiliary Status Summary Register (Page 10h–14h: Address 32h–
33h),” on page 213
34h
1Ah
16
Table 157: “Interrupt Status Register (Page 10h–14h: Address 34h–35h),” on
page 214
36h
1Bh
16
–
38h
1Ch
16
Table 159: “Spare Control 2 Register (Page 10h–14h: Address 38h, Shadow
Value 00100),” on page 216
Table 159: “Spare Control 2 Register (Page 10h–14h: Address 38h, Shadow
Value 00100),” on page 216
Table 160: “Auto Power-Down Register (Page 10h–14h: Address 38h, Shadow
Value 01010),” on page 216
Table 162: “Mode Control Register (Page 10h–14h: Address 38h, Shadow Value
11111),” on page 219
3Ah
1Dh
16
Table 163: “Master/Slave Seed Register (Page 10h–14h: Address 3Ah–3Bh) Bit
15 = 0,” on page 219
Table 164: “HCD Status Register (Page 10h–14h: Address 3Ah–3Bh) Bit 15 = 1,”
on page 220
3Ch
1Eh
16
Table 165: “Test Register 1 (Page 10h–14h: Address 3C–3Dh),” on page 222
3Eh
1Fh
16
Reserved (Do not read from or write to a reserved register.)
Br
oa
dc
om
C
on
fid
en
tia
l
Reserved (Do not read from or write to a reserved register except for accessing
the Expansion registers through register 15h.)
Expansion registers: Read/Write through register 2Ah (accessed by writing to register 2Eh, bits [11:0]
= 1111 + expansion register number)
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 194
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 10h–14h: Internal GPHY MII Registers
MII Control Register (Page 10h–14h: Address 00h–01h)
Table 129: MII Control Register (Page 10h–14h: Address 00h–01h)
Name
R/W
Description
Default
15
Reset
R/W
SC
1 = PHY reset.
0 = Normal operation.
0
14
Internal Loopback
R/W
1 = Loopback mode.
0 = Normal operation.
0
13
Speed Selection (LSB)
R/W
Bits [6,13]:
11 = Reserved.
10 = 1000 Mbps.
01 = 100 Mbps.
00 = 10 Mbps.
0
12
Auto-negotiation Enable
R/W
1 = Auto-negotiation is enabled.
0 = Auto-negotiation is disabled.
1
11
Power Down
R/W
1 = Power-down.
0 = Normal operation.
0
10
Isolate
R/W
1 = Electrically isolate PHY from GMII.
0 = Normal operation.
0
9
Restart Auto-negotiation
R/W
SC
1 = Restarting auto-negotiation.
0 = Auto-negotiation restart is complete.
0
8
Duplex Mode
R/W
1 = Full duplex.
0 = Half duplex.
1
7
Collision Test Enable
R/W
1 = Enable the collision test mode.
0 = Disable the collision test mode.
0
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
Reserved
tia
en
fid
on
C
om
R/W
Works in conjunction with bit 13.
1
dc
Speed Selection (MSB)
5
R/W
Write as 0, ignore on read.
0
R/W
Write as 0 ignore on read.
0
R/W
Write as 0 ignore on read.
0
R/W
Write as 0 ignore on read.
0
R/W
Write as 0 ignore on read.
0
R/W
Write as 0 ignore on read.
0
Br
oa
6
l
Bit
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 195
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 10h–14h: Internal GPHY MII Registers
MII Status Register (Page 10h–14h: Address 02h)
Table 130: MII Status Register (Page 10h–14h: Address 02h–03h)
Name
R/W
Description
Default
15
100BASE-T4 Capable
RO
L
1 = 100BASE-T4 capable.
0 = Not 100BASE-T4 capable
0
14
100BASE-X Full-Duplex
Capable
RO
H
1 = 100BASE-X full-duplex capable.
0 = Not 100BASE-X full-duplex capable.
1
13
100BASE-X Half-Duplex
Capable
RO
H
1 = 100BASE-X half-duplex capable.
0 = Not 100BASE-X half-duplex capable.
1
12
10BASE-T Full-Duplex
Capable
RO
H
1 = 10BASE-T full-duplex capable.
0 = Not 10BASE-T full-duplex capable.
1
11
10BASE-T Half-Duplex
Capable
RO
H
1 = 10BASE-T half-duplex capable.
0 = Not 10BASE-T half-duplex capable.
1
10
100BASE-T2 Full-Duplex
Capable
RO
L
1 = 100BASE-T2 full-duplex capable.
0 = Not 100BASE-T2 full-duplex capable.
0
9
100BASE-T2 Half-Duplex
Capable
RO
L
1 = 100BASE-T2 half-duplex capable.
0 = Not 100BASE-T2 half-duplex capable.
0
8
Extended Status
RO
H
1 = Extended status information in reg 0Fh.
0 = No extended status information in reg 0Fh.
1
7
Reserved
RO
Ignore on read.
0
6
Management Frames
Preamble Suppression
RO
H
1 = Preamble can be suppressed.
0 = Preamble always required.
1
5
Auto-negotiation Complete
RO
1 = Auto-negotiation is complete.
0 = Auto-negotiation is in progress.
0
4
Remote Fault
RO
LH
1 = Remote fault detected.
0 = No remote fault detected.
0
3
Auto-negotiation Ability
RO
H
1 = Auto-negotiation capable.
0 = Not auto-negotiation capable.
1
2
Link Status
RO
LL
1 = Link is up (link pass state).
0 = Link is down (link fail state).
0
1
Jabber Detect
RO
LH
1 = Jabber condition detected.
0 = No jabber condition detected.
0
0
Extended Capability
RO
H
1 = Extended register capabilities.
0 = No extended register capabilities.
1
tia
en
fid
on
C
om
dc
oa
Br
l
Bit
PHY Identifier Register (Page 10h–14h: Address 04h)
Table 131: PHY Identifier Register MSB (Page 10h–14h: Address 04–07h)
Bit
Name
R/W
Description
15:0
OUI
RO
Bits 3:18 of organizationally unique identifier 0x362 (hex)
Broadcom®
March 11, 2016 • 53125S-DS06-R
Default
Page 196
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 10h–14h: Internal GPHY MII Registers
Table 132: PHY Identifier Register LSB (Page 10h–14h: Address 06h–07h)
Bit
Name
R/W
Description
Default
15:10
OUI
RO
Bits 19:24 of organizationally unique
identifier
010111
9:4
MODEL
RO
Device model number
110010
3:0
REVISION
RO
Device revision number
na (hex)
a. The revision number (n) changes with each silicon revision.
l
The IEEE has issued an Organizationally Unique Identifier (OUI) to Broadcom Corporation. This 24-bit number
allows devices developed by Broadcom to be distinguished from all other manufacturers. The OUI combined
with model numbers and revision numbers assigned by Broadcom precisely identifies a device manufactured
by Broadcom.
en
tia
The [15:0] bits of MII register 02h (PHYID HIGH) contain OUI bits [3:18]. The [15:0] bits of MII register 03h
(PHYID LOW) contain the most significant OUI bits [19:24], six manufacturer’s model number bits, and four
revision number bits. The two
least significant OUI binary bits are not used.
on
fid
Broadcom Corporation's OUI is 00-0A-F7, expressed as hexadecimal values. The binary OUI is 0000-00000000-1010-1111-0111. The model number for BCM53125S is 38h. Revision numbers start with 0h and
increment by 1 for each chip modification.
PHYID HIGH[15:0] = OUI[3:18]
•
PHYID LOW[15:0] = OUI[19:24] + Model[5:0] + Revision [3:0]
om
C
•
dc
Auto-Negotiation Advertisement Register (Page 10h–14h: Address
08h)
Name
R/W
Description
Default
15
Next Page
R/W
1 = Next page ability is supported.
0 = Next page ability is not supported.
0
14
Reserved
R/W
Write as 0, ignore on read.
0
13
Remote Fault
R/W
1 = Advertise remote fault is detected.
0 = Advertise no remote fault is detected.
0
12
Reserved Technology
R/W
Write as 0, ignore on read.
0
11
Asymmetric Pause
R/W
1 = Advertise asymmetric pause.
0 = Advertise no asymmetric pause.
1
10
Pause Capable
R/W
1 = Capable of full-duplex pause operation. 1
0 = Incapable of pause operation.
9
100BASE-T4 Capable
R/W
1 = 100BASE-T4 capable.
0 = Not 100BASE-T4 capable.
Br
Bit
oa
Table 133: Auto-Negotiation Advertisement Register (Page 10h–14h: Address 08h–09h)
Broadcom®
March 11, 2016 • 53125S-DS06-R
0
Page 197
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 10h–14h: Internal GPHY MII Registers
Table 133: Auto-Negotiation Advertisement Register (Page 10h–14h: Address 08h–09h) (Cont.)
Bit
Name
R/W
Description
Default
8
100BASE-TX FullDuplex Capable
R/W
1 = 100BASE-TX full-duplex capable.
1
0 = Not 100BASE-TX full-duplex capable.
7
100BASE-TX HalfDuplex Capable
R/W
1 = 100BASE-TX half-duplex capable.
1
0 = Not 100BASE-TX half-duplex capable.
6
10BASE-T Full-Duplex
Capable
R/W
1 = 10BASE-T full-duplex capable.
0 = Not 10BASE-T full-duplex capable.
1
5
10BASE-T Half-Duplex
Capable
R/W
1 = 10BASE-T half-duplex capable.
0 = Not 10BASE-T half-duplex capable.
1
4
Protocol Selector Field
R/W
Bits [4:0] = 00001 indicates
IEEE 802.3 CSMA/CD.
0
R/W
0
2
R/W
0
1
R/W
0
R/W
en
tia
l
3
0
1
on
fid
Auto-Negotiation Link Partner Ability Register (Page 10h–14h:
Address 0Ah)
R/W
Description
Default
15
Next Page
RO
1 = Link partner has next page ability.
0 = Link partner does not have next page ability.
0
14
Acknowledge
1 = Link partner has received link code word.
0 = Link partner has not received link code word.
0
13
Remote Fault
RO
1 = Link partner has detected remote fault.
0 = Link partner has not detected remote fault.
0
12
Reserved Technology
RO
Write as 0, ignore on read.
0
11
Link Partner Asymmetric Pause RO
1 = Link partner wants asymmetric pause.
0 = Link partner does not want asymmetric pause.
0
10
Pause Capable
RO
1 = Link partner is capable of pause operation.
0 = Link partner is incapable of pause operation.
0
9
100BASE-T4 Capable
RO
1 = Link partner is 100BASE-T4 capable.
0 = Link partner is not 100BASE-T4 capable.
0
8
100BASE-TX Full-Duplex
Capable
RO
1 = Link partner is 100BASE-TX full-duplex capable. 0
0 = Link partner is not 100BASE-TX full-duplex
capable.
7
100BASE-TX Half-Duplex
Capable
RO
1 = Link partner is 100BASE-TX half-duplex capable. 0
0 = Link partner not 100BASE-TX half-duplex
capable.
om
Bit(s) Name
C
Table 134: Auto-Negotiation Link Partner Ability Register (Page 10h–14h: Address 0Ah–0Bh)
Br
oa
dc
RO
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 198
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 10h–14h: Internal GPHY MII Registers
Table 134: Auto-Negotiation Link Partner Ability Register (Page 10h–14h: Address 0Ah–0Bh) (Cont.)
Bit(s) Name
R/W
Description
Default
6
10BASE-T Full-Duplex Capable RO
1 = Link partner is 10BASE-T full-duplex capable.
0
0 = Link partner is not 10BASE-T full-duplex capable.
5
10BASE-T Half-Duplex Capable RO
1 = Link partner is 10BASE-T half-duplex capable.
0 = Link partner is not 10BASE-T half-duplex
capable.
0
4:0
Protocol Selector Field
Link partner protocol selector field.
0
RO
tia
l
Note: As indicated by bit 5 of the 10BASE-T/100BASE-TX/1000BASE-T MII Status register, the values
contained in the 10BASE-T/100BASE-TX/1000BASE-T Auto-negotiation Link Partner Ability register are
only guaranteed to be valid after auto-negotiation has successfully completed.
en
Next Page
fid
BCM53125S returns a 1 in bit 15 when the link partner wants to transmit Next Page information.
Acknowledge
C
on
BCM53125S returns a 1 in bit 14 when the link partner has acknowledged reception of the link code word;
otherwise, BCM53125S returns a 0.
om
Auto-Negotiation Expansion Register (Page 10h–14h: Address 0Ch)
Table 135: Auto-Negotiation Expansion Register (Page 10h–14h: Address 0Ch–0Dh)
Description
Default
15
Reserved
R0
Ignore on read.
0
14
Reserved
R0
Ignore on read.
0
13
Reserved
12
Reserved
R0
Ignore on read.
0
R0
Ignore on read.
0
11
Reserved
R0
Ignore on read.
0
10
Reserved
R0
Ignore on read.
0
9
Reserved
R0
Ignore on read.
0
8
Reserved
R0
Ignore on read.
0
7
Reserved
R0
Ignore on read.
0
6
Next Page Receive Location
Able
R/W
1 = Bit 5 in register 06h determines next page
receive location.
0 = Bit 5 in register 06h does not determine next
page receive location.
1
5
Next Page Receive Location
R/W
1 = Next pages stored in register 08h.
0 = Next pages stored in register 05h.
1
dc
R/W
oa
Name
Br
Bit
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 199
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 10h–14h: Internal GPHY MII Registers
Table 135: Auto-Negotiation Expansion Register (Page 10h–14h: Address 0Ch–0Dh) (Cont.)
Bit
Name
R/W
Description
Default
4
Parallel Detection Fault
RO
LH
1 = Parallel link fault is detected.
0 = Parallel link fault is not detected.
0
3
Link Partner Next Page Ability RO
1 = Link partner has next page capability.
0
0 = Link partner does not have next page capability.
2
Next Page Capable
RO
H
1 = BCM53125S is next page capable.
0 = BCM53125S is not next page capable.
1
Page Received
RO
LH
1 = New page has been received from link partner. 0
0 = New page has not been received.
0
Link Partner Auto-negotiation
Ability
RO
1 = Link partner has auto-negotiation capability.
0 = Link partner does not have auto-negotiation.
1
l
0
tia
Next Page Transmit Register (Page 10h–14h: Address 0Eh)
en
Table 136: Next Page Transmit Register (Page 10h–14h: Address 0Eh–0Fh)
Name
R/W
Description
15
Next Page
R/W
1 = Additional next pages follow.
0 = Sending last next page.
0
14
Reserved
RO
Ignore on read.
0
13
Message Page
R/W
1 = Formatted page.
0 = Unformatted page.
1
12
Acknowledge2
R/W
1 = Complies with message.
0 = Cannot comply with message.
Note: Not used with 1000BASE-T next
pages.
0
11
Toggle
10:1
Message/Unformatted Code
Field
on
C
om
dc
oa
Default
RO
Toggles between exchanges of different next 0
pages.
R/W
Next page message code or unformatted
data.
Br
0
fid
Bit
0
1
Link Partner Received Next Page Register (Page 10h–14h: Address
10h)
Table 137: Link Partner Received Next Page Register (Page 10h–14h: Address 10h–11h)
Bit(s)
Name
R/W
Description
Default
15
Next Page
RO
1 = Additional next pages follow.
0 = Sending last next page.
0
14
Acknowledge
RO
1 = Acknowledge.
0 = No acknowledge.
0
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 200
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 10h–14h: Internal GPHY MII Registers
Table 137: Link Partner Received Next Page Register (Page 10h–14h: Address 10h–11h) (Cont.)
Bit(s)
Name
R/W
Description
Default
13
Message Page
RO
1 = Formatted page.
0 = Unformatted page.
0
12
Acknowledge2
RO
1 = Complies with message.
0 = Cannot comply with message.
Note: Not used with 1000BASE-T next pages.
0
11
Toggle
RO
Toggles between exchanges of different next pages. 0
10:0
Message code field
RO
Next page message code or unformatted data.
0
1000BASE-T Control Register (Page 10h–14h: Address 12h)
R/W
Description
Default
15:13 Test Mode
R/W
1 X X = Test mode 4—Transmitter distortion test. 0
0 1 1 = Test mode 3—Slave transmit jitter test.
0 1 0 = Test mode 2—Master transmit jitter test.
0 0 1 = Test mode 1—Transmit waveform test.
0 0 0 = Normal operation.
12
Master/Slave
Configuration Enable
R/W
1 = Enable master/slave manual configuration
value.
0 = Automatic master/slave configuration.
0
11
Master/Slave
Configuration Value
R/W
1 = Configure PHY as master.
0 = Configure PHY as slave.
1
10
Repeater/DTE
R/W
1 = Repeater/switch device port.
0 = DTE device.
1
9
Advertise 1000BASE- R/W
T
Full-Duplex Capability
1 = Advertise 1000BASE-T full-duplex capability. 1
0 = Advertise no 1000BASE-T full-duplex
capability.
8
Advertise 1000BASE- R/W
T
Half-Duplex Capability
1 = Advertise 1000BASE-T half-duplex
capability.
0 = Advertise no 1000BASE-T half-duplex
capability.
1
7
Reserved
RO
Ignore on read.
0
6
Reserved
RO
Ignore on read.
0
5
Reserved
RO
Ignore on read.
0
en
Name
Br
oa
dc
om
C
on
fid
Bit
tia
l
Table 138: 1000BASE-T Control Register (Page 10h–14h: Address 12h–13h)
4
Reserved
RO
Ignore on read.
0
3
Reserved
RO
Ignore on read.
0
2
Reserved
RO
Ignore on read.
0
1
Reserved
RO
Ignore on read.
0
0
Reserved
RO
Ignore on read.
0
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 201
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 10h–14h: Internal GPHY MII Registers
Test Mode
The BCM53125S can be placed in 1 of 4 transmit test modes by writing bits [15:13] of the 1000BASE-T Control
register. The transmit test modes are defined in IEEE 802.3ab. When read, these bits return the last value
written. For test modes 1, 2, and 4, the PHY must have auto-negotiation disabled and forced to 1000BASE-T
mode and Auto-MDIX disabled.
•
Disable auto-negotiation and force to 1000BASE-T mode (write to register 00h = 0x0040)
•
Disable Auto-MDIX (write to register 18h, shadow value 111, bit 9 = 0)
•
Enter test modes (write to register 09h, bits [15:13] = the desired test mode)
Master/Slave Configuration Enable
tia
l
When bit 12 is set = 1, the BCM53125S master/slave mode is configured using the manual master/slave
configuration value. When the bit is cleared, the master/slave mode is configured using the automatic resolution
function. This bit returns a 1 when manual master/slave configuration is enabled; otherwise, it returns a 0.
en
1000BASE-T Status Register (Page 10h–14h: Address 14h)
fid
Table 139: 1000BASE-T Status Register (Page 10h–14h: Address 14h–15h)
Name
R/W
Description
15
Master/Slave Configuration Fault
RO
LH
1 = Master/slave configuration fault detected.
0 = No master/slave configuration fault detected.
14
Master/Slave Configuration
Resolution
RO
13
Local Receiver Status
12
Remote Receiver Status
11
Link Partner 1000BASE-T
Full-Duplex Capability
10
C
on
Bit
om
1 = Local transmitter is master.
0 = Local transmitter is slave.
Default
0
0
1 = Local receiver is OK.
0 = Local receiver is not OK.
0
RO
1 = Remote receiver is OK.
0 = Remote receiver is not OK.
0
RO
1 = Link partner is 1000BASE-T full-duplex
capable.
0 = Link partner is not 1000BASE-T full-duplex
capable.
0
Link Partner 1000BASE-T
Half-Duplex Capability
RO
1 = Link partner is 1000BASE-T half-duplex
capable.
0 = Link partner is not 1000BASE-T half-duplex
capable.
0
9
Reserved
RO
Ignore on read.
0
8
Reserved
RO
Ignore on read.
0
Br
oa
dc
RO
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 202
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 10h–14h: Internal GPHY MII Registers
Table 139: 1000BASE-T Status Register (Page 10h–14h: Address 14h–15h) (Cont.)
Bit
Name
R/W
Description
Default
7
Idle Error Count
RO
CR
Number of idle errors since last read.
0
RO
CR
0
5
RO
CR
0
4
RO
CR
0
3
RO
CR
0
2
RO
CR
0
1
RO
CR
0
RO
CR
0
0
on
fid
en
tia
l
6
om
C
Note: As indicated by bit 5 of the MII Status register (0h), the values contained in bits 14, 11, and 10 of
the 1000BASE-T Status register are guaranteed to be valid only after auto-negotiation has successfully
completed.
dc
IEEE Extended Status Register (Page 10h–14h: Address 1Eh)
Table 140: IEEE Extended Status Register (Page 10h–14h: Address 1Eh–1Fh)
R/W
Description
Default
15
1000BASE-X Full-Duplex
Capable
RO
L
1 = 1000BASE-X full-duplex capable.
0 = Not 1000BASE-X full-duplex capable.
0
14
1000BASE-X Half-Duplex
Capable
RO
L
1 = 1000BASE-X half-duplex capable.
0 = Not 1000BASE-X half-duplex capable.
0
13
1000BASE-T Full-Duplex
Capable
RO
H
1 = 1000BASE-T full-duplex capable.
0 = Not 1000BASE-T full-duplex capable.
1
12
1000BASE-T Half-Duplex
Capable
RO
H
1 = 1000BASE-T half-duplex capable.
0 = Not 1000BASE-T half-duplex capable.
1
11
Reserved
RO
Ignore on read.
0
10
Reserved
RO
Ignore on read.
0
9
Reserved
RO
Ignore on read.
0
8
Reserved
RO
Ignore on read.
0
7
Reserved
RO
Ignore on read.
0
6
Reserved
RO
Ignore on read.
0
oa
Name
Br
Bit
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 203
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 10h–14h: Internal GPHY MII Registers
Table 140: IEEE Extended Status Register (Page 10h–14h: Address 1Eh–1Fh) (Cont.)
Bit
Name
R/W
Description
Default
5
Reserved
RO
Ignore on read.
0
4
Reserved
RO
Ignore on read.
0
3
Reserved
RO
Ignore on read.
0
2
Reserved
RO
Ignore on read.
0
1
Reserved
RO
Ignore on read.
0
0
Reserved
RO
Ignore on read.
0
PHY Extended Control Register (Page 10h–14h: Address 20h)
Table 141: PHY Extended Control Register (Page 10h–14h: Address 20h–21h)
Name
R/W
Description
15
Reserved
R/W
Write as 0, ignore on read.
0
14
Disable Automatic MDI
Crossover
R/W
1 = Automatic MDI crossover is disabled.
0 = Automatic MDI crossover is enabled.
0
13
Transmit Disable
R/W
1 = Transmitter outputs are disabled.
0 = Normal operation.
0
–
fid
en
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Bit
Default
–
–
Bypass 4B/5B Encoder/
Decoder (100BASE-TX)
R/W
1 = Transmit and receive 5B codes over MII
pins.
0 = Normal MII.
9
Bypass Scrambler/Descrambler R/W
(100BASE-TX)
8
Bypass NRZI/MLT3 Encoder/
Decoder (100BASE-TX)
7
Bypass Receive Symbol
Alignment (100BASE-TX)
R/W
1 = The 5B receive symbols are not aligned. 0
0 = Receive symbols aligned to 5B
boundaries.
6
Reset Scrambler (100BASETX)
R/W
SC
1 = Reset scrambler to initial state.
0 = Normal scrambler operation.
0
5:3
Reserved
–
–
–
2
Reserved
R/W
Write as 0, ignore on read.
0
1
Reserved
R/W
Write as 0, ignore on read.
0
0
1000 Mbps PCS Transmit FIFO R/W
Elasticity
1 = High latency.
0 = Low latency.
0
C
0
1 = Scrambler and descrambler are disabled. 0
0 = Scrambler and descrambler are enabled.
om
R/W
dc
oa
Br
on
12:11 Reserved
10
1 = Bypass NRZI/MLT3 encoder and decoder. 0
0 = Normal operation.
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 204
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 10h–14h: Internal GPHY MII Registers
PHY Extended Status Register (Page 10h–14h: Address 22h)
Name
R/W
Description
Default
15
Auto-negotiation Base Page
Selector Field Mismatch
RO
LH
1 = Link partner base page selector field
mismatched advertised selector field since last
read.
0 = No mismatch detected since last read.
0
14
Ethernet@Wirespeed™
Downgrade
RO
1 = Auto-negotiation advertised speed downgraded. 0
0 = No advertised speed downgrade.
13
MDI Crossover State
RO
1 = Crossover MDI mode.
0 = Normal MDI mode.
0
12
Interrupt Status
RO
1 = Unmasked interrupt is currently active.
0 = Interrupt is cleared.
0
11
Remote Receiver Status
RO
LL
1 = Remote receiver is OK.
0 = Remote receiver is not OK since last read.
0
10
Local Receiver Status
RO
LL
1 = Local receiver is OK.
0 = Local receiver is not OK since last read.
0
9
Locked
RO
1 = Descrambler is locked.
0 = Descrambler is unlocked.
8
Link Status
RO
1 = Link pass
0 = Link fail
0
7
CRC Error Detected
RO
LH
1 = CRC error detected.
0 = No CRC error since last read.
0
6
Carrier Extension Error
Detected
5
Bad SSD Detected
(False Carrier)
4
Bad ESD Detected
(Premature End)
3
om
C
on
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Bit
en
Table 142: PHY Extended Status Register (Page 10h–14h: Address 22h–23h)
0
1 = Carrier extension error detected since last read. 0
0 = No carrier extension error since last read.
RO
LH
1 = Bad SSD error detected since last read.
0 = No bad SSD error since last read.
0
RO
LH
1 = Bad ESD error detected since last read.
0 = No bad ESD error since last read.
0
Receive Error Detected
RO
LH
1 = Receive error detected since last read.
0 = No receive error since last read.
0
2
Transmit Error Detected
RO
LH
1 = Transmit error code received since last read.
0
0 = No transmit error code received since last read.
1
Lock Error Detected
RO
LH
1 = Lock error detected since last read.
0 = No lock error since last read.
0
0
MLT3 Code Error Detected
RO
LH
1 = MLT3 code error detected since last read.
0 = No MLT3 code error since last read.
0
Br
oa
dc
RO
LH
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 205
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 10h–14h: Internal GPHY MII Registers
Receive Error Counter Register (Page 10h–14h: Address 24h)
Table 143: Receive Error Counter Register (Page 10h–14h: Address 24h–25h)a
Bit
Name
R/W
Description
Default
15:0
Receive Error Counter
R/W
CR
Number of noncollision packets with receive errors 0000h
since last read.
a. Bits 15:0 of this register become the 10BASE-T, 100BASE-TX, 1000BASE-T Receive Error Counter when
register 38h, shadow value11011, bit 9 = 0.
Copper Receive Error Counter
tia
l
When bit 9 = 0 in register 38h, shadow value 11011, this counter increments each time BCM53125S receives a
10BASE-T, 100BASE-TX, 1000BASE-T noncollision packet containing at least one receive error. This counter
freezes at the maximum value of FFFFh. The counter automatically clears when read.
en
False Carrier Sense Counter Register (Page 10h–14h: Address 26h)
fid
Table 144: False Carrier Sense Counter Register (Page 10h–14h: Address 26h–27h)a
Name
R/W
Description
Default
15:8
Reserved
RO
Ignore on read.
00h
7:0
False Carrier Sense Counter R/W
CR
Number of false carrier sense events since last
read.
00h
C
on
Bit
om
a. Bits 7:0 of this register become the 10BASE-T/100BASE-TX/1000BASE-T Carrier Sense Counter when register
38h, shadow 11011, bit 9 = 0 and register 3Ch, bit 14 = 0.
dc
Copper False Carrier Sense Counter
Br
oa
When bit 9 = 0 in register 1Ch, shadow value 11011 and bit 14 = 0 in register 3Ch, the False Carrier Sense
Counter increments each time the BCM53125S detects a 10BASE-T, 100BASE-TX, 1000BASE-T false carrier
sense on the receive input. This counter freezes at the maximum value of FFh. The counter automatically clears
when read.
10BASE-T/100BASE-TX/1000BASE-T Packets Received with
Transmit Error Codes Counter
Table 145: 10BASE-T/100BASE-TX/1000BASE-T Transmit Error Code Counter Register (Address 13h)a
Bit
Name
R/W
Description
Default
15:8
Reserved
RO
Write as 0, ignore on read.
00h
7:0
Transmit Error Code Counter R/W
CR
Number of packets received with transmit error
codes since last read.
00h
a. Bits 7:0 of this register become the 10BASE-T/100BASE-TX/1000BASE-T packets received with transmit error
codes counter when register 38h, shadow 11011, bit 9 = 0 and register 3Ch, bit 14 = 1.
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 206
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 10h–14h: Internal GPHY MII Registers
Packets Received with Transmit Error Codes Counter
BCM53125S detects a 10BASE-T/100BASE-TX/1000BASE-T packet with a transmit error code violation when
bit 9 = 0 in register 38h, shadow value 11011, and when bit 14 = 1 in register 1Eh, Packets Received with
Transmit Error Codes Counter increments each time. This counter freezes at the maximum value of FFh. The
counter automatically clears when read.
Receiver NOT_OK Counter Register (Page 10h–14h: Address 28h)
Table 146: Receiver NOT_OK Counter Register (Page 10h–14h: Address 28h–29h)a
Name
R/W
Description
Default
15:8
Local Receiver NOT_OK
Counter
R/W
CR
Number of times local receiver was NOT_OK since 00h
last read.
7:0
Remote Receiver NOT_OK
Counter
R/W
CR
Number of times BCM53125S detected that the
remote receiver was NOT_OK since last read.
00h
tia
l
Bit
fid
Copper Local Receiver NOT_OK Counter
en
a. Bits 15:0 of this register become the 10BASE-T, 100BASE-TX, or 1000BASE-T Receiver NOT_OK Counter
when register 38h, shadow 11011, bit 9 = 0 and register 3Ch bit 15 = 0.
C
on
When bit 9 = 0 in register 38h, shadow value 11011 and bit 15 = 0 in register 3Ch, this counter increments each
time the 10BASE-T, 100BASE-TX, or 1000BASE-T local receiver enters the NOT_OK state. This counter
freezes at the maximum value of FFh. The counter automatically clears when read.
om
Copper Remote Receiver NOT_OK Counter
oa
dc
When bit 9 = 0 in register 38h, shadow value 11011 and bit 15 = 0 in register 3Ch, this counter increments each
time the 1000BASE-T, 100BASE-TX, or 10BASE-T remote receiver enters the NOT_OK state. This counter
freezes at the maximum value of FFh. The counter automatically clears when read.
Br
Receive CRC Counter Register (Page 10h–14h: Address 28h)
Table 147: CRC Counter Register (Page 10h–14h: Address 28h–29h)a
Bit
Name
R/W
Description
Default
15:0
Receive CRC Counter
R/W
CR
Number of times receive CRC errors were
detected.
00h
a. Bits 15:0 of this register become the 10BASE-T, 100BASE-TX, or 1000BASE-T Receive CRC Counter when
register 38h, shadow 11011, bit 9 = 0 and register 3Ch bit 15 = 1.
Copper CRC Counter
When bit 9 = 0 in register 38h, shadow value 11011 and bit 15 = 1 in register 3Ch, this counter increments each
time the 10BASE-T, 100BASE-TX, or 1000BASE-T detects a receive CRC error. This counter freezes at the
maximum value of FFh. The counter automatically clears when read.
Broadcom®
March 11, 2016 • 53125S-DS06-R
Page 207
BROADCOM CONFIDENTIAL
BCM53125S Data Sheet
Page 10h–14h: Internal GPHY MII Registers
Auxiliary Control Shadow Value Access Register (Page 10h–14h:
Address 30h)
Available 30h registers are listed in the Table 148.
Table 148: Auxiliary Control Shadow Values Access Register (Page 10h–14h: Address 30h)
Register Name
000
”Auxiliary Control Shadow Values Access Register (Page 10h–14h: Address 30h)” on page
208
001
”10BASE-T Register (Page 10h–14h: Address 30h, Shadow Value 001)” on page 210
010
”Power/MII Control Register (Page 10h–14h: Address 30h, Shadow Value 010)” on page
211
100
”Miscellaneous Test Register (Page 10h–14h: Address 30h, Shadow Value 100)” on page
211
111
”Miscellaneous Control Register (Page 10h–14h: Address 30h, Shadow Value 111)” on
page 212
en
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Shadow Value
fid
Read from register 30h, shadow value zzz.
Table 149: Reading Register 30h
Description
Write register 30h, bits [2:0] = 111
This selects the miscellaneous control register, shadow value 111.
All reads must be done through the miscellaneous control register.
Bit 15 = 0
This allows only bits [14:12] and bits [2:0] to be written.
Bits [14:12] = zzz
This selects shadow value register zzz to be read.
om
C
on
Register Reads/Writes
Bits [11: 3] =
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