Data Sheet
BCM53134M
Multiport Ultra Low-Power Gigabit Ethernet Switch
General Description
Features
The Broadcom® BCM53134M is an ultra low-power, highly
integrated, cost-effective smart-managed Gigabit switch.
The switch design is based on the field-proven, industryleading ROBO architecture. This device combines all the
functions of a high-speed switch system including packet
buffers, PHY transceivers, media access controllers
(MACs), address management, port-based rate control, and
a nonblocking switch fabric into a single 28 nm CMOS
device. Designed to be fully compliant with the IEEE 802.3
and IEEE 802.3x specifications, including the MAC-control
PAUSE frame, the BCM53134M provides compatibility with
all industry-standard Ethernet, Fast Ethernet, and Gigabit
Ethernet (GbE) devices.
The BCM53134M has a rich feature set suitable for not only
standard GbE connectivity for broadband home gateways,
desktop, and laptop PCs, but also for next-generation
gaming consoles, set-top boxes, networked DVD players,
and home theater receivers. It is also specifically designed
for next generation SOHO/SMB routers and gateways.
The BCM53134M contains four full-duplex 10/100/
1000BASE-T Ethernet transceivers. In addition, the
BCM53134M has two PHY-less interfaces for the CPU or a
router chip, providing flexible 10/100/1000 Mb/s
connectivity. One RGMII interface can be connected to a
CPU entity and configured as an IMP (In-Band
Management port).
The second RGMII interface is available for another PHY,
modem, or CPU connection.
The BCM53134M provides 70+ on-chip MIB counters to
collect receive and transmit statistics for each port.
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Six 10/100/1000 media access controllers
Four-port 10/100/1000 transceivers for TX
One RGMII interface for an IMP for connection to a
CPU/management entity without PHY
One RGMII interface for a connection to another PHY,
CPU, or modem
IEEE 802.1p, MAC Port, TOS, and DiffServ QoS for six
queues, plus two time-sensitive queues
Port-based VLAN
IEEE 802.1Q-based VLAN with 4K entries
MAC-based trunking with automatic link failover
Port-based rate control
Port mirroring (Ingress/Egress)
Supports IPv4 and IPv6
Priority modification on egress
BroadSync® HD for IEEE 802.1AS support
Timestamp tagging at MAC interface
Time-aware egress scheduler
DOS attack prevention
IGMP Snooping, MLD snooping support
Spanning tree support (multiple spanning trees–up to
eight)
Embedded CPU (8051) processor for cable diagnostics
CableChecker™ with unmanaged mode support
Double tagging/QinQ
IEEE 802.az Energy Efficient Ethernet (EEE) support
IEEE 802.3x programmable per-port flow control and
backpressure, with IEEE 802.1X support for secure
user authentication
EEPROM, MDC/MDIO, and SPI Interface.
Serial Flash Interface for accessing embedded CPU
(8051)
4K entry MAC address table with automatic learning
and aging
128 KB packet buffer (1 KB = 1024 bytes)
128 multicast group support
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BCM53134M Data Sheet
Multiport Ultra Low-Power Gigabit Ethernet Switch
Features (Continued)
Jumbo frame support up to 9720 bytes
1.0V for core and 3.3V for I/O
RGMII with option of 3.3V/2.5V or 1.8V/1.5V
JTAG support
212-pin FBGA package
Figure 1: Functional Block Diagram
BCM53134M
TDP/N_0_[3:0]
(Port 0)
10/100/1000
GPHY
GMAC
TDP/N_1_[3:0]
(Port 1)
10/100/1000
GPHY
GMAC
TDP/N_2_[3:0]
(Port 2)
10/100/1000
GPHY
GMAC
TDP/N_3_[3:0]
(Port 3)
10/100/1000
GPHY
GMAC
WAN_RGMII
(Port 5)
IMP_RGMII
(Port 8)
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ContentAware
Compact Field
Processor
Registers
Packet Buffer MMU
Address
Management
GMAC
LED Interface
LED
8051 Micro
Controller
Flash
Memory
EEPROM/SPI
Interface
EEPROM/
CPU
GMAC
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BCM53134M Data Sheet
Multiport Ultra Low-Power Gigabit Ethernet Switch
Table of Contents
Chapter 1: Introduction ...................................................................................................................... 8
1.1 Overview ....................................................................................................................................................................8
1.2 Audience ....................................................................................................................................................................9
1.3 Data Sheet Information .............................................................................................................................................9
Chapter 2: Features and Operation ................................................................................................. 10
2.1 Overview ..................................................................................................................................................................10
2.2 Quality of Service and Scheduling ........................................................................................................................11
2.2.1 CoS Mapping ..................................................................................................................................................13
2.2.2 SF3 Egress Queues and Scheduler ...............................................................................................................14
2.2.2.1 Egress Transmit Queues ......................................................................................................................14
2.2.2.2 Scheduler..............................................................................................................................................15
2.2.3 Scheduling ......................................................................................................................................................17
2.2.4 Leaky Bucket Shaper......................................................................................................................................17
2.3 Port-Based VLAN ....................................................................................................................................................19
2.4 IEEE 802.1Q VLAN ..................................................................................................................................................19
2.4.1 IEEE 802.1Q VLAN Table Organization .........................................................................................................20
2.5 Double-Tagging.......................................................................................................................................................20
2.5.1 ISP Port...........................................................................................................................................................21
2.5.2 Customer Port.................................................................................................................................................21
2.5.3 Uplink Traffic (from Customer Port to ISP) .....................................................................................................22
2.5.4 Downlink Traffic (from ISP to Customer Port) .................................................................................................22
2.6 Egress VID Modification .........................................................................................................................................22
2.7 Jumbo Frame Support............................................................................................................................................23
2.8 Port Trunking/Aggregation ....................................................................................................................................23
2.9 WAN Port .................................................................................................................................................................24
2.10 Rate Control...........................................................................................................................................................25
2.10.1 Ingress Rate Control .....................................................................................................................................25
2.10.2 Two-Bucket System ......................................................................................................................................25
2.10.3 Egress Rate Control......................................................................................................................................26
2.10.4 Bucket Bit Rate .............................................................................................................................................26
2.11 Protected Ports .....................................................................................................................................................26
2.12 Port Mirroring ........................................................................................................................................................26
2.12.1 Enabling Port Mirroring .................................................................................................................................27
2.12.2 Capture Port..................................................................................................................................................27
2.12.3 Mirror Filtering Rules.....................................................................................................................................27
2.12.3.1 Port Mask Filter...................................................................................................................................27
2.12.3.2 Packet Address Filter..........................................................................................................................27
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2.12.3.3 Packet Divider Filter............................................................................................................................28
2.13 IGMP Snooping .....................................................................................................................................................28
2.14 MLD Snooping.......................................................................................................................................................28
2.15 IEEE 802.1X Port-Based Security ........................................................................................................................28
2.16 DoS Attack Prevention .........................................................................................................................................30
2.17 Compact Field Processor.....................................................................................................................................31
2.17.1 Parser ...........................................................................................................................................................32
2.17.1.1 L2 Framing Structure Parsing .............................................................................................................33
2.17.1.1.1 VLAN Tagging Structure Parsing ............................................................................................................... 33
2.17.1.1.2 Ethernet Framing Structure Parsing ........................................................................................................... 34
2.17.1.2 L3 Framing Structure Parsing .............................................................................................................35
2.17.1.2.1 IPv4 Header ............................................................................................................................................... 35
2.17.1.2.2 IPv6 Header ............................................................................................................................................... 36
2.17.1.2.3 IPv6 Extension Header............................................................................................................................... 36
2.17.1.3 L4 Framing Structure Parsing .............................................................................................................38
2.17.1.3.1
2.17.1.3.2
2.17.1.3.3
2.17.1.3.4
TCP Header ............................................................................................................................................... 38
UDP Header ............................................................................................................................................... 39
UDPLite Header ......................................................................................................................................... 40
ICMP/IGMP Headers.................................................................................................................................. 40
2.17.1.4 User Defined Field (UDF) Extraction ..................................................................................................40
2.17.1.4.1 UDF Offset Base Generation ..................................................................................................................... 40
2.17.1.4.2 UDF Specification....................................................................................................................................... 41
2.17.2 Search Key Composition ..............................................................................................................................42
2.17.3 Action Resolution ..........................................................................................................................................48
2.17.3.1 Policy Action Definitions .....................................................................................................................48
2.17.3.2 Metering/Statistics Selection...............................................................................................................50
2.18 Multiple Spanning Tree Protocol .........................................................................................................................50
2.19 Software Reset ......................................................................................................................................................51
2.20 BroadSync HD .......................................................................................................................................................51
2.20.1 Time Base and Slot Generation ....................................................................................................................51
2.20.2 Transmission Shaping and Scheduling.........................................................................................................52
2.20.2.1 BroadSync HD Class5 Media Traffic ..................................................................................................52
2.20.2.2 BroadSync HD Class4 Media Traffic ..................................................................................................52
2.21 CableChecker ........................................................................................................................................................53
2.22 Egress PCP Remarking ........................................................................................................................................54
2.23 Address Management...........................................................................................................................................55
2.23.1 Address Table Organization .........................................................................................................................55
2.23.2 Address Learning..........................................................................................................................................56
2.23.3 Address Resolution and Frame Forwarding .................................................................................................56
2.23.3.1 Unicast Addresses ..............................................................................................................................57
2.23.3.2 Multicast Addresses............................................................................................................................57
2.23.3.3 Reserved Multicast Addresses ...........................................................................................................59
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2.23.4 Static Address Entries...................................................................................................................................59
2.23.5 Accessing the ARL Table Entries .................................................................................................................60
2.23.5.1 Searching the ARL Table....................................................................................................................60
2.23.6 Address Aging...............................................................................................................................................60
2.23.6.1 Normal Aging ......................................................................................................................................60
2.23.6.2 Fast Aging...........................................................................................................................................60
2.24 Power Savings Modes ..........................................................................................................................................61
2.24.1 Auto Power-Down Mode ...............................................................................................................................61
2.24.2 Energy Efficient Ethernet Mode ....................................................................................................................61
2.24.3 Deep Green Mode ........................................................................................................................................62
2.25 Interrupt .................................................................................................................................................................62
Chapter 3: System Functional Blocks ............................................................................................ 63
3.1 Overview ..................................................................................................................................................................63
3.2 Media Access Controller ........................................................................................................................................63
3.2.1 Receive Function ............................................................................................................................................63
3.2.2 Transmit Function ...........................................................................................................................................64
3.2.3 Flow Control....................................................................................................................................................64
3.2.3.1 10/100 Mb/s Half-Duplex ......................................................................................................................64
3.2.3.2 10/100/1000 Mb/s Full-Duplex ..............................................................................................................64
3.3 Integrated 10/100/1000 PHY ...................................................................................................................................64
3.3.1 Encoder...........................................................................................................................................................65
3.3.2 Decoder ..........................................................................................................................................................65
3.3.3 Link Monitor ....................................................................................................................................................66
3.3.4 Digital Adaptive Equalizer ...............................................................................................................................66
3.3.5 Echo Canceler ................................................................................................................................................66
3.3.6 Crosstalk Canceler..........................................................................................................................................66
3.3.7 Analog-to-Digital Converter.............................................................................................................................66
3.3.8 Clock Recovery/Generator..............................................................................................................................67
3.3.9 Baseline Wander Correction ...........................................................................................................................67
3.3.10 Multimode TX Digital-to-Analog Converter ...................................................................................................67
3.3.11 Stream Cipher...............................................................................................................................................67
3.3.12 Wire Map and Pair Skew Correction .............................................................................................................68
3.3.13 Automatic MDI Crossover .............................................................................................................................68
3.3.14 10/100BASE-TX Forced Mode Auto-MDIX ...................................................................................................69
3.3.15 Resetting the PHY ........................................................................................................................................69
3.3.16 PHY Address ................................................................................................................................................69
3.3.17 Super Isolate Mode.......................................................................................................................................69
3.3.18 Standby Power-Down Mode .........................................................................................................................70
3.3.19 Auto Power-Down Mode ...............................................................................................................................70
3.3.20 External Loopback Mode ..............................................................................................................................70
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Multiport Ultra Low-Power Gigabit Ethernet Switch
3.3.21 Full-Duplex Mode ..........................................................................................................................................71
3.3.21.1 Copper Mode ......................................................................................................................................71
3.3.22 Master/Slave Configuration...........................................................................................................................72
3.3.23 Next Page Exchange ....................................................................................................................................72
3.4 Frame Management ................................................................................................................................................72
3.4.1 In-Band Management Port..............................................................................................................................72
3.4.2 Broadcom Tag Format for Egress Packet Transfer ........................................................................................74
3.4.3 Broadcom Tag Format for Ingress Packet Transfer........................................................................................75
3.5 MIB Engine...............................................................................................................................................................75
3.5.1 MIB Counters Per Port....................................................................................................................................76
3.6 Integrated High-Performance Memory..................................................................................................................82
3.7 Switch Controller ....................................................................................................................................................82
3.7.1 Buffer Management ........................................................................................................................................82
3.7.2 Memory Arbitration..........................................................................................................................................82
3.7.3 Transmit Output Port Queues .........................................................................................................................83
Chapter 4: System Interfaces .......................................................................................................... 84
4.1 Overview ..................................................................................................................................................................84
4.2 Copper Interface......................................................................................................................................................84
4.2.1 Auto-Negotiation .............................................................................................................................................84
4.2.2 Line-side (Remote) Loopback Mode ...............................................................................................................84
4.3 Frame Management Port Interface ........................................................................................................................84
4.3.1 RGMII Interface...............................................................................................................................................85
4.4 WAN Interface..........................................................................................................................................................85
4.5 Configuration Pins ..................................................................................................................................................85
4.6 Programming Interfaces.........................................................................................................................................85
4.6.1 SPI-Compatible Programming Interface .........................................................................................................86
4.6.1.1 SS: Slave Select ...................................................................................................................................86
4.6.1.2 SCK: Serial Clock .................................................................................................................................86
4.6.1.3 MOSI: Master Output Slave Input.........................................................................................................86
4.6.1.4 MISO: Master Input Slave Output.........................................................................................................86
4.6.1.5 External PHY Registers ........................................................................................................................88
4.6.1.6 Reading and Writing BCM53134M Registers Using SPI ......................................................................89
4.6.1.7 Normal Read Operation ........................................................................................................................90
4.6.1.8 Fast Read Operation ............................................................................................................................94
4.6.1.9 Normal Write Operation ........................................................................................................................97
4.6.2 EEPROM Interface .......................................................................................................................................100
4.6.2.1 EEPROM Format................................................................................................................................100
4.6.3 Serial Flash Interface ....................................................................................................................................102
4.6.4 MDC/MDIO Interface ....................................................................................................................................102
4.6.4.1 MDC/MDIO Interface Register Programming .....................................................................................103
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Multiport Ultra Low-Power Gigabit Ethernet Switch
4.6.4.2 Pseudo-PHY .......................................................................................................................................104
4.7 LED Interfaces .......................................................................................................................................................110
4.7.1 Dual Input Configuration/LED Output Function.............................................................................................114
4.8 Digital Voltage Regulator (LDO) ..........................................................................................................................115
Chapter 5: Hardware Signal Definitions ....................................................................................... 116
5.1 I/O Signal Types ....................................................................................................................................................116
5.2 Signal Descriptions...............................................................................................................................................117
Chapter 6: Pin Assignment ............................................................................................................ 123
6.1 Pin List by Pin Number.........................................................................................................................................123
6.2 Pin List by Pin Name.............................................................................................................................................130
Chapter 7: Electrical Characteristics ............................................................................................ 137
7.1 Absolute Maximum Ratings .................................................................................................................................137
7.2 Recommended Operating Conditions.................................................................................................................137
7.3 Electrical Characteristics .....................................................................................................................................138
Chapter 8: Timing Characteristics ................................................................................................ 140
8.1 Reset and Clock Timing .......................................................................................................................................140
8.2 RGMII Interface Timing .........................................................................................................................................141
8.2.1 RGMII Output Timing (Normal Mode) ...........................................................................................................141
8.2.2 RGMII Output Timing (Delayed Mode) .........................................................................................................142
8.2.3 RGMII Input Timing (Normal Mode)..............................................................................................................143
8.2.4 RGMII Input Timing (Delayed Mode) ............................................................................................................143
8.3 MDC/MDIO Timing.................................................................................................................................................145
8.4 Serial LED Interface Timing .................................................................................................................................147
8.5 SPI Timings............................................................................................................................................................147
8.6 JTAG Interface.......................................................................................................................................................149
8.7 EEPROM Timing....................................................................................................................................................149
Chapter 9: Thermal Characteristics .............................................................................................. 151
9.1 Package Only.........................................................................................................................................................151
9.2 Package Only with Heat Sink (50 x 50 x 35 mm3) ..............................................................................................151
9.3 Package Only.........................................................................................................................................................152
9.4 Package Only with Heat Sink (19 x 19 x 5 mm3) ................................................................................................152
Chapter 10: Mechanical Information ............................................................................................. 153
Chapter 11: Ordering Information ................................................................................................. 154
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BCM53134M Data Sheet
Multiport Ultra Low-Power Gigabit Ethernet Switch
Chapter 1: Introduction
1.1 Overview
The BCM53134M is a single-chip, six-port Gigabit Ethernet (GbE) switch device. It provides the following:
A six-port nonblocking 10/100/1000 Mb/s switch controller.
Four ports with 10/100/1000BASE-T compatible transceivers.
Six integrated Gigabit MACs (GMACs).
Two RGMII ports for PHY-less connection to the management agent (available only in full-duplex mode).
An integrated Motorola SPI-compatible interface.
High-performance, integrated packet buffer memory.
An address resolution engine.
A set of management information base (MIB) statistics registers.
The GMACs support full-duplex and half-duplex modes for 10 Mb/s and 100 Mb/s, and full-duplex for 1000 Mb/s. Flow
control is supported in half-duplex mode with backpressure. In full-duplex mode, IEEE 802.3x frame-based flow control is
supported. The GMACs are IEEE 802.3-compliant and support a maximum frame size of 9720 bytes.
The BCM53134M supports advanced ContentAware™ processing using a compact field processor (CFP). Up to four
intelligent ContentAware processes are performed in parallel for every packet. This flexible engine uses TCAM-based
architecture, which allows wildcard capabilities. Action examples include dropping, changing the forward port map, adding
forward port, assigning the priority of a frame, and so on. These advanced ContentAware processes are well suited for
access control lists (ACLs) and DoS prevention.
An integrated address management engine provides address learning and recognition functions at maximum frame rates.
The address table provides capacity for learning up to 4K unicast addresses. Addresses are added to the table after
receiving an error-free packet.
The MIB statistics registers collect receive and transmit statistics for each port and provide direct hardware support for the
Ether-like MIB, MIB II (interfaces), and the first four groups of the RMON MIB. All nine groups of RMON can be supported
by using additional capabilities, such as port mirroring/snooping, together with an external microcontroller to process some
MIB attributes. The MIB registers can be accessed through the Serial Peripheral Interface Port by an external
microcontroller.
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BCM53134M Data Sheet
Multiport Ultra Low-Power Gigabit Ethernet Switch
1.2 Audience
This document is for designers interested in integrating the BCM53134M switches into their hardware designs and for others
who need specific data about the physical characteristics and operation of the BCM53134M switches.
1.3 Data Sheet Information
The following notational conventions are used in this document:
Signal names are shown in uppercase letters (such as DATA).
A bar over a signal name indicates that it is active low (such as CE).
In register and signal descriptions, [n:m] indicates a range from bit n to bit m (such as [7:0] indicates bits 7 through 0,
inclusive).
The use of R or Reserved indicates that a bit or a field is reserved by Broadcom for future use. Typically, R is used for
individual bits and Reserved is used for fields.
Numerical modifiers such as K or M follow traditional usage (for example, 1 KB means 1,024 bytes, 100 Mb/s [referring
to fast Ethernet speed] means 100,000,000 b/s, and 133 MHz means 133,000,000 Hz).
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BCM53134M Data Sheet
Multiport Ultra Low-Power Gigabit Ethernet Switch
Chapter 2: Features and Operation
2.1 Overview
The BCM53134M switches include the following features:
“Quality of Service and Scheduling” on page 11
“Port-Based VLAN” on page 19
“IEEE 802.1Q VLAN” on page 19
“Double-Tagging” on page 20
“Jumbo Frame Support” on page 23
“Port Trunking/Aggregation” on page 23
“WAN Port” on page 24
“Rate Control” on page 25
“Protected Ports” on page 26
“Port Mirroring” on page 26
“IGMP Snooping” on page 28
“MLD Snooping” on page 28
“IEEE 802.1X Port-Based Security” on page 28
“DoS Attack Prevention” on page 30
“Compact Field Processor” on page 31
“Multiple Spanning Tree Protocol” on page 50
“Software Reset” on page 51
“BroadSync HD” on page 51
“CableChecker” on page 53
“Egress PCP Remarking” on page 54
“Address Management” on page 55
“Power Savings Modes” on page 61
The following sections discuss each feature in detail.
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BCM53134M Data Sheet
Multiport Ultra Low-Power Gigabit Ethernet Switch
2.2 Quality of Service and Scheduling
The Quality of Service (QoS) feature provides up to eight internal queues per port to support eight different traffic classes
(TCs). Traffic class is an internal representation of the priority of an incoming packet inside the device. The traffic class
assignment can be programmed so that the user can assign incoming packets to higher/lower TC priorities through TC
Mapping. Then, each TC is mapped to one of eight internal class-of-service (CoS) egress queues through TC-to-CoS
process. Packets assigned (mapped) to a higher priority output queue in the switch experience less delay than packets with
a lower priority under congested conditions. This can be important in minimizing latency for delay-sensitive traffic.
Figure 2 on page 12 shows how the BCM53134M determines the CoS and performs Priority Code Point (PCP) remarking
in packets.
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BCM53134M Data Sheet
Multiport Ultra Low-Power Gigabit Ethernet Switch
Figure 2: CoS and Egress Remarking Flow
IP P acket = (IP v 4 P acket || IP v 6 P acket)
T rus ted T agged P acket = ((V LAN T agged || P riority T agged) && T rus t_1P [Ingres s P ID])
DS C P 2T C Mapping
(G lobal)
Ingres s DS C P
S tatic MAC Des tination
Note: for untagged frames
. Ingres s P C P = Default P ort P C P
. Ingres s DE I = 0
T C _A
Ingres s P C P ,
Ingres s P ID,
Ingres s DE I
S1
S2
00
S0
SS S
21 0
111
T C _S E L_7
….
…….
001
T C _S E L_1
000
T C _S E L_0
T C _B
P C P 2T C Mapping
(P er Ingres s P ort)
01
Ingres s P ackets
P ort_T C [2:0]
DA2T C (AR L)
Mapping
(G lobal)
MAC DA, V LAN
T C _C
Lookup
T able
10
P ars ing Logic
(P er Ingres s P ort)
(P er Ingres s P ort)
Ingres s P ID
T C _D
P ID2T C Mapping
(P er Ingres s P ort)
11
C F P Actions ,
configurations
Mark
F low
P olicer
0
R E D/
WR E D
Drop
0
Q7
T C 2C OS
K eys
Mapping
(P er
Ingres s
port +
IMP )
1
C F P P riority
Modification
(G lobal)
T C [2:0]
C F P .C hange T C
B R C M_HDR .T C (from C P U)
C OS [2:0]
egres s _T C _o[2:0]
Q1
1
P er Ingres s
P ort
C onfiguration
/F unction
B R C M_HDR .E N &
~B R C M_HDR _R X_DIS
R eas on C odes
P ort_T C [2:0]
M
A
X
1
1
B R C M_HDR .T C (from C P U)
C F P .C hange T C _O
Broadcom Confidential
E gres s
T C 2P C P
(IMP 0,
IMP 1,
CPU
P ort)
R emarked
P C P [2:0]
Q7
0
Q1
Q0
0
0
C F P .New_T C _O
C P U_C OS [2:0]
R emarked
P C P [2:0]
S cheduler
and
S hapers
egres s _T C _o[2:0]
C P U2C OS
Mapping
(G lobal)
E gres s
T C 2P C P
(P er
E gres s
network
port)
Q0
Network
P ort
Queues
Q6
G lobal
C onfiguration
/F unction
P er E gres s
P ort
C onfiguration
/F unction
Q6
to IMP 0 and IMP 1 ports
C F P .New_T C
1
Note: egres s _T C _O[2: 0]
is us ed in the E gres s port logic
egres s _T C _O[2: 0]
IMP 0, IMP 1,
and C P U
Queues
Aggregation Mode or
non-IMP mode (per port:
S cheduler
and
S hapers
IMP 0, IMP 1) or C P U port
B R C M_HDR .E N &
~B R C M_HDR _R X_DIS
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The TC is selected from one of the following sources based on software configuration of an eight-entry lookup table
corresponding to the ingress port on which the packet was received.
DSCP-to-TC mapping table (DSCP2TC) (global function)
The TC of a packet received from an Ethernet (or IMP) port is assigned the TC configured for the corresponding IP
TOS/DSCP. When DSCP is disabled, or when the incoming packet is not of IPv4/v6 type, the TC that results from this
mapping is 000.
IEEE 802.1p PCP-to-TC mapping table (PCP2TC) (per ingress port function)
The TC of a packet received from an Ethernet (or IMP) port is assigned the TC configured for the corresponding IEEE
802.1p priority code point (PCP). When IEEE 802.1p tagging is disabled or when the incoming packet is not tagged, the
TC that results from this mapping is 000. The PCP of an ingress-tagged or priority-tagged packet is the same as the
PCP field in the outermost VLAN header in the packet. The PCP of an untagged packet is the same as the default PCP
register value corresponding to the port on which the packet was received.
TC from ARL table (DA2TC) (global function)
When using MACDA-based QoS, destination addresses and VLAN IDs are used to index the ARL table, as described in
“Address Management” on page 55. The matching ARL entry contains a 3-bit TC field, as shown. These bits set the
MACDA-based TC for the frame and TC can also be looked up from ARL table static entries. The MACDA-based TC is
assigned to the TC bits depending upon the result. The TC bits for a learned ARL entry default to 0.
Port-to-TC mapping table (PID2TC) (per ingress port function)
The TC of a packet received from an Ethernet (or IMP) port is assigned the TC configured for the corresponding port.
The mapping mechanism is enabled and disabled using Port ID to TC Mapping Register (Page 30h: Address 48h–4Bh)
programming. When disabled, the TC that results from this mapping is 000.
The Lookup Table is configured by software for each port separately. The TC generated from the CFP (one of the possible
CFP actions is changing TC) can override the TC value generated from the four methods described above (DSCP2TC,
PCP2TC, DA2TC, or PID2TC).
The Lookup Table is indexed by the following internal flags:
IP Packet. The flag indicates that the packet is either an IPv4 or IPv6 packet.
Trusted Tagged Packet. The flag indicates that the packet is either VLAN-tagged or priority-tagged, and was received
on a port that is configured as a trusted port.
Static MAC Destination. The flag indicates that the MAC destination address matched a static entry in the ARL table.
The TC_SEL_X is an 8-entry x 2-bits-per-entry table for every ingress port. One of the 8 entries (TC_SEL_7..TC_SEL_0) is
selected by a 3-bit address {S2, S1, S0}, where:
S2 = Static MAC Destination
S1 = Trusted Tagged Packet
S0 = IP Packet
The two bits (which are configurable by user) that are stored at the indexed entry in the table are then used to select one of
the following sources of TC (before it is optionally overridden by the CFP or the TC field in the Broadcom header):
00: TC_A
01: TC_B
10: TC_C
11: TC_D
2.2.1 CoS Mapping
All packets should be configured to be mapped to appropriate TCs and those TCs should be mapped to appropriate egress
queues through the TC2COS table.
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A packet may be sent to the CPU through the IMP0. An additional CPU2COS mapping table may be used for the packet in
nonaggregation mode to determine the CoS of those packets. The index to the mapping table entry is determined by a MAX
function that selects the maximum value of reason codes. A reason code indicates the reason why a packet is sent to the
CPU.
NOTE:
In addition to determining the CPU queue in nonaggregation mode, the reason code may also help software
process the packet in all modes. In aggregation mode, however, the CoS is determined by the same TC2COS
hardware mapping function that is used for network ports.
2.2.2 SF3 Egress Queues and Scheduler
2.2.2.1 Egress Transmit Queues
Each Ethernet egress port has eight transmit queues (CoS0–CoS7). Each CoS queue has its own dedicated counter to
measure the buffer occupancy of the queue for congestion management purposes. Every Ethernet (ingress) port has its own
set of counters to measure the buffer occupancy and the arrival rate related to the traffic received from the port.
The IMP (egress) port and port 5 also serve eight transmit queues. When the IMP port (or port 5) is set in non-aggregation
mode (for example, IMP port is configured as a management port to CPU), the CoS (output queue) is decided based on the
reasons for forwarding the packets to the CPU. When the IMP port (port 5) is set in aggregation mode (for example, IMP
port is configured as a regular data uplink port), the CoS is decided from the TC based the normal packet classification flow.
For the rest of Ethernet egress ports, all incoming frames are assigned to an egress transmit queue depending on their
assigned TC. Each egress transmit queue is a list that specifies an order for packet transmission. The corresponding egress
port transmits packets from each of the queues according to a programmable algorithm, with the higher TC queues being
given greater access than the lower TC queues. Queue 0 is the lowest-TC queue.
The queues and scheduler/shaper for each port are shown in the Figure 3 on page 14.
Figure 3: Queues and Scheduler/Shaper Diagram
cos7
Q7
cos6
Q6
cos5
Q5
cos4
Q4
cos3
Q3
cos2
Q2
cos1
Q1
cos0
Q0
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Shaper
SH7
Shaper
SH6
Shaper
SH5
Shaper
SH4
Shaper
SH3
Scheduler
(SP/+
WRR/+
WDRR)
Port
Shaper
SH8
Shaper
SH2
Shaper
SH1
Shaper
SH0
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2.2.2.2 Scheduler
The scheduling element can be configured to be one of the following operating modes:
1. Strict Priority.
2. Weighted Round Robin (WRR): packet-based scheduling.
3. Weighted Deficit Round Robin (WDRR): byte-based scheduling.
4. Or a mix of SP, WRR, and WDRR.
Table 1 lists various configuration options of the scheduler.
Table 1: Scheduler Configuration Selections
CoS7
CoS6
CoS5
CoS4
CoS3
SP
SP
SP
CoS2
CoS1
CoS0
Option 1
SP
SP
SP
SP
SP
Option 2
SP
WDRR/WRR WDRR/WRR WDRR/WRR WDRR/WRR
WDRR/WRR
WDRR/WRR
WDRR/WRR
Option 3
SP
SP
WDRR/WRR WDRR/WRR WDRR/WRR
WDRR/WRR
WDRR/WRR
WDRR/WRR
Option 4
SP
SP
SP
WDRR/WRR WDRR/WRR
WDRR/WRR
WDRR/WRR
WDRR/WRR
Option 5
SP
SP
SP
SP
WDRR/WRR
WDRR/WRR
WDRR/WRR
WDRR/WRR
Option 6
WDRR/WRR WDRR/WRR WDRR/WRR WDRR/WRR WDRR/WRR
WDRR/WRR
WDRR/WRR
WDRR/WRR
The operating mode of a scheduling queue/port can be configured independent of the operating mode of any other
scheduling queue/port in the device. One of the two round robin scheduling algorithms (WRR or WDRR) is selected through
a per-port configuration register.
Within the SP group, the precedence takes the ascending order of the CoS number. The higher the CoS number, the higher
the precedence for scheduling.
Within the WDRR group, the queues are selected based on the following round-robin rules:
The share can be weighted by assigning each queue its corresponding Weight in granularity of 1/256. If CoS2 is
assigned a weight of x/256, CoS1 is assigned a weight of y/256, and CoS0 is assigned a weight of z/256, the ratio of
transmitted packet bytes between Cos2:CoS1:CoS0 should be x:y:z in each Scheduling Round, if there is always a
packet waiting during the round.
A Scheduling Round is defined as a period within which each queue gets its fair share of packet transmission resource
in granularity of number of packets or number of sets of 256 bytes transmitted.
– At the beginning of each scheduling round:
Every queue’s share is added to its respective accumulated credit, and
Empty queues are noted and are not considered for scheduling in the scheduling round.
– During each scheduling round, queues with positive credits in respective queue shaper are serviced in order of CoS
(CoS7, CoS6, CoS5,….CoS0):
Empty queues as well as queues that do not have positive credits in the respective queue shaper are skipped.
When a queue is serviced, the number of packets transmitted from the queue depends on one of the two modes
of operations configured by software:
Burst Mode: one or more packets are transmitted from the queue when its fair share of packet transmission resources
is used up (credit becomes negative), or the queue becomes empty before the current scheduling round for the queue
ends. End of current scheduling round for a queue means the queue will not be serviced again in the current scheduling
round.
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Non-Burst Mode: one packet is transmitted from each queue in the CoS order (CoS7...0), until the fair share of packet
transmission resources of a queue is used up (credit becomes negative), or the queue becomes empty before the current
scheduling round for the queue ends. End of current scheduling round for a queue means the queue will not be serviced
again in the current scheduling round.
– Also, the negative accumulated credit of a non-empty queue from the current round is carried forward from the
current round to the beginning of the next round.
– If a queue becomes empty before its fair share is used up, the current scheduling round for the queue ends will
mean that the queue will not be serviced again in the current scheduling round. Also, its left-over credit is not carried
over to the next scheduling round, which means the deficit counter of an empty queue is set to zero (to avoid
carrying over accumulated credit history of empty queues). The action of setting the accumulated credit to zero is
independent of whether the queue became negative after serving the last packet in the queue, or it was still positive
after it served the last packet in the queue.
The scheduler algorithm goes back to Step “At the beginning of each scheduling round” to start the next round.
The weights of a WRR/WDRR scheduler can be configured independent of weights of any other WRR/WDRR scheduler in
the device.
The scheduler works by first servicing the SP queues. Queues have an intrinsic priority from high to low. That is, CoS7 has
higher priority than CoS6. The second scheduling option utilizes WRR/WDRR. The WRR/WDRR scheduling discipline
interleaves packets from queues based on a configured weight for the queues. That is, when a queue is selected for service
the depth of the queue is sampled. Packets are transmitted from the queue in the scheduling round until either the queue
becomes empty or the credit counter runs out of credits. Once these numbers of packets are serviced, then the next queue
is serviced. Queues are serviced in a round-robin fashion (WRR/WDRR) until this process is completed. Queues that do not
have packets to send in a round (either empty or do not have positive credits in respective queue shapers), are skipped and
not serviced. A queue is serviced only once in a round. If a packet arrives in a queue just after the scheduler decided to skip
a queue (because it was empty, became empty) in the current round, the packet will not be serviced in the current round by
the scheduler.
For example, assume the queue weights for CoS3–CoS0 are 4, 3, 2, 1 (or 1024, 768, 512, and 256 bytes) respectively, and
the scheduler is configured in burst mode of operation. Note that small weights have been used in this example for
simplification. In real applications, the minimum (WDRR weight * 256) should be ≥ MTU for correct behavior of the WDRR
scheduler. Because of programming error, if the weight of any DRR queue is configured such that (WDRR weight * 256) <
MTU, the behavior of the DRR scheduler is not predictable.
Assume an example of a scheduling round is similar to Figure 3 on page 14 where the frames are queued only in CoS3,
CoS1, and CoS0. CoS2 is empty through the entire round in this example. The egress packet stream created by the WDRR
scheduler is depicted where the number in a rectangle indicates the length of the packet in bytes. In the example, the WDRR
scheduler creates an egress packet stream by interleaving packets from CoS3, CoS1, and CoS0 (the non-empty queues
with accumulated weight > 0) in a fashion that depends on the WDRR weights assigned to the respective CoS.
In the example, assume a scheduling round started with zero accumulated credit for each of the four CoS queues. The
WDRR scheme will add credits to the four queues at the beginning of the round. Hence, there will be 1024 bytes
accumulated credits for CoS3, 0 for CoS2, 512 for CoS1, and 256 for CoS0. CoS2 accumulated credits at the beginning of
the round is 0 since it was either empty, or its shaper was blocked, or the shaper was enabled but did not have positive
credits. In the current round, the WDRR scheduler will service the queues in the following order:
1. The scheduler will service CoS3 first because it is the highest order CoS queue that has positive credits in the current
round. In the example, CoS3 has 494 bytes in four packets whereas its accumulated credits are 1024 bytes. Hence, it
became empty when it still had 530 positive accumulated credits. However, since the queue became empty before it
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could use up all its credits, the WDRR scheme will carry forward 0 accumulated credits for CoS3 to the next round. The
scheduler will not service CoS3 any more in the current round even if a new packet is stored in the queue while it is
servicing any remaining queues in the current round.
2. It will skip CoS2 next because it has 0 accumulated credits. The scheduler will carry forward 0 accumulated credits to
the next round for CoS2. The scheduler will not service CoS2 any more in the current round even if a new packet is stored
in the queue while it is servicing the remaining queues in the current round.
3. It will service CoS1 next because it has the next highest order CoS queue. CoS1 has 780 bytes in four packets, which
is more than 512 bytes of accumulated credits. Hence, the WDRR scheduler will stop servicing the queue and carry
forward -278 accumulated credits for CoS1 to the next round after the first three packets from the queue are transmitted.
The scheduler will not service CoS1 any more in the current round even if a new packet is stored in the queue while it is
servicing the remaining queues in the current round.
4. Finally, it will serve CoS0 and then end the current round. CoS0 has 204 bytes in two packets, which is a little less than
256 bytes of accumulated credits for CoS1. Since the queue will become empty before its positive credits are used up,
the WDRR scheduler will carry forward 0 credits for CoS0 to the next round. The scheduler will not service CoS0 any
more in the current round even if a packet arrives before the next round starts.
2.2.3 Scheduling
There are three shapers, SH2, SH1, and SH0, and they can be separately configured to be either a credit-based AVB shaper
that is compliant with the IEEE 802.1qav standard, or a standard Leaky Bucket rate limiter.
2.2.4 Leaky Bucket Shaper
Initially, the bucket is filled with tokens with a burst size (B). In every refresh interval, certain amounts of tokens are removed
from the bucket, which effectively determines the shaping rate. The scheduler services a packet based on the state
information of the shaper. If the bucket count is less than or equal to the burst size, the packet is in-profile. Otherwise, the
packet is out-of-profile. After servicing a packet, tokens are added into the bucket by an amount of tokens equivalent to the
size of the packet. In the BroadSync HD (AVB) shaping mode, the following additional token updates are required to reduce
the burstiness of the EAV traffic. After the bucket counter is updated, if the queue is empty and the bucket counter is less
than the burst size (B), reset the bucket counter to be equal to burst size (B). See Figure 4.
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Figure 4: Leaky Bucket Shaper
Packet
P3
P2
P1
Add Tokens
(Frame Departure)
Burst Size (B)
Bucket Count
Shaping Rate (R)
Remove Tokens
(Every Refresh Interval (I))
The leaky bucket shaper has the following parameters:
Refresh Interval (I): Defines the how often the tokens are removed from the buckets.
Shaping Rate (R): The rate at which the shaper limits service.
Burst Size (B): The maximum number of tokens that can be added into the bucket.
AVB Shaping Mode: Used to select AVB versus Normal shaping mode.
In every refresh interval, T tokens are removed from the bucket. T is the number of tokens. Associated with a token is a token
size (S). The shaper operates in byte-based mode, and the token size (S) is the number of bytes per token.
The relation between Shaping Rate (R), Refresh Interval (I) and Token Size (S) can be represented by formula:
R = T x (S/I)
NOTE:
The refresh interval is fixed at 7.8125 μs.
It is recommended that software configure the two shapers in the following way when applicable:
SH2 should be configured as:
– An AVB shaper for an AVB port with Class A traffic.
– A non-AVB shaper in all other applications.
SH1 should be configured as:
– An AVB shaper for an AVB port with Class B traffic.
– A non-AVB shaper in all other applications.
SH0 should be configured as a non-AVB shaper in all applications.
The Leaky Bucket threshold of a shaper can be configured in the range of 64 bytes–16 MB, with a resolution of 64 bytes.
When the shaper operates as an AVB shaper, the number of tokens in the shaper is saturated by hardware (made equal to
the configured threshold) when there is no packet at the shaper input. For example, if SH2 is configured as an AVB shaper
and Q5 is empty, then hardware forces the accumulated credits in SH2 to be the same as the threshold. Each shaper output
rate can be configured in the range of 64 Kb/s–1 Gb/s, with a resolution of 64 Kb/s.
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2.3 Port-Based VLAN
The port-based virtual LAN (VLAN) feature partitions the switching ports into virtual private domains designated on a perport basis. Data switching outside of the port’s private domain is not allowed. The BCM53134M provide flexible VLAN
configuration for each ingress (receiving) port.
The port-based VLAN feature works as a filter, filtering out traffic destined to nonprivate domain ports. For each received
packet, the ARL resolves the DA and obtains a forwarding vector (list of ports to which the frame will be forwarded). The
ARL then applies the VLAN filter to the forwarding vector, effectively masking out the nonprivate domain ports. The frame is
forwarded only to those ports that meet the ARL table criteria, as well as the port-based VLAN criteria.
2.4 IEEE 802.1Q VLAN
The BCM53134M support IEEE 802.1Q VLAN and up to approximately 4096 VLAN table entries that reside in the internal
embedded memory. Once the VLAN table is programmed and maintained by the microcontroller, the BCM53134M
autonomously handle all operations of the protocol. These actions include the stripping or adding of the IEEE 802.1Q tag,
depending on the requirements of the individual transmitting port. It also performs all the necessary VLAN lookups in addition
to MAC L2 lookups.
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2.4.1 IEEE 802.1Q VLAN Table Organization
Each VLAN table entry, also referred to as a VLAN ID, an untag map, and a forward map:
The untag map controls whether the egress packet is tagged or untagged.
The forward map defines the membership within a VLAN domain.
The FWD_MODE indicates whether the packet forwarding should be based on VLAN membership or on ARL flow.
The untag map and forward map include bit-wise representation of all the ports.
Figure 5: VLAN Table Organization
Entry 0
FWD_MODE MSTP_Index
UNTAG_MAP[8:0]
FORWARD_ MAP[8 :0]
Entry 1
Entry 2
Entry 4095
NOTE:
If the MII port is configured as a management port, then the tag is not stripped even if the untag bit is set.
2.5 Double-Tagging
The BCM53134M provide the double tagging feature, which is useful for ISP applications. When the ISP aggregates
incoming traffic from each individual customer, the extra tag (double tag) can provide an additional layer of tagging to the
existing IEEE 802.1Q VLAN. The ISP tag (extra tag) is a way of separating individual customers from other customers. Using
the IEEE 802.1Q VLAN tag, the individual customer’s traffic can be identified on a per-port basis.
When the double-tagging feature is enabled (register Page 34h, Address 05h, bit[3:2]) and the Enable IEEE 802.1Q (register
Page 34h, Address 00h, bit 7), users can expect two VLAN tags in a frame: the tag close to MAC_SA is the ISP tag, and the
one following is the customer tag as shown in Figure 6.
Figure 6: ISP Tag Diagram
MAC_DA
MAC _SA
ISP_TAG Customer_ tag Ty /Len
TPID
Payload
VID
The switch uses the ISP tag for ARL and VLAN table accesses and the customer tag as an IEEE 802.1Q tag. There is a perchip programmable register Double Tagging TPID register for ISP tag (default = 9100'h). All ISP tags will be qualified by this
Tag Protocol ID (TPID) value.
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When the double-tagging feature is enabled, all switch ports are separated into two groups: ISP ports and customer ports.
The BCM53134M performs the normalization process for all ingress frames for both Intelligent Double Tag (IDT) and Double
Tag (DT) modes, whether from the ISP port or customer port. The normalization process is to insert an ISP tag, customer
tag, or ISP + customer tag (depending on whether the ingress frame is without tags or with one tag) to allow all ingress
frames with double tags. However, if the ingress frames are with double tags (ISP + customer tag), and the ISP tag TPID
matches the TPID specified in the Double Tagging TPID register, it does not perform the normalization process. The ISP
ports are defined in the ISP Port Selection Portmap register. When the port(s) corresponding bit(s) are set, those port(s)
should be connected to the ISP, and otherwise connected to customers. Each switch device can have multiple ports
assigned as ISP ports, and each ISP is uniquely identified using different VLAN forward maps or the port-based VLAN
feature.
2.5.1 ISP Port
It is possible for the ISP port to receive three different types of frames: untagged, ISP-tagged, and ISP+Customer-tagged
frames.
When the double-tagging feature is enabled and the received frame is untagged (or the TPID does not match with ISP TPID
specified in Double Tagging TPID register, the default ISP tag and customer tag are added, and VLAN ID of ISP tag receives
it from the port default VID. The frames are forwarded according to the VLAN table. However, if the Port-Based VLAN Control
register is enabled, the egress ports specified in the port-VLAN control register override the VLAN table settings. If the
received frame is ISP tagged (TPID matches with the ISP tag VLAN ID specified in the double-tagging TPID register), the
default customer tag (8100 + default PVID) is added, the ISP VID is used to access the ARL table, and the ISP tag can be
stripped on the way out according to the untagged bit setting in the VLAN table. In addition, ISP port frame can forward to
the destination port directly based on forward port map of VLAN table by setting FWD_MODE bit to 1 of VLAN Table Entry
register.
The VLAN ID is generated from the ISP tag, and TC is generated from the ingress frame outer tag.
2.5.2 Customer Port
It is also possible for the Customer port to receive two different types of frames: untagged and Customer-tagged frames.
When the double-tagging feature is enabled, all the ingress frames preform the normalization process to insert an ISP tag
or ISP + Customer tag (depending whether the ingress frame is without tags or with one tag) to allow all ingress frames with
double tags. The VLAN ID of ISP tag receives it from the port default VID.
The VLAN ID is generated from the ISP tag, and the TC is generated from the ingress frame outer tag.
NOTE:
It is illegal to strip out the ISP tag on the ISP egress port by using the untagged bit setting in the VLAN table.
NOTE:
Only the VLAN tagged or untagged packets are expected for the ingress of the customer ports. The customer does
not add the ISP tags.
There are two possible traffic scenarios:
One scenario is from a customer port to an ISP port.
The second scenario is from an ISP port to a customer port.
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2.5.3 Uplink Traffic (from Customer Port to ISP)
Data traffic is traffic received from the customer port without tags or a customer tag, and the frame is destined for an ISP
port. The customer ingress port performs a normalization process to allow ingress frames with double tags (ISP + Customer
tag), and the ISP tag VID is based on the port default VID tag.
However, if the ingress frame is with an IEEE 802.1p tag, the VID of IEEE 802.1p tag is changed by the VID of the port default
VID tag after the customer port normalization process. The TC do not change.
Control traffic frames can be forwarded to the CPU first and then the CPU forwards to the ISP port if the switch management
mode is enabled and if the RESV_MCAST_FLOOD bit=0 in the Global VLAN Control 4 register. In this case, the control
frame adds an ISP tag by ingress port and forwards to the CPU. The CPU can then forward it to the ISP port with or without
the ISP tag by using the egress-direct feature.
2.5.4 Downlink Traffic (from ISP to Customer Port)
Data traffic frame received from the ISP port may or may not have an ISP tag attached. When the received frame does not
have an ISP tag and customer tag, the ISP ingress port does a normalization process to insert double tags (ISP + Customer
tag), and the ISP tag VID is based on the port default VID tag. All ARL and VID table access should be based on the new
tag. The traffic is then forwarded to the customer port through proper VLAN configuration. Usually, the software configures
so the customer Egress port continuously removes the ISP tag. However, it is based on how the untagged map is configured.
Moreover, if the ingress frame is with an IEEE 802.1p tag, the VID of the IEEE 802.1p tag is changed by the VID of the port
default VID tag after the ISP port normalization process. The TC will not change.
The Control traffic is forwarded to the CPU when the switch management mode is enabled and if RESV_MCAST_FLOOD
bit=0 in the Global VLAN Control 4 register. The BCM53134M can also support multiple ISP port configurations by enabling
the FWD_MODE bit of the VLAN Table Entry register.
There are also two ways to separate traffic that belongs to two different ISP customers:
1. Each group (ISP and customer) is assigned to the same VLAN group, so that traffic does not leak to other ISP.
2. Use the Port-based VLAN to separate traffic that belongs to a different ISP.
2.6 Egress VID Modification
The BCM53134M provides the egress VID remarking feature. The VID field of the outer tag or inner tag can be modified or
removed. This feature is port-dependent; each port can be set up differently. This feature is available only when Intelligent
Double Tag (IDT) mode is enabled (Page 34h, Address 05h, Bit[3:2]).
The BCM53134M performs the normalization process for all ingress packets when double-tag enabled (DT_Mode or
IDT_Mode).
At each egress port, the double-tag of a normalized packet is subject to VID modification before the packet is transmitted by
the corresponding port.
The egress VID modification instruction is generated through a mapping table indexed by the Egress Port ID and the
Classification ID generated from the CFP. Each egress port supports 256 entries to the VID mapping table (register Page
34h, Address 40h).
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Table 2: VID Modification Instruction Mapping
Index
VID Instruction for Outer Tag
VID Instruction for Inner Tag
{Egress Port ID,
Classification ID}
00 = Indicates the outer tag should be sent as the
internally normalized VLAN tag.
01 = Indicates the outer tag should be sent as the one
when the packet is received from its ingress port. If the
packet is received originally with an outer VLAN tag, it
should be sent out through the egress port with the
same outer VLAN tag, otherwise it should be sent out
without the outer VLAN tag.
10 = Remove outer tag before the packet is transmitted.
11 = VID modified on outer tag before the packet is
transmitted.
00 = Indicates the inner tag should be sent as the
internally normalized VLAN tag.
01 = Indicates the inner tag should be sent as the one
when the packet is received from its ingress port. If the
packet is received originally with an inner VLAN tag, it
should be sent out through the egress port with the
same outer VLAN tag, otherwise it should be sent out
without the inner VLAN tag.
10 = Remove inner tag before the packet is
transmitted.
11 = VID modified on inner tag before the packet is
transmitted.
2.7 Jumbo Frame Support
The BCM53134M can receive and transmit frames of extended length on ports linked at gigabit speed. Referred to as jumbo
frames, these packets are longer than the standard maximum size, but shorter than 9720 bytes. Jumbo packets can be
received or forwarded only to 1000BASE-T–linked ports that are jumbo-frame enabled. Up to 38 buffer memory pages are
required for storing the longest allowed jumbo frame. While there is no physical limitation to the number of ports that can be
jumbo enabled, it is recommended that no more than two be enabled simultaneously to ensure system performance. There
is no performance penalty for enabling additional jumbo ports beyond the potential strain on memory resources that can
occur due to accumulated jumbo packets at multiple ports.
2.8 Port Trunking/Aggregation
The BCM53134M supports MAC-based trunking. The trunking feature allows up to four ports to be grouped together as a
single-link connection between two switch devices. This increases the effective bandwidth through a link and provides
redundancy. The BCM53134M allow up to two trunk groups. Trunks are composed of predetermined ports and can be
enabled using the Trunking Group 0 register. Ports within a trunk group must be of the same linked speed. By performing a
dynamic hashing algorithm on the MAC address, each packet destined for the trunk is forwarded to one of the valid ports
within the trunk group. This method has several key advantages. By dynamically performing this function, the traffic patterns
can be more balanced across the ports within a trunk. In addition, the MAC-based algorithm provides dynamic failover. If a
port within a trunking group fails, the other port within the trunk automatically assumes all traffic designated for the trunk. It
allows for a seamless, automatic redundancy scheme. This hashing function can be performed on the DA, SA, or DA/SA.
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Figure 7: Trunking
Switch 1
Frame Z
Frame Y
Switch 2
Port X
Frame X
Port Y
Port Z
Port 0
One Pipe
Port 1
Port 2
2.9 WAN Port
The BCM53134M offers a programmable WAN port feature: a WAN Port Select register (page 00h, address 26h). Select a
port as a WAN port to forward all of that port's traffic to only the CPU port. The non-WAN port traffic from all other local ports
does not flood to the WAN port.
Figure 8 shows the WAN and LAN domain separation when the WAN port is selected.
Figure 8: WAN and LAN Domain Separation
IMP/ISP
LAN domain
LAN X
LAN Y
LAN Z
IMP/ISP
LAN Y
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WAN domain
LAN Z
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2.10 Rate Control
2.10.1 Ingress Rate Control
Forwarding broadcast traffic consumes switch resources, which can negatively impact the forwarding of other traffic. The
rate-based broadcast storm suppression mechanism is used to protect regular traffic from an overabundance of broadcast
or multicast traffic. This feature monitors the rate of ingressed traffic of programmable packet types. If the rates of these
packet types exceed the programmable maximum rate, the packets are dropped.
The broadcast storm suppression mechanism works on a credit-based rate system that figuratively uses a bucket to track
the bandwidth of each port (see Figure 9). Credit is continually added to the bucket at a programmable bucket bit rate. Credit
is decremented from the bucket whenever one of the programmable packet types is ingressed at the port. If no packets are
ingressed for a considerable length of time, the bucket credit continues to increase up to a programmable-maximum bucket
size. If a heavy burst of traffic is suddenly ingressed at the port, the bucket credit becomes drained. When the bucket is
emptied, incoming traffic is constrained to the bucket bit rate (the rate at which credit is added to the bucket). At this point,
excess packets either are dropped or deterred using flow control, depending upon the Suppression Drop mode.
Figure 9: Bucket Flow
Ingress Packet Rate
assigned to Bucket 1
Ingress Packet Rate
assigned to Bucket 2
Bucket 2 Bit Rate
Bucket 1 Bit Rate
Accumulated Credit
Accumulated Credit
BUCKET 1
BUCKET 2
If there is no accumulated credit available,
the switch does not accept input packets .
2.10.2 Two-Bucket System
For added flexibility, the BCM53134M employs two buckets to track the rate of ingressed packets. Each of the two buckets
(Bucket 0 and Bucket 1) can be programmed to monitor different packet types. For example, Bucket 0 could monitor
broadcast packets, while Bucket 1 monitors multicast packets. Multiple packet types can be monitored by each bucket, and
a packet type can be monitored by both buckets.
The rates of each bucket can be individually programmed. For example, the broadcast packets of Bucket 0 could have a
maximum rate of 3 Mb/s, whereas the multicast packets of Bucket 1 could be allowed up to 80 Mb/s. The size of each bucket
can be programmed. This determines the maximum credit that can accumulate in each bucket. The rate count and bucket
size can be individually programmed for each port, providing another level of flexibility. Suppression control can be enabled
or disabled on a per-port basis. This system allows the user to control dual packet-type rates on a per-port basis.
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2.10.3 Egress Rate Control
The BCM53134M monitors the rate of egress traffic per port. Unlike the ingress traffic rate control, the egress rate control
provides only the per-port rate control regardless of traffic types. This feature uses only one bucket to track the rate of
egressed packets. The egress rate control feature supports only absolute bit rate mode (Bit Rate Mode = 0), and the bucket
bit rate calculation is shown in Table 3.
2.10.4 Bucket Bit Rate
The relative ingress rates of each bucket can be programmed on a per-port basis. Each port has a programmable rate count
value for Bucket 0 and Bucket 1. Additionally, the bit rate mode is programmed on a chip basis. If this bit is 1, the packet rate
is automatically scaled according to the port link speed. Ports operating at 1000 Mb/s would be allotted a 100 times higher
ingress rate than ports linked at 10 Mb/s. Together, the rate count value and the bit rate mode determine the bucket bit rate,
which is a reflection of how quickly data can be ingressed (Kb/s) at the given port for a given bucket. The rate count values
are specified in Table 3. Values outside these ranges are not valid entries.
Table 3: Bucket Bit Rate
Approximate Computed
Bucket Bit Rate
Values (as a function of RC)
Rate Count (RC)
Bit Rate
Mode
Link Speed
Bucket Bit Rate
Equation
1–28
0
Any
(RC × 8 × 1M)/125
64 KB, 128 KB, 192 KB,..., 1.792 MB
29–127
0
Any
(RC – 27) × 1M
2 MB, 3 MB, 4 MB,..., 100 MB
128–240
0
Any
(RC – 115) × 1M × 8
104 MB, 112 MB, 120 MB,..., 1000 MB
1–125
1
10 Mb/s
(RC × 8 × 1M)/100
0.08 MB, 0.16 MB, 0.24 MB,..., 10 MB
1–125
1
100 Mb/s
(RC × 8 × 1M)/10
0.8 MB, 1.6 MB, 2.4 MB,..., 100 MB
1–125
1
1000 Mb/s
RC × 8 × 1M
8 MB, 16 MB, 24 MB,..., 1000 MB
NOTE: 1M represents 1 ×
106.
2.11 Protected Ports
The Protected Ports feature allows certain ports to be designated as protected. All other ports are unprotected. Traffic
between protected port group members is blocked. However, protected ports are able to send traffic to unprotected ports.
Unprotected ports can send traffic to any port. Several applications that can benefit from protected ports:
Aggregator: For example, all the available ports are designated as protected ports except a single aggregator port. No
traffic incoming to the protected ports is sent within the protected ports group. Any flooded traffic is forwarded only to
the aggregator port.
To prevent nonsecured ports from monitoring important information on a server port, the server port and nonsecured
ports are designated as protected. The nonsecured ports will not be able to receive traffic from the server port.
2.12 Port Mirroring
The BCM53134M support Port Mirroring, allowing ingress and/or egress traffic to be monitored by a single port designated
as the mirror capture port. The BCM53134M can be configured to mirror the ingress traffic and/or egress traffic of any other
port (s). Mirroring multiple ports is possible, but can create congestion at the mirror capture port. Several filters are used to
decrease congestion.
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2.12.1 Enabling Port Mirroring
Port Mirroring is enabled by setting the Mirror Enable bit.
Figure 10: Mirror Filter Flow
Port Mask Filter
Ingress Mirror Mask
Port Address Filter
Ingress Mirror Filter
Port Divider Filter
Ingress Mirror Divider
Capture Port
All
Packets
Egress Mirror Mask
Egress Mirror Filter
Egress Mirror Divider
Destination Port(s)
2.12.2 Capture Port
The capture port is capable of monitoring other specified ports. Frames transmitted and received at the other ports are
forwarded to the Capture port according to the mirror filtering rules discussed below.
2.12.3 Mirror Filtering Rules
Mirror filtering rules consist of a set of three filter operations (Port Mask, Packet Address, and Packet Divider) that are applied
to traffic ingressed and/or egressed at a switch port.
2.12.3.1 Port Mask Filter
The IN_MIRROR_MASK bits define the receive ports that are monitored. The OUT_MIRROR_MASK bits define the transmit
ports that are monitored.
Any number of ingress/egress ports can be programmed to be mirrored, but bandwidth restrictions on the one-mirror capture
port should be taken into account to avoid congestion or packet loss.
2.12.3.2 Packet Address Filter
The type of filtering that is applied to frames received on the mirrored ports is configurable. The IN_MIRROR_FILTER bits
select among the following where x is the 48-bit MAC address. Likewise, the type of filtering that is applied to frames
transmitted on the egressed mirrored ports:
Mirror all received frames
Mirror received frames with DA = x
Mirror received frames with SA = x
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2.12.3.3 Packet Divider Filter
The IN_DIV_EN bit allows further statistical sampling. When IN_DIV_EN = 1, the receive frames passing the initial filter are
divided by the value IN_MIRROR_DIV, which is a 10-bit value. Only one out of every n frames is forwarded to the mirror
capture port, where n = IN_MIRROR_DIV +1. This allows the following additional capabilities:
Mirror every nth received frame
Mirror every nth received frame with DA = x
Mirror every nth received frame with SA = x
NOTE:
When multiple ingress ports have been enabled in the IN_MIRROR_MASK, the cumulative total packet count
received from all ingress ports is divided by the value of IN_MIRROR_DIV to deliver the nth receive frame to the
mirror capture port. Egressed frames are governed by the OUT_MIRROR_MASK bit and the OUT_MIRROR_DIV
bit.
2.13 IGMP Snooping
The BCM53134M supports IP layer IGMP Snooping, which includes IGMP unknown, query, report, and leave message.
A frame with a value of 2 in the IP header protocol field and IGMP frames are forwarded to the CPU port. The management
CPU can then determine, from the IGMP control packets which port should participate in the multigroup session. The
management CPU proactively programs the multicast address in the ARL table or the multiport address entries. If the
IGMP_UKN_FWD_EN, IGMP_QRY_FWD_EN, IGMP_RPTLVE_FWD_EN is enabled, IGMP frames will be trapped to the
CPU port only.
2.14 MLD Snooping
The BCM53134M supports IP layer MLD Snooping, which includes MLD query, report, and done message. For of the query
and report/done message types, there are four options available: discard, forward normally, forward to CPU, or forward
normally and copy to CPU. The CPU is then expected to interpret these messages and configure the address table
accordingly.
2.15 IEEE 802.1X Port-Based Security
IEEE 802.1X is a port-based authentication protocol. By receiving and extracting special frames, the CPU can control
whether the ingress and egress ports should forward packets or not. If a user port wants service from another port
(authenticator), it must get approved by the authenticator. EAPOL is the protocol used by the authentication process. The
BCM53134M detects EAPOL frames by checking the destination address of the frame. The Destination addresses should
be either a multicast address as defined in IEEE 802.1X (01-80-C2-00-00-03) or a user-predefined MAC (unicast or
multicast) address. Once EAPOL frames are detected, the frames are forwarded to the CPU so it can send the frames to
the authenticator server. Eventually, the CPU determines whether the requestor is qualified or not based on its MAC_Source
addresses, and frames are either accepted or dropped. The per-port EAP can be programmed in the register.
BCM53134M provides three modes for implementing the IEEE 802.1X feature. Each mode can be selected by setting the
appropriate bits in the register.
The Basic Mode (when EAP Mode = 00'b) is the standard mode. The EAP_BLK_MODE bit is set before authentication
to block all of the incoming packets. Upon authentication, the EAP_BLK_MODE bit is cleared to allow all the incoming
packets. In this mode, the Source Address of incoming packets is not checked.
The second mode is Extended Mode (when EAP Mode = 10'b), where an extra filtering mechanism is implemented
after the port is authenticated. If the Source MAC address is unknown, the incoming packets would be dropped and the
unknown SA is not learned. However if the incoming packet is IEEE 802.1X packet, or special frames, the incoming
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packets is forwarded. The definition of the Unknown SA in this case is when the switch cannot match the incoming
Source MAC address to any of the addresses in ARL table, or the incoming Source MAC address matches the address
in ARL table, but the port number is mismatched.
The third mode is Simplified Mode (when EAP Mode = 11'b). In this mode, the unknown Source MAC address packets
would be forwarded to CPU rather than dropped. Otherwise, it is same as the Extended Mode operation.
NOTE:
The BCM53134M checks only the destination addresses to qualify EAPOL frames. Ethernet type fields, packet
type fields, or non-IEEE 802.1Q frames are not checked.
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2.16 DoS Attack Prevention
The BCM53134M supports the detection of the following DoS (Denial of Service) attack types based on register setting,
which can be programmed drop or not to drop each type of DoS packets respectively.
Table 4: DoS Attacks Detected by BCM53134M
DoS Attack Type
Description
IP_LAND
IPDA = IPSA in an IPv4/IPv6 datagram
TCP_BLAT
DPort = SPort in a TCP header carried in an unfragmented IP datagram or in the first fragment of a
fragmented IP datagram
UDP_BLAT
DPort = SPort in a UDP header carried in an unfragmented IP datagram or in the first fragment of a
fragmented IP datagram
TCP_NULLScan
Seq_Num = 0 and all TCP_FLAGs = 0 in a TCP header carried in an unfragmented IP datagram or in the
first fragment of a fragmented IP datagram
TCP_XMASScan
Seq_Num = 0, FIN = 1, URG = 1, and PSH = 1 in a TCP header carried in an unfragmented IP datagram or
in the first fragment of a fragmented IP datagram
TCP_SYNFINScan
SYN = 1 and FIN = 1 in a TCP header carried in an unfragmented IP datagram or in the first fragment of a
fragmented IP datagram
TCP_SYNError
SYN = 1, ACK = 0, and SRC_Port=1536)
Length ( Prohibit Access (RO/LH), for Page Number = 8'h1X, which are PHY MII registers.
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Figure 50: Pseudo-PHY MII Register 24: Access Register Bit Definition
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access register bits [15:0]
Bit #
Reg 24
bits [15:0] => Access register bits [15:0] (RW)
Figure 51: Pseudo-PHY MII Register 25: Access Register Bit Definition
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access register bits [31:16]
Bit #
Reg 25
bits [15:0] => Access register bits [31:16] (RW)
Figure 52: Pseudo-PHY MII Register 26: Access Register Bit Definition
15
14
13
12
11
10
9
8
7
6
Access register bits [47:32]
5
4
3
2
1
0
Bit #
Reg 26
bits [15:0] => Access register bits [47:32] (RW)
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Figure 53: Pseudo-PHY MII Register 27: Access Register Bit Definition
15
14
13
12
11
10
9
8
7
6
Access register bits [63:48]
5
4
3
2
1
0
Bit #
Reg 27
bits [15:0] => Access register bits [63:48] (RW)
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Figure 54: Read Access to the Register Set using the Pseudo-PHY (PHYAD = 11110) MDC/MDIO Path
Write MII register 16:
Set bit 0 as 1
Set Page Number to bits [15:8]
Write MII register 17:
Set Operation Code as 10
Set register address to bits [15:8]
Read MII register 17:
Check op_code = 00?
No
Yes
Read MII register 24:
for Access register bits [15:0]
Read MII register 25:
for Access register bits [31:16]
Read MII register 26:
for Access register bits [47:32]
Read MII register 27:
for Access register bits [63:48]
No
New Page Access?
Yes
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Figure 55: Write Access to the Register Set using the Pseudo-PHY (PHYAD = 11110) MDC/MDIO Path
Write MII register 16:
Set bit 0 as 1
Set Page Number to bits [15:8]
Write MII register 24:
for Access register bits [15:0]
Write MII register 25:
for Access register bits [31:16]
Write MII register 26:
for Access register bits [47:32]
Write MII register 27:
for Access register bits [63:48]
Write MII register 17:
Set Operation Code as 01
Set register address to bits [15:8]
Read MII register 17:
Check op_code = 00?
No
Yes
No
New Page Access?
Yes
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Table 30 summarizes the complete management frame format.
Table 30: MII Management Frame Format
ST
OP
PHYAD
Read
Operation
PRE
1 ... 1
01
10
AAAAA
RRRRR
Write
1 ... 1
01
AAAAA
RRRRR
01
REGAD
TA
ZZ
Z0
10
Data
Direction
Z ... Z
D ... D
Driven by master
Driven by slave
D ... D
Driven to master
See “MDC/MDIO Interface” on page 102 for more information regarding the timing requirements.
4.7 LED Interfaces
The BCM53134M provides flexible, programmable per-port status of various functions. The user can select predefined LED
displays per port by setting the LED_MODE strap pins. Alternatively, the user can program different display functions and
different sets of display functions for different ports by programming the LED Control registers. Normally the BCM53134M
offers a total of 16 LED displays with four functions per port when the WAN (port 5) RGMII interface is not used, or a total
of eight LED displays with two functions per port when the WAN (port 5) RGMII interface is used. The LED interface offers
options to display different functions.
The options that are available for the LED display include the following:
Number of displays per port
Display functions per port
LED lighting behavior
The total number of displays per port is based on the GMII_LED_DEL strap-pin option. When the GMII (port 5) is used, the
16-LED display option is not available. The LED[xx] signal allocation for each port is shown in Table 31, 8-LED Display Mode
(WANLEDSEL=0).
The options for the number of LED displays are as follows:
16 LED displays total (WANLEDSEL = 1).
– Four display functions per port.
– LED[0:9] active state will be depends on the strap pin state. The LED active state will follow the same as the strap
state. (for example, if the strap pin is pulled up, LED active state is high, and vice versa)
– LED[10:15] active state is low. These LED pins will be always active-low, regardless of external/internal pull up or
pull down.
Eight LED displays total (WANLEDSEL = 0). This mode is forced when GMII (port 5) is used for data interface.
– Two display functions per port
– LED[0:7] active state depends on the strap pin state. The LED active state will follow the same as the strap state. (for
example, if the strap pin is pulled up, the LED active state is high. If the strap pin is pulled low, the LED active state
is low.)
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The options for the different function displays per port are as follows:
Using default display settings through the strap pins LED_MODE[1:0].
– The different displays per LED_MODE settings are shown in Table 31. Each LED [xx] signal is assigned to a specific
port. For example, if the port 3 and port 2 LED displays are disabled (register Page 00h, Address 16h = 0003), port 0
and port 1 LED display are still from LED pins LED[0~3] (port 0), LED[4~7] (port 1), just as if all four ports were used.
If port 1 and port 0 LED displays are disabled (register Page 00h, Address 16h = 001C), port 2 and port 3 are still
from LED pins LED[8~11] (port 2), and LED[12~15] (port 3), also just as if all four ports were used.
– All the ports are displaying a same set of functions based on the strap pin settings. The display is fixed per port and
per pin as shown in Table 31.
Displaying one of two different display settings through programming the LED configuration registers.
– Option to enable LED display per port (register Page 00h, Address 16h).
– There are two sets of displays options the user can set through the LED Function Control Register 0 and 1 (register
Page 00h, Address 10h, and 12h).
– Each port can select one of two display functions (register Page 00h, Address 14h).
NOTE:
For additional details about how to program LED-related registers, see the BCM53134 application note, Layout
and Design Guide (53134-AN1xx-R).
The options for different LED lighting behavior (register Page 00h, Address 18h, and 1Ah) are as follows:
Automatic mode: All the modes indication is in a steady state, except the activity state, which is blinking.
Blink mode: All the status indication is blinking. The blinking rate can be set through the register page 00h, address 0Fh,
bit [2:0].
ON mode: Forces the LED to be on.
In serial LED pins, the status of the enabled ports is sent out with the highest port number first with the lowest port number
last. Within a port, the highest (in terms of bit number) selected functionality in LED Function Control Register 0/1 is sent out
first followed by lower (in terms of bit number) selected functionality in LED Function Control Register 0/1.
For parallel LED pins, lower ports are mapped to lower LED pins. Port0 is mapped to the lowest LED pins (LED[3:0] or
LED[1:0] depending on 16-bit LED or 8-bit LED mode). Port1 is mapped to LED[7:4] or LED[3:2] (depending on 16-bit or 8bit LED mode). Within a port, the lower (in terms of bit number) selected functionality is LED function Control Register 0/1 is
mapped to lower LED pin.
Table 31: 8-LED Display Mode (WANLEDSEL=0)
Port 0
Port 1
Port 2
Port 3
LED_MODE=
2'b11
2’b10
2’b01
2’b00
LED[1]
LED[3]
LED[5]
LED[7]
10M/ACT
LNK/ACT
DPX/COL
LNK/ACT
LED[0]
LED[2]
LED[4]
LED[6]
DPX
DPX
PHYLED4
PHYLED4
2’b01
2’b00
Table 32: 16-LED Display Mode (WANLEDSEL=1)
Port 0
Port 1
Port 2
Port 3
LED_MODE=
2'b11
2’b10
LED[3]
LED[7]
LED[11]
LED[15]
1G/ACT
SPD1G
1G/ACT
SPD1G
LED[2]
LED[6]
LED[10]
LED[14]
100M/ACT
SPD100M
10_100/ACT
SPD100M
LED[1]
LED[5]
LED[9]
LED[13]
10M/ACT
LNK/ACT
DPX/COL
LNK/ACT
LED[0]
LED[4]
LED[8]
LED[12]
DPX
DPX
PHYLED4
PHYLED4
Figure 56 shows the LED Interface register structure.
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Figure 56: LED Interface Register Structure Diagram
LED Function Control Register 0
Available Functions
Selected Functions
LED Function Control Register 1
Available Functions
15 : PHYLED3
15 : PHYLED3
14 : BroadSync HD Link
14 : BroadSync HD Link
13 : 1G/ACT
12 : 10 /100 M/ACT
13 : 1G/ACT
12 : 10/100 M/ACT
11 : 100M/ACT
10 : 10M/ACT
9 : SPD1G
8 : SPDI00M
7 : SPD10M
Selected Functions
11 : 100M/ACT
1G/ACT
LNKL/ACTG
DPX/COL
LNK
10 : 10M/ACT
9 : SPD1G
8 : SPDI00M
7 : SPD10M
LNKG/ACTL
SPD100M
6 : DPX/COL
6 : DPX/COL
5 : LNK/ACT
5 : LNK/ACT
4 : COL
4 : COL
3 : ACT
2 : DPX
3 : ACT
2 : DPX
1 : LNK
1 : LNK
0 : PHYLED4
0 : PHYLED4
Reserved
1 1
0
0
LED Function Map Register
Reserved
1 1
0
0
LED Enable Map Register
1 0
1
1 Port Mode Map 0 Register 0 1 0 1
1 1
0
0 Port Mode Map 1 Register 0 0 1 1
Reserved
Note:
PHYLED3 and PHYLED4 are the output of the
functions that are selected in the LED Selector 2
Register (Page10h– 14h: Address 38P Shadow
value 01110'b)
3
2 1
0
Port / Bit #
LED AUTO
LED BLINK
LED ON
LED OFF
The BCM53134M offers two LED Interfaces: a parallel LED interface and a serial interface. As shown in Figure 57 on page
113, the source of the LED status stream is the same for both interfaces. The status bit stream is based on the programmed
register settings. The Parallel LED Interface provides all the shifting and storing of the status internally so that it does not
require any external shift registers, but it requires more I/O pins to be connected on the part. The active level of the LED
DATA signal can be low or high, depending on the strap pin configuration of each LED signal in the parallel LED interface
output. The determination of the active state is shown in “Dual Input Configuration/LED Output Function” on page 114.
The serial LED interface is output through two pins (LEDDATA and LEDCLK), saving the number of I/O pins but requiring
the user to design in the external shift registers. The serial LED interface provides the LED display of port 0 to port 3. The
active level of the LED DATA signal is low for each status in the serial LED interface output.
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In serial LED mode, all LEDs are active low. In parallel LED mode, the LED active state is described in the previous
pages.
Figure 57: LED Interface Block Diagram
LED I/O Block
LED Control Block
LEDCLK
LEDDATA
LED[09]
Q
D
LED[08]
Q
D
LED[07]
Q
D
LED[0]
Q
D
NOTE:
There is a difference between the serial LED and the parallel LED display mode. In parallel LED mode, there is a
fixed number of pins assigned to a specific port. In 16 LED display mode, there are four fixed LED signals assigned
to each port and four LED signal pins are fixed to each port, even if the user decided to display 3, 2, or 1 LED
functions per port. In serial LED mode, only the selected number of LED functions will be shifted out, so there is
no gap between each port when the user displays 2, 3, or 4 functions per port. If the user displays/enables only
three LED functions per port, then different port LED functions will be shifted out at every 4th function.
A dual LED is used for displaying more than one status using one LED cell. By packing two different-colored LEDs into one
holder, a dual LED can display more than two states in one cell. Figure 58 shows typical dual LED usage. The green LED
displays LNKG/ACT status, while the yellow LED displays LNKF/ACT status.
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Figure 58: Dual LED Usage Example
Green LED
LNKF/ACT
LNKG/ACT
Yellow LED
4.7.1 Dual Input Configuration/LED Output Function
There are 10 LED pins that have secondary functions. These pins serve as input pins during the power-on/reset sequence.
The logic level of the pin is sampled at reset and configures the secondary function. After the reset process is completed,
the pin acts as an output LED during normal operation. The polarity of the output LED is determined based on the latched
input value at reset. For example, if the value at the pin is high during reset, the LED output during normal operation is activehigh. The user must first decide, based on the individual application, the values of the input configuration pin shown in
Table 33 to provide the correct device configuration. The LED circuit must then be configured to accommodate either an
active-low or an active-high LED output.
Table 33: Input Configuration/LED Output Function
LED Output Pins
Input Configuration Pins
Internal Default Pull-ups and
Pull-downs
Active State
LED[0]
–
Pull-down
Same as strap pin state
LED[1]
SKIp_RAM_BIST
Pull-up
Same as strap pin state
LED[2]
IMP_VOL_SEL
Pull-down
Same as strap pin state
LED[3]
CLKFREQ[1]
Pull-up
Same as strap pin state
LED[4]
WAN MODE
Pull-down
Same as strap pin state
LED[5]
–
Pull-down
Same as strap pin state
LED[6]
IMP MODE
Pull-down
Same as strap pin state
LED[7]
–
Pull-down
Same as strap pin state
LED[8]
CPU_EEPROM_SEL
Pull-up
Same as strap pin state
LED[9]
HW_FWDG_EN
Pull-up
Same as strap pin state
NOTE:
For LEDs whose Active State is same as strap pin state only, if the signal is pulled up/down, the LED is active high/
low.
NOTE:
Refer to the LED Interface Design Guidelines application note for LED interface design consideration, and the LED
function behavior difference between the BCM53134M A0 and B0 chips.
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Figure 59: Dual Input Configuration/LED Output Function
Switch
Switch
3.3V
3.3V
Active HIGH
LED signal
Active HIGH
LED signal
GND
GND
3.3V
3.3V
Active LOW
LED signal
Active LOW
LED signal
GND
GND
Note: When LED signal pins are pulled up or down through an external or an internal termination due to the strap pin
configuration, the active states of LED signals are as follows:
o
If the signal is pulled up, the LED is active high.
o
If the signal is pulled low, the LED is active low.
4.8 Digital Voltage Regulator (LDO)
The BCM53134M LDO generates a 1.8V power supply. The 1.8V is used internally as an intermediate voltage level in
28 -nm technology.
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Chapter 5: Hardware Signal Definitions
5.1 I/O Signal Types
The following conventions are used to identify the I/O types. The I/O pin type is useful in referencing the DC pin
characteristics.
Table 34: I/O Signal Type Definitions
Abbreviation
Description
XYZ
Active-low signal
3T
3.3V tolerant
A
Analog pin type
B
Bias pin type
CS
Continuously sampled
D
Digital pin type
DNC
Do not connect
GND
Ground
I
Input
I/O
Bidirectional
IPU
Input with internal pull-up
O3S
Tristated signal
ODO
Open-drain output
O
Output
PD
Internal pull-down
SOR
Sample on reset
PWR
Power pin supply
PU
Internal pull-up
XT
Crystal pin type
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5.2 Signal Descriptions
Table 35: Signal Descriptions
Signal Name
Type and
Default
State
Description
PHY Interface
TDP0_0
Bi
TDN0_0
Bi
TDP0_1
Bi
TDN0_1
Bi
TDP0_2
Bi
TDN0_2
Bi
TDP0_3
Bi
TDN0_3
Bi
TDP1_0
Bi
TDN1_0
Bi
TDP1_1
Bi
TDN1_1
Bi
TDP1_2
Bi
TDN1_2
Bi
TDP1_3
Bi
TDN1_3
Bi
TDP2_0
Bi
TDN2_0
Bi
TDP2_1
Bi
TDN2_1
Bi
TDP2_2
Bi
TDN2_2
Bi
TDP2_3
Bi
TDN2_3
Bi
TDP3_0
Bi
TDN3_0
Bi
TDP3_1
Bi
TDN3_1
Bi
TDP3_2
Bi
TDN3_2
Bi
TDP3_3
Bi
TDN3_3
Bi
Broadcom Confidential
TDP[port#]_[ch#], TDN[port#]_[ch#] are Transmit/Receive Pairs. In TRP/N [port
number]_[channel number] for 1000BASE-T mode, differential data from the media is
transmitted and received on all four signal pairs. In auto-negotiation and 10BASE-T and
100BASE-TX modes, the BCM53134M normally transmits on TRP/N[port #]_[0] and
receives on TRD[port#]_[1].
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Table 35: Signal Descriptions (Continued)
Signal Name
Type and
Default
State
Description
RESET/Clock
RESET_L
I, Pu
Hardware Reset Input. Active low Schmitt-triggered input. Resets the BCM53134M.
Active low.
XTAL_P
I
XTAL_N
I
50 MHz Crystal Input/Output. A continuous 50 MHz reference clock must be supplied to
the BCM53134M by connecting a 50 MHz crystal between these two pins or by driving
XTALI with a clock. When using a crystal, connect a loading capacitor from each pin to
GND.
NOTE: BCM53134 (A0) supports 50 MHz crystal reference clock input only.
NOTE: BCM53134 (B0) supports both 25 MHz and 50 MHz crystal reference clock inputs
by using the “CLKREF_SEL” strap pin to select the state. CLKREF_SEL is shared with
the LED5 pin.
IMP Interface
IMP_RXCLK
In, Pd
IMP port RGMII Interface Receive Clock 125 MHz for 1000 Mb/s operation, 25 MHz for
100 Mb/s operation and 2.5 MHz for 10 Mb/s operation.
IMP_RXD_0
I, Pd
IMP_RXD_1
I, Pd
IMP_RXD_2
I, Pd
IMP port RGMII Receive Data Inputs. For 1000 Mb/s operation, data bits RXD[3:0] are
clocked-out on the rising edge of RXCLK, and data bits RXD[7:4] are clocked on the
falling edge of RXCLK. In 10 Mb/s and 100 Mb/s modes, data bits RXD[3:0] are clocked
on the rising edge of RXCLK.
IMP_RXD_3
I, Pd
IMP_RXDV
I, Pd
IMP port Receive Data Valid. Active high. Indicates the data on the RXD[3:0] pins are
encoded and transmitted. Connects to the TXEN of the external MAC/Management entity.
IMP_TXCLK
O, Pd
IMP Port RGMII Transmit Clock. This clock is driven to synchronize the transmit data in
RGMII mode (125 MHz for 1000 Mb/s operation, 25 MHz for 100 Mb/s operation, and
2.5 MHz for 10 Mb/s operation). In RGMII mode, both edges of the clock are used to align
with TXD[3:0].
IMP_TXD_0
O, Pd
IMP_TXD_1
O, Pd
IMP_TXD_2
O, Pd
IMP Port RGMII Transmit Data Output. For 1000 Mb/s operation, data bits TXD[3:0] are
clocked on the rising edge of TXCLK, and data bits TXD[7:4] are clocked on the falling
edge of TXCLK. For 10 Mb/s and 100 Mb/s, data bits TXD[3:0] are clocked on the rising
edge of TXCLK. These output pins have internal 25Ω series termination resistor.
IMP_TXD_3
O, Pd
IMP_TXEN
O, Pd
IMP_VOL_REF
pwr, in
Reference point
WAN_RXCLK
I, Pd
RGMII Receive Clock 125 MHz for 1000 Mb/s operation, 25 MHz for 100 Mb/s operation
and 2.5 MHz for 10 Mb/s operation.
WAN_RXD0
I, Pd
WAN Receive Data Input.
WAN_RXD1
I, Pd
WAN_RXD2
I, Pd
WAN_RXD3
I, Pd
WAN_RXDV
I, Pd
RGMII/MII Receive Data Valid
LED15_WAN_TXCLK
O, Pd
When WANLEDSEL = 1b'0: LED15_WAN_TXCLK is used as WAN transmit clock.
When WANLEDSEL = 1b'1: LED15_WAN_TXCLK is used as LED15 and the polarity is
always active low.
WAN Port Interface
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Table 35: Signal Descriptions (Continued)
Signal Name
Type and
Default
State
LED10_WAN_TXD0
O, Pd
When WANLEDSEL = 1b'0: LED10_WAN_TXD0 is used as WAN transmit data output 0.
When WANLEDSEL = 1b'1: LED10_WAN_TXD0 is used as LED10 and the polarity is
always active low.
LED11_WAN_TXD1
O, Pd
When WANLEDSEL = 1b'0: LED11_WAN_TXD1 is used as WAN transmit data output 1.
When WANLEDSEL = 1b'1: LED11_WAN_TXD1 is used as LED11 and the polarity is
always active low.
LED12_WAN_TXD2
O, Pd
When WANLEDSEL = 1b'0: LED12_WAN_TXD2 is used as WAN transmit data output 2.
When WANLEDSEL = 1b'1: LED12_WAN_TXD2 is used as LED12 and the polarity is
always active low.
LED13_WAN_TXD3
O, Pd
When WANLEDSEL = 1b'0: LED13_WAN_TXD3 is used as RGMII transmit data output
3.
When WANLEDSEL = 1b'1: LED13_WAN_TXD3 is used as LED13 and the polarity is
always active low.
LED14_WAN_TXEN
O, Pd
When WANLEDSEL = 1b'0: LED14_WAN_TXEN is used as RGMII transmit enable.
When WANLEDSEL = 1b'1: LED14_WAN_TXEN is used as LED14 and the polarity is
always active low.
WAN_VOL_REF
I
–
WANVOLSEL
I
Use to set the WAN interface operating voltage level. 0 = 3.3V/2.5V, 1 = 1.8V/1.5V.
Description
Interrupt
INT_L_LEDMODE1
O, Pu, SOR Interrupt. This interrupt pin generates an interrupt based on the configuration in the
Interrupt Enable register. It can be programmed to generate based on link status change
of any port, or to generate an interrupt to a CPU entity when there is a packet(s) queued
in the IMP transmit queue. This signal is active low. INT_L is a strap pin for LEDMODE1.
MDC/MDIO Interface
MDC
Bi, Pd
Management Data I/O. In Master mode, this serial input/output data signal is used to read
from and write to the MII registers of the external transceivers. In slave mode, it is used
by an external entity to read/write to the switch registers using the Pseudo-PHY. See the
MDC/MDIO interface for more information.
MDIO
Bi, Pd
Management Data Clock. In master mode, this 2.5 MHz clock sourced by BCM53134M
to the external PHY device. In Slave mode, it is sources by an external entity.
SCK/SK
I,O, Pd
SPI Serial Clock. The clock input to the BCM53134M SPI interface is supplied by the SPI
master, which supports up to 25 MHz, and is enabled if CPU_EEPROM_SEL is high
during power-on reset.
EEPROM Serial Clock. The clock output to an external EEPROM device and is enabled
if CPU_EEPROM_SEL is low during power-on reset.
SS/CS
I,O, Pu
SPI Slave Select. Active-low signal that enables an SPI interface read or write operation.
Enable if CPU_EEPROM_SEL is high during power-on reset.
EEPROM Chip Select. Active-high control signal that enables a read operation from an
external EEPROM device. Enable if CPU_EEPROM_SEL is low during power-on reset.
SPI/EEPROM Interface
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Table 35: Signal Descriptions (Continued)
Signal Name
Type and
Default
State
Description
MISO/DO_ENEEE
O, Pu, SOR SPI Master-In/Slave-Out. Output signal which transmits serial data during an SPI
interface read operations. Enabled if CPU_EEPROM_SEL is high during Power- On
Reset.
EEPROM Data Out. Serial data output to an external EEPROM device. Enable if
CPU_EEPROM_SEL is low during power-on reset. MISO is used for the strap pin for
EN_EEE (Energy Efficent Ethernet). Enable EEE feature for switch MAC: 0 = disable 1 =
enable (default)
MOSI/DI
I,O, Pu
SPI Master-Out/Slave-In. Input signal which receives control and address information for
the SPI interface, as well as serial data during write operations. Enabled if
CPU_EEPROM_SEL is high during power-on reset.
EEPROM Data In. Serial data input to an external EEPROM device. Enabled if
CPU_EEPROM_SEL is low during power-on reset.
NOTE: This signal is tristated during RESET.
RS232_RXD
I, Pu
RS-232 Input
RS232_TXD_WANLEDSEL
O, Pd, SOR RS-232 Output. This pin is used for the strap pin for WAN port LED Select 0 = WAN
interface, 1 = LED interface. When set to 0, WAN interface is used for WAN interface.
When set to 1, WAN interface is used for LED[15:8].
RS-232 Interface
Flash Memory Interface
FCK
O, Pd
Flash Memory Serial Clock. The clock output for serial Flash memory.
FCS_L_ENLOOPDET
O, Pd, SOR Flash Memory Chip Select. Active low signal. Chip select to serial Flash memory device.
FCS_L is used for the strap pin for ENLOOPDET to enable the Loop Detect feature. 1 =
enable.
FSI
I, Pd
Serial Data Input. Serial data input from serial Flash memory.
FSO
O, Pd
Serial Data Output. Serial data output to drive serial Flash memory.
TMS
I
JTAG Mode Select Input.
TRST_L
I
JTAG Test Reset. Active low. Resets the JTAG controller. This signal must be pulled low
during normal operation.
TCK
I
JTAG Test Clock Input. Clock Input used to synchronize JTAG control and data
transfers. If unused, may be left unconnected.
TDI
I
JTAG Test Data Input. Serial data input to the JTAG TAP Controller. Sampled on the
rising edge of TCK. If unused, may be left unconnected.
TDO_EN8051
O, Pu
JTAG Test Data Output. TDO is used for the strap pin for EN_8051. Enable the
embedded BCM8051 microcontroller. The embedded BCM8051 microcontroller is
enabled by default. 0 = disabled 1= enabled (default)
JTCE
I, Pd
JTAG Capability Select.
O, Pd
LED0.
NOTE:
This LED0 also shares strap pin Xtal_Bypass. The default is internal pull down to select
the crystal clock input.
Xtal_Bypass = 0, selects Crystal mode for crystal input.
Xtal_Bypass = 1, selects single-ended CMOS clock input.
JTAG Interface
LED Interface
LED0
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Table 35: Signal Descriptions (Continued)
Signal Name
Type and
Default
State
Description
LED1
O, Pu
LED1.
LED2_IMPVOLSEL
O, Pd, SOR LED2 is used for the strap pin for IMPVOLSEL, use to set the IMP interface operating
voltage level. 0 = 3.3V/2.5V, 1 = 1.8V/1.5V.
LED3_CLKFREQ1
O, Pu, SOR LED3 is used for the strap pin for CLK Frequency 1 bit.
LED4_WANMODE
O, Pd, SOR LED4 is used for the strap pin for WAN MODE. 0 = RGMII, 1 = reserved. To use the WAN
port as RGMII, this pin must be low.
LED5
O, Pd
LED6_IMPMODE
O, Pd, SOR LED6 is used for the strap pin for IMP MODE. 0 = RGMII, 1 = reserved. To use the IMP
port as RGMII, this pin must be low.
–
LED7
O, Pd
LED8_CPUEEPROMSEL
O, Pu, SOR LED8 is used for the strap pin for CPU_EEPROM_SEL. CPU or EEPROM interface
selection. CPU_EEPROM_SEL = 0: Enable EEPROM interface CPU_EEPROM_SEL =
1: Enable SPI Interface (default) The SPI interface must be selected
(CPU_EEPROM_SEL=1) for Pseudo-PHY accesses through the MDC/MDIO Interface.
LED9_HWFWDGEN
O, Pu, SOR LED9 is used for the strap pin for HW_FWDG_EN. Forwarding enable. When this pin is
pulled high (default) at power-up, traffic is forwarded without any register settings, based
on default register settings. When this pin is pulled low at power-up, frame forwarding is
disabled. Traffic forwarding is enabled through Software Register bit set.
LEDCLK_LEDMODE0
O, Pd, SOR LEDCLK is the LED Shift Clock. This clock is periodically active to enable LEDDATA to
shift into external registers. LEDCLK are used for the strap pin for LED MODE[1:0]. Users
can select predefined functions to be displayed for each port by setting the bits
accordingly.
LEDDATA_CLKFREQ0
O, Pd, SOR LEDDATA is Serial LED Data Output. Serial LED data for all ports is shifted out when
LEDCLK is active. LEDDATA signal is used for the strap pin for Clock Frequency set bit
0. CLKFREQ[1:0] 00 = 125 MHz, 01 = 142 MHz, 10 = 200 MHz, 11 = 167 MHz.
LED5.
NOTE: For BCM53134 (A0), this pin is LED5 only and not a strap pin.
NOTE: For BCM53134 (B0), this is strap pin “CLKREF_SEL” and it is shared with LED5
to select the 50 MHz or 25 MHz clock input:
– CLKREF_SEL = 1, selects 50 MHz crystal reference clock input.
– CLKREF_SEL = 0, selects 25 MHz crystal reference clock input.
NOTE: For SGMII applications, the reference clock must only be 50 MHz.
LED7.
Power Interface
XTAL_AVDD
pwr, in
1.0V for XTAL
AVDDL
pwr, in
1.0V PHY core
AVDDHa
pwr, in
3.3V/2.5V for analog I/O
DVDD
pwr, in
1.0V for core
VDDO
pwr, in
3.3V for digital I/O
VDD_1_8
pwr, in
1.8V input for intermediate state for internal use. (The output is from LDO_VOUT.)
PHY_BVDDa
pwr, in
3.3V/2.5V
VDD_PLL
pwr, in
1.0V for PLL
VDD_SGMII
pwr, in
1.0V for SGMII
OVDD_IMP
pwr, in
Power for IMP port I/O, 3.3V, 2.5V, 1.8V, or 1.5V
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Table 35: Signal Descriptions (Continued)
Signal Name
Type and
Default
State
Description
OVDD_WAN
pwr, in
Power for WAN port I/O, 3.3V, 2.5V, 1.8V, or 1.5V
AVSS
–
GND
VSS
–
GND
PHYPLL_GND
–
GND
IMP_VDDP
pwr, in
1.8/1.5V power for IMP port core
WAN_VDDP
pwr, in
1.8/1.5V power for WAN port core
PHY_VDD_PLL
pwr, in
1.0V for PHY PLL
LDO_AVDD
pwr, in
3.3V for LDO power input
LDO_VOUT
pwr, out
1.8V output from LDO
LDO_VSENSE
pwr, in
1.8V LDO sense input
DNP
–
No physical ball (no solder mask)
NC
–
No connect
PHY_RDAC
–
6.04 K resistor to GND is required.
ACT_LOOP_DETECT
I, Pd
Active loop detect function.
LDO Interface
Miscellaneous
a. The BCM53134M supports 3.3V or 2.5V GPHY power rail.
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Chapter 6: Pin Assignment
6.1 Pin List by Pin Number
Table 36: Pin List by Pin Number
Ball
Ball Name
Type
A01
TDN0_0
Bi-Dir
A02
TDN0_1
Bi-Dir
A03
TDN0_2
Bi-Dir
A04
TDN0_3
Bi-Dir
A05
TDP1_3
Bi-Dir
A06
TDP1_2
Bi-Dir
A07
TDP1_1
Bi-Dir
A08
TDP1_0
Bi-Dir
A09
TDP2_0
Bi-Dir
A10
TDP2_1
Bi-Dir
A11
TDP2_2
Bi-Dir
A12
TDP2_3
Bi-Dir
A13
TDN3_3
Bi-Dir
A14
TDN3_2
Bi-Dir
A15
TDN3_1
Bi-Dir
A16
TDN3_0
Bi-Dir
B01
TDP0_0
Bi-Dir
B02
TDP0_1
Bi-Dir
B03
TDP0_2
Bi-Dir
B04
TDP0_3
Bi-Dir
B05
TDN1_3
Bi-Dir
B06
TDN1_2
Bi-Dir
B07
TDN1_1
Bi-Dir
B08
TDN1_0
Bi-Dir
B09
TDN2_0
Bi-Dir
B10
TDN2_1
Bi-Dir
B11
TDN2_2
Bi-Dir
B12
TDN2_3
Bi-Dir
B13
TDP3_3
Bi-Dir
B14
TDP3_2
Bi-Dir
B15
TDP3_1
Bi-Dir
B16
TDP3_0
Bi-Dir
C01
PHY_RDAC
Input
C02
NC
No connect
C03
PHY_VDD_PLL
Power
C04
VSS
GND
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Table 36: Pin List by Pin Number (Continued)
Ball
Ball Name
Type
C05
AVDDH
Power
C06
AVDDL
Power
C07
AVDDH
Power
C08
AVDDL
Power
C09
AVDDH
Power
C10
VSS
GND
C11
AVDDL
Power
C12
AVDDL
Power
C13
PHY_BVDD
Power
C14
AVDDH
Power
C15
VSS
GND
C16
VSS
GND
D01
VSS
GND
D02
VSS
GND
D03
VSS
GND
D04
VSS
GND
D05
DNP
No PHYSICAL BALL (no solder mask)
D06
DNP
No PHYSICAL BALL (no solder mask)
D07
DNP
No PHYSICAL BALL (no solder mask)
D08
DNP
No PHYSICAL BALL (no solder mask)
D09
DNP
No PHYSICAL BALL (no solder mask)
D10
DNP
No PHYSICAL BALL (no solder mask)
D11
DNP
No PHYSICAL BALL (no solder mask)
D12
DNP
No PHYSICAL BALL (no solder mask)
D13
VSS
GND
D14
VSS
GND
D15
MDC
–
D16
MDIO
–
E01
DNP
No PHYSICAL BALL (no solder mask)
E02
LED10_WAN_TXD0
–
E03
LED11_WAN_TXD1
–
E04
DNP
No PHYSICAL BALL (no solder mask)
E05
DNP
No PHYSICAL BALL (no solder mask)
E06
VSS
GND
E07
VSS
GND
E08
VSS
GND
E09
VSS
GND
E10
VSS
GND
E11
VSS
GND
E12
DNP
No PHYSICAL BALL (no solder mask)
E13
DNP
No PHYSICAL BALL (no solder mask)
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Table 36: Pin List by Pin Number (Continued)
Ball
Ball Name
Type
E14
LED_0
–
E15
LED_1
–
E16
LED_2_IMPVOLSEL
–
F01
LED12_WAN_TXD2
–
F02
LED13_WAN_TXD3
–
F03
LED14_WAN_TXEN
–
F04
DNP
No PHYSICAL BALL (no solder mask)
F05
VSS
GND
F06
VSS
GND
F07
VSS
GND
F08
VSS
GND
F09
VSS
GND
F10
VSS
GND
F11
VSS
GND
F12
VSS
GND
F13
DNP
No PHYSICAL BALL (no solder mask)
F14
LED_3_CLKFREQ1
–
F15
LED_4_WANMODE
–
F16
DNP
No PHYSICAL BALL (no solder mask)
G01
LED15_WAN_TXCLK
–
G02
WAN_VOL_REF
–
G03
VSS
GND
G04
DNP
No PHYSICAL BALL (no solder mask)
G05
VSS
GND
G06
VSS
GND
G07
VSS
GND
G08
VSS
GND
G09
VSS
GND
G10
VSS
GND
G11
VSS
GND
G12
VSS
GND
G13
DNP
No PHYSICAL BALL (no solder mask)
G14
LED_5
–
G15
LED_6_IMPMODE
–
G16
LED_7
–
H01
WAN_RXCLK
–
H02
WAN_RXD_0
–
H03
OVDD_WAN
–
H04
DNP
No PHYSICAL BALL (no solder mask)
H05
VSS
GND
H06
VSS
GND
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Table 36: Pin List by Pin Number (Continued)
Ball
Ball Name
Type
H07
VSS
GND
H08
VSS
GND
H09
VSS
GND
H10
VSS
GND
H11
VSS
GND
H12
VSS
GND
H13
DNP
No PHYSICAL BALL (no solder mask)
H14
LED_DATA_CLKFREQ0
–
H15
LED_8_CPUEEPROMSEL
–
H16
LED_9_HWFWDGEN
–
J01
WAN_RXD1
–
J02
WAN_RXDV
–
J03
OVDD_WAN
Power
J04
DNP
No PHYSICAL BALL (no solder mask)
J05
VSS
GND
J06
VSS
GND
J07
VSS
GND
J08
VSS
GND
J09
VSS
GND
J10
VSS
GND
J11
VSS
GND
J12
VDDO
Power
J13
DNP
No PHYSICAL BALL (no solder mask)
J14
FSI
–
J15
LED_CLK_LEDMODE0
–
J16
DNP
No PHYSICAL BALL (no solder mask)
K01
WAN_RXD2
–
K02
WAN_RXD3
–
K03
WAN_VDDP
–
K04
DNP
No PHYSICAL BALL (no solder mask)
K05
VSS
GND
K06
DVDD
Power
K07
VSS
GND
K08
DVDD
Power
K09
VSS
GND
K10
DVDD
Power
K11
VSS
GND
K12
VDDO
Power
K13
DNP
No PHYSICAL BALL (no solder mask)
K14
FSO
–
K15
FCSL_ENLOOPDET
–
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BCM53134M Data Sheet
Multiport Ultra Low-Power Gigabit Ethernet Switch
Table 36: Pin List by Pin Number (Continued)
Ball
Ball Name
Type
K16
FCK
–
L01
NC
–
L02
VSS
GND
L03
VSS
GND
L04
DNP
No PHYSICAL BALL (no solder mask)
L05
VSS
GND
L06
DVDD
Power
L07
VSS
GND
L08
DVDD
Power
L09
VSS
GND
L10
DVDD
Power
L11
VSS
GND
L12
VDD_1P8
Power
L13
DNP
No PHYSICAL BALL (no solder mask)
L14
VDDO
Power
L15
NC
No connect
L16
ACT_LOOP_DETECT
–
M01
NC
No connect
M02
NC
No connect
M03
VDD_SGMII
Power
M04
DNP
No PHYSICAL BALL (no solder mask)
M05
DNP
No PHYSICAL BALL (no solder mask)
M06
DVDD
Power
M07
VSS
GND
M08
DVDD
Power
M09
VSS
GND
M10
DVDD
Power
M11
VSS
GND
M12
DNP
No PHYSICAL BALL (no solder mask)
M13
DNP
No PHYSICAL BALL (no solder mask)
M14
WANVOLSEL
Input
M15
NC
No connect
M16
DNP
No PHYSICAL BALL (no solder mask)
N01
DNP
No PHYSICAL BALL (no solder mask)
N02
NC
–
N03
VDD_SGMII
Power
N04
LDO_VOUT
Power
N05
DNP
No PHYSICAL BALL (no solder mask)
N06
DNP
No PHYSICAL BALL (no solder mask)
N07
DNP
No PHYSICAL BALL (no solder mask)
N08
DNP
No PHYSICAL BALL (no solder mask)
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BCM53134M Data Sheet
Multiport Ultra Low-Power Gigabit Ethernet Switch
Table 36: Pin List by Pin Number (Continued)
Ball
Ball Name
Type
N09
DNP
No PHYSICAL BALL (no solder mask)
N10
DNP
No PHYSICAL BALL (no solder mask)
N11
DNP
No PHYSICAL BALL (no solder mask)
N12
DNP
No PHYSICAL BALL (no solder mask)
N13
VDD_1P8
Power
N14
JTCE
Input
N15
TDO_EN8051
Output
N16
TCK
Input
P01
NC
–
P02
NC
–
P03
LDO_VSENSE
Power
P04
LDO_AVDD
Power
P05
NC
No connect
P06
VDD_PLL
Power
P07
VSS
GND
P08
OVDD_IMP
Power
P09
OVDD_IMP
Power
P10
IMP_VDDP
Power
P11
VSS
GND
P12
SS
Input
P13
SCK
Input
P14
NC
No connect
P15
TRST_L
Input
P16
TDI
Input
R01
NC
No connect
R02
NC
No connect
R03
VSS
GND
R04
XTAL_VDD
Power
R05
IMP_TXEN
–
R06
IMP_TXD1
–
R07
IMP_TXD2
–
R08
IMP_VOL_REF
Power/GND
R09
IMP_RXD3
–
R10
IMP_RXD1
–
R11
IMP_RXDV
–
R12
MOSI_DI
–
R13
INTR_L_LEDMODE1
–
R14
RESET_L
–
R15
TMS
Input
R16
DNP
No PHYSICAL BALL (no solder mask)
T01
VSS
GND
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BCM53134M Data Sheet
Multiport Ultra Low-Power Gigabit Ethernet Switch
Table 36: Pin List by Pin Number (Continued)
Ball
Ball Name
Type
T02
VSS
GND
T03
XTAL_N
–
T04
XTAL_P
–
T05
DNP
No PHYSICAL BALL (no solder mask)
T06
IMP_TXD0
–
T07
IMP_TXD3
–
T08
IMP_TXCLK
–
T09
IMP_RXD0
–
T10
IMP_RXD2
–
T11
IMP_RXCLK
–
T12
MISO_DO_ENEEE
–
T13
DNP
No PHYSICAL BALL (no solder mask)
T14
RS232_TXD_WANLEDSEL
–
T15
RS232_RXD
–
T16
VSS
GND
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BCM53134M Data Sheet
Multiport Ultra Low-Power Gigabit Ethernet Switch
6.2 Pin List by Pin Name
Table 37: Pin List by Pin Name
Ball
Ball Name
Type
C05
AVDDH
Power
C07
AVDDH
Power
C09
AVDDH
Power
C14
AVDDH
Power
C06
AVDDL
Power
C08
AVDDL
Power
C11
AVDDL
Power
C12
AVDDL
Power
D05
DNP
No PHYSICAL BALL (no solder mask)
D06
DNP
No PHYSICAL BALL (no solder mask)
D07
DNP
No PHYSICAL BALL (no solder mask)
D08
DNP
No PHYSICAL BALL (no solder mask)
D09
DNP
No PHYSICAL BALL (no solder mask)
D10
DNP
No PHYSICAL BALL (no solder mask)
D11
DNP
No PHYSICAL BALL (no solder mask)
D12
DNP
No PHYSICAL BALL (no solder mask)
E01
DNP
No PHYSICAL BALL (no solder mask)
E04
DNP
No PHYSICAL BALL (no solder mask)
E05
DNP
No PHYSICAL BALL (no solder mask)
E12
DNP
No PHYSICAL BALL (no solder mask)
E13
DNP
No PHYSICAL BALL (no solder mask)
F04
DNP
No PHYSICAL BALL (no solder mask)
F13
DNP
No PHYSICAL BALL (no solder mask)
F16
DNP
No PHYSICAL BALL (no solder mask)
G04
DNP
No PHYSICAL BALL (no solder mask)
G13
DNP
No PHYSICAL BALL (no solder mask)
H04
DNP
No PHYSICAL BALL (no solder mask)
H13
DNP
No PHYSICAL BALL (no solder mask)
J04
DNP
No PHYSICAL BALL (no solder mask)
J13
DNP
No PHYSICAL BALL (no solder mask)
J16
DNP
No PHYSICAL BALL (no solder mask)
K04
DNP
No PHYSICAL BALL (no solder mask)
K13
DNP
No PHYSICAL BALL (no solder mask)
L04
DNP
No PHYSICAL BALL (no solder mask)
L13
DNP
No PHYSICAL BALL (no solder mask)
M04
DNP
No PHYSICAL BALL (no solder mask)
M05
DNP
No PHYSICAL BALL (no solder mask)
M12
DNP
No PHYSICAL BALL (no solder mask)
M13
DNP
No PHYSICAL BALL (no solder mask)
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BCM53134M Data Sheet
Multiport Ultra Low-Power Gigabit Ethernet Switch
Table 37: Pin List by Pin Name (Continued)
Ball
Ball Name
Type
M16
DNP
No PHYSICAL BALL (no solder mask)
N01
DNP
No PHYSICAL BALL (no solder mask)
N05
DNP
No PHYSICAL BALL (no solder mask)
N06
DNP
No PHYSICAL BALL (no solder mask)
N07
DNP
No PHYSICAL BALL (no solder mask)
N08
DNP
No PHYSICAL BALL (no solder mask)
N09
DNP
No PHYSICAL BALL (no solder mask)
N10
DNP
No PHYSICAL BALL (no solder mask)
N11
DNP
No PHYSICAL BALL (no solder mask)
N12
DNP
No PHYSICAL BALL (no solder mask)
R16
DNP
No PHYSICAL BALL (no solder mask)
T05
DNP
No PHYSICAL BALL (no solder mask)
T13
DNP
No PHYSICAL BALL (no solder mask)
K06
DVDD
Power
K08
DVDD
Power
K10
DVDD
Power
L06
DVDD
Power
L08
DVDD
Power
L10
DVDD
Power
M06
DVDD
Power
M08
DVDD
Power
M10
DVDD
Power
K16
FCK
–
K15
FCSL_ENLOOPDET
–
J14
FSI
–
K14
FSO
–
T11
IMP_RXCLK
–
T09
IMP_RXD0
–
R10
IMP_RXD1
–
T10
IMP_RXD2
–
R09
IMP_RXD3
–
R11
IMP_RXDV
–
T08
IMP_TXCLK
–
T06
IMP_TXD0
–
R06
IMP_TXD1
–
R07
IMP_TXD2
–
T07
IMP_TXD3
–
R05
IMP_TXEN
–
P10
IMP_VDDP
Power
R08
IMP_VOL_REF
Power/GND
R13
INTR_L_LEDMODE1
–
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BCM53134M Data Sheet
Multiport Ultra Low-Power Gigabit Ethernet Switch
Table 37: Pin List by Pin Name (Continued)
Ball
Ball Name
Type
N14
JTCE
Input
P04
LDO_AVDD
Power
N04
LDO_VOUT
Power
P03
LDO_VSENSE
Power
E14
LED_0
–
E15
LED_1
–
E16
LED_2_IMPVOLSEL
–
F14
LED_3_CLKFREQ1
–
F15
LED_4_WANMODE
–
G14
LED_5
–
G15
LED_6_IMPMODE
–
G16
LED_7
–
H15
LED_8_CPUEEPROMSEL
–
H16
LED_9_HWFWDGEN
–
J15
LED_CLK_LEDMODE0
–
H14
LED_DATA_CLKFREQ0
–
E02
LED10_WAN_TXD0
–
E03
LED11_WAN_TXD1
–
F01
LED12_WAN_TXD2
–
F02
LED13_WAN_TXD3
–
F03
LED14_WAN_TXEN
–
G01
LED15_WAN_TXCLK
–
D15
MDC
–
D16
MDIO
–
T12
MISO_DO_ENEEE
–
R12
MOSI_DI
–
L01
NC
–
M01
NC
–
M02
NC
–
N02
NC
–
P01
NC
–
P02
NC
–
P05
NC
No connect
P14
NC
No connect
R01
NC
No connect
R02
NC
No connect
C02
NC
No connect
L15
NC
No connect
L16
ACT_LOOP_DETECT
–
M15
NC
No connect
P08
OVDD_IMP
Power
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BCM53134M Data Sheet
Multiport Ultra Low-Power Gigabit Ethernet Switch
Table 37: Pin List by Pin Name (Continued)
Ball
Ball Name
Type
P09
OVDD_IMP
Power
H03
OVDD_WAN
–
J03
OVDD_WAN
Power
C13
PHY_BVDD
Power
C01
PHY_RDAC
Input
C03
PHY_VDD_PLL
Power
R14
RESET_L
–
T15
RS232_RXD
–
T14
RS232_TXD_WANLEDSEL –
P13
SCK
Input
P12
SS
Input
N16
TCK
Input
P16
TDI
Input
A01
TDN0_0
Bi-Dir
A02
TDN0_1
Bi-Dir
A03
TDN0_2
Bi-Dir
A04
TDN0_3
Bi-Dir
B08
TDN1_0
Bi-Dir
B07
TDN1_1
Bi-Dir
B06
TDN1_2
Bi-Dir
B05
TDN1_3
Bi-Dir
B09
TDN2_0
Bi-Dir
B10
TDN2_1
Bi-Dir
B11
TDN2_2
Bi-Dir
B12
TDN2_3
Bi-Dir
A16
TDN3_0
Bi-Dir
A15
TDN3_1
Bi-Dir
A14
TDN3_2
Bi-Dir
A13
TDN3_3
Bi-Dir
N15
TDO_EN8051
Output
B01
TDP0_0
Bi-Dir
B02
TDP0_1
Bi-Dir
B03
TDP0_2
Bi-Dir
B04
TDP0_3
Bi-Dir
A08
TDP1_0
Bi-Dir
A07
TDP1_1
Bi-Dir
A06
TDP1_2
Bi-Dir
A05
TDP1_3
Bi-Dir
A09
TDP2_0
Bi-Dir
A10
TDP2_1
Bi-Dir
A11
TDP2_2
Bi-Dir
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Multiport Ultra Low-Power Gigabit Ethernet Switch
Table 37: Pin List by Pin Name (Continued)
Ball
Ball Name
Type
A12
TDP2_3
Bi-Dir
B16
TDP3_0
Bi-Dir
B15
TDP3_1
Bi-Dir
B14
TDP3_2
Bi-Dir
B13
TDP3_3
Bi-Dir
R15
TMS
Input
P15
TRST_L
Input
L12
VDD_1P8
Power
N13
VDD_1P8
Power
P06
VDD_PLL
Power
M03
VDD_SGMII
Power
N03
VDD_SGMII
Power
J12
VDDO
Power
K12
VDDO
Power
L14
VDDO
Power
C04
VSS
GND
C10
VSS
GND
C15
VSS
GND
C16
VSS
GND
D01
VSS
GND
D02
VSS
GND
D03
VSS
GND
D04
VSS
GND
D13
VSS
GND
D14
VSS
GND
E06
VSS
GND
E07
VSS
GND
E08
VSS
GND
E09
VSS
GND
E10
VSS
GND
E11
VSS
GND
F05
VSS
GND
F06
VSS
GND
F07
VSS
GND
F08
VSS
GND
F09
VSS
GND
F10
VSS
GND
F11
VSS
GND
F12
VSS
GND
G03
VSS
GND
G05
VSS
GND
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BCM53134M Data Sheet
Multiport Ultra Low-Power Gigabit Ethernet Switch
Table 37: Pin List by Pin Name (Continued)
Ball
Ball Name
Type
G06
VSS
GND
G07
VSS
GND
G08
VSS
GND
G09
VSS
GND
G10
VSS
GND
G11
VSS
GND
G12
VSS
GND
H05
VSS
GND
H06
VSS
GND
H07
VSS
GND
H08
VSS
GND
H09
VSS
GND
H10
VSS
GND
H11
VSS
GND
H12
VSS
GND
J05
VSS
GND
J06
VSS
GND
J07
VSS
GND
J08
VSS
GND
J09
VSS
GND
J10
VSS
GND
J11
VSS
GND
K05
VSS
GND
K07
VSS
GND
K09
VSS
GND
K11
VSS
GND
L02
VSS
GND
L03
VSS
GND
L05
VSS
GND
L07
VSS
GND
L09
VSS
GND
L11
VSS
GND
M07
VSS
GND
M09
VSS
GND
M11
VSS
GND
P07
VSS
GND
P11
VSS
GND
R03
VSS
GND
T01
VSS
GND
T02
VSS
GND
T16
VSS
GND
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BCM53134M Data Sheet
Multiport Ultra Low-Power Gigabit Ethernet Switch
Table 37: Pin List by Pin Name (Continued)
Ball
Ball Name
Type
H01
WAN_RXCLK
–
H02
WAN_RXD_0
–
J01
WAN_RXD1
–
K01
WAN_RXD2
–
K02
WAN_RXD3
–
J02
WAN_RXDV
–
K03
WAN_VDDP
–
G02
WAN_VOL_REF
–
M14
WANVOLSEL
Input
T03
XTAL_N
–
T04
XTAL_P
–
R04
XTAL_VDD
Power
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BCM53134M Data Sheet
Multiport Ultra Low-Power Gigabit Ethernet Switch
Chapter 7: Electrical Characteristics
7.1 Absolute Maximum Ratings
Table 38: Absolute Maximum Ratings
Symbol
Parameter and Pins
Minimum
Maximum
Unit
AVDDL, DVDD, EGPHY_PLLVDD, QGPHY1_PLLVDD,
QGPHY2_PLLVDD
Supply voltage
GND – 0.3
1.1
V
OVDD, OTP_VDD, EPHY_BVDD, QGPHY1_BVDD,
QGPHY2_BVDD, SWREG_VDDO, XTAL_AVDD
Supply voltage
GND – 0.3
3.63
V
II
Input current
–
–
mA
TSTG
Storage temperature
–40
125
°C
VESD
Electrostatic discharge
–
1800V
V
–
Input voltage: Digital input pins –
–
V
NOTE: These specifications indicate levels where permanent damage to the device may occur. Functional operation is not guaranteed
under these conditions. Operation at absolute maximum conditions for extended periods may adversely affect long-term reliability of the
device.
7.2 Recommended Operating Conditions
Table 39: Recommended Operating Conditions
Symbol
Parameter
Pins
Minimum
Maximum
Unit
VDD
Supply voltage
–
0.95
1.1
V
–
3.14
3.47
V
–
–
–
V
–
–
–
V
VIH
High-level input voltage
All digital inputs
1.7
–
V
VIL
Low-level input voltage for 2.5V
All digital inputs
–
0.7
V
VIL
Low-level input voltage for 3.3V
All digital inputs
–
0.9
V
–TA
Ambient operating temperature
–
0
70
°C
NOTE:
The recommended minimum/maximum operating voltages are not final. The final numbers will be updated after
the characterization.
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BCM53134M Data Sheet
Multiport Ultra Low-Power Gigabit Ethernet Switch
7.3 Electrical Characteristics
Table 40: Electrical Characteristics
Symbol
Parameter
IDD
Supply current (for 1.0V power rail (analog)
2x RGMII
1.0V power rail (digital)
operation)
3.3V power rail
VOH
VOL
High-level output
voltage
Low-level output
voltage
Pins
Conditions
Min.
Typical
Max.
Unit
Measured
–
122.2
–
mA
Measured
–
247.5
–
mA
Measured
–
197.65
–
mA
OVDD_IMP and OVDD_WAN (2.5V
for RGMII)
Measured
–
49.7
–
mA
Digital output pins at 3.3V
Ioh = –8 mA
2.4
–
–
V
Digital output pins at 2.5V
IOH = –8 mA
2.0
–
–
V
Digital output pins at 1.5V/1.8V
IOH = –8 mA
1.0
–
–
V
Digital output pins at 3.3V
IOL = 8 mA
–
–
0.4
V
Digital output pins at 2.5V
IOL= 8 mA
–
–
0.4
V
Digital output pins at 1.5V/1.8V
IOL = 8 mA
–
–
0.4
V
–
1.7
–
–
V
VIH
High-level input
voltage
Digital input pins at 3.3V and 2.5V
Digital input pins at 1.5V/1.8V
–
0.9
–
–
V
VIL
Low-level input
voltage
Digital input pins for 3.3V
–
–
–
0.9
V
Digital input pins for 2.5V
–
–
–
0.7
V
Digital input pins at 1.5V/1.8V
–
–
–
0.5
V
II
Input current
Digital Inputs w/pull-up resistors
–
–
–
–
µA
Digital Inputs w/pull-up resistors
–
–
–
–
µA
Digital Inputs w/pull-down resistors
–
–
–
–
µA
Digital Inputs w/pull-down resistors
–
–
–
–
µA
All other digital inputs
–
–
–
–
µA
1. The measured result is based on 3.3V GPHY and 120m cable length. The 3m result will be 50 mW higher.
2. The measured result of 2.5V GPHY power rail will be 80 mW lower than 3.3V GPHY.
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BCM53134M Data Sheet
Multiport Ultra Low-Power Gigabit Ethernet Switch
Table 41: Internal Voltage Regulator Electrical Characteristics
Parameter
Min.
Typ.
Max.
Unit
1.8V LDO output range
1.44
1.8
1.98
V
1.8V LDO output ripple
–
15
30
mV
1.8V LDO output accuracy
–
–
4.5
%
1.8V LDO output current
–
–
100
mA
1.8V LDO output current limit
200
300
400
mA
1.8V LDO power-up time
–
120
160
μ
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BCM53134M Data Sheet
Multiport Ultra Low-Power Gigabit Ethernet Switch
Chapter 8: Timing Characteristics
8.1 Reset and Clock Timing
Figure 60: Reset and Clock Timing
Power
Rails
t104
t106
t103
t101
XTALI
t102
t107
t108
RESET
t105
t109
Configuration
Strap Signals
NOTE:
Valid
Advanced timing extracted from statistical data. It may or may not reflect the true timing of the device.
Table 42: Reset and Clock Timing
Description
Parameter
Minimum
Typical
Maximum
XTALI period
t101
19.999 ns
20 ns
20.001 ns
XTALI high time
t102
9 ns
–
11 ns
XTALI low time
t103
9 ns
–
11 ns
RESET low pulse duration
t104
80 ms
100 ms
–
RESET rise time
t105
–
–
25 ns
Configuration valid setup to RESET rising
t107
100 ns
–
–
Configuration valid hold from RESET rising
t108
–
–
100 ns
Hardware initialization is complete.
t109
All the strap pin values are clocked in, and the internal registers
can be accessed.
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5 ms before the registers can be accessed
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BCM53134M Data Sheet
Multiport Ultra Low-Power Gigabit Ethernet Switch
8.2 RGMII Interface Timing
The following specifies timing information regarding the IMP interface pins when configured in RGMII mode.
8.2.1 RGMII Output Timing (Normal Mode)
Figure 61: RGMII Output Timing (Normal Mode)
GTX_CLK
(at source)
TXD [3:0]
TX_CTL
t201
t201
NOTE:
Advanced timing extracted from statistical data. It may or may not reflect the true timing of the device.
Table 43: RGMII Output Timing (Normal Mode)
Description
Parameter
Minimum
Typical
Maximum
Unit
MII1_TXC clock period (1000M mode)
–
7.2
8
8.8
ns
MII1_TXC clock period (100M mode)
–
36
40
44
ns
MII1_TXC clock period (10M mode)
–
360
400
440
ns
TskewT: Data to clock output skew
t201
–500 (1000M)
0
+500 (1000M)
ps
TskewT: Data to Clock at 1.5V/1.8V mode
t201
–750 (1000M)
0
+500 (1000M)
ps
Duty cycle for 1000M (GbE)
–
45
50
55
%
Duty cycle for 10/100M (FE)
–
40
50
60
%
NOTE:
The output timing in 10/100M operation is always as specified in the delayed mode.
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Multiport Ultra Low-Power Gigabit Ethernet Switch
8.2.2 RGMII Output Timing (Delayed Mode)
Figure 62: RGMII Output Timing (Delayed Mode)
GTX_CLK
(internal)
Delayed
GTX_CLK
(actual output
at source)
t201D t202D
TXD [3:0]
TX_CTRL
t202D
t201D
NOTE:
Advanced timing extracted from statistical data. It may or may not reflect the true timing of the device.
Table 44: RGMII Output Timing (Delayed Mode)
Description
Parameter
Minimum
Typical
Maximum
Unit
MII1_TXC clock period (1000M mode)
–
7.2
8
8.8
ns
MII1_TXC clock period (100M mode)
–
36
40
44
ns
MII1_TXC clock period (10M mode)
–
360
400
440
ns
TsetupT
Data valid to clock transition:
Available setup time at the output source
(delayed mode)
t201D
1.2
(all speeds)
2.0
–
ns
TholdT
Clock transition to data valid:
Available hold time at the output source
(delayed mode)
t202D
1.2
(all speeds)
2.0
–
ns
TsetupT
Data valid to clock transition:
Available setup time at the output source
(1.5V/1.8V mode)
t201D
1.0
(all speeds)
2.0
–
ns
TholdT
Clock transition to data valid:
Available hold time at the output source
(1.5V/1.8V mode)
t202D
1.0
(all speeds)
2.0
–
ns
Duty cycle for 1000M (GbE)
–
45
50
55
%
Duty cycle for 10/100M (FE)
–
40
50
60
%
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Multiport Ultra Low-Power Gigabit Ethernet Switch
8.2.3 RGMII Input Timing (Normal Mode)
Figure 63: RGMII Input Timing (Normal Mode)
RXCLK
(internal)
RXCLK
(actual )
t301
t302
t301
t302
RXD[3:0]
RX_CTRL
NOTE:
Advanced timing extracted from statistical data. It may or may not reflect the true timing of the device.
Table 45: RGMII Input Timing (Normal Mode)
Description
Parameter
Minimum
Typical
Maximum
Unit
MII1_RXC clock period (1000M mode)
–
7.2
8
8.8
ns
MII1_RXC clock period (100M mode)
–
36
40
44
ns
MII1_RXC clock period (10M mode)
–
360
400
440
ns
TsetupR
Input setup time: Valid data to clock
t301
1.0
2.0
–
ns
TholdR
Input hold time: Clock to valid data
t302
1.0
2.0
–
ns
Duty cycle for 1000M (GbE)
–
45
50
55
%
Duty cycle for 10/100M (FE)
–
40
50
60
%
8.2.4 RGMII Input Timing (Delayed Mode)
Figure 64: RGMII Input Timing (Delayed Mode)
R XCLK
( internal)
Delayed RXCLK
( Actual output at
destination)
t301D
t302D
t3 01D
t302D
RXD [3:0]
RX_CTRL
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BCM53134M Data Sheet
NOTE:
Multiport Ultra Low-Power Gigabit Ethernet Switch
Advanced timing extracted from statistical data. It may or may not reflect the true timing of the device.
Table 46: RGMII Input Timing (Delayed Mode)
Description
Parameter
TsetupR
Input setup time (delayed mode)
t301D
TholdR
Input hold time (delayed mode)
t302D
Broadcom Confidential
Minimum
Typical
Maximum
Unit
–1.0 (1000M)
–
–
ns
–1.0 (10/100M)
–
–
ns
3.0 (1000M)
–
–
ns
9.0 (10/100M)
–
–
ns
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BCM53134M Data Sheet
Multiport Ultra Low-Power Gigabit Ethernet Switch
8.3 MDC/MDIO Timing
The following specifies timing information regarding the MDC/MDIO interface pins.
Figure 65: MDC/MDIO Timing (Slave Mode)
t401
t402
MDC
t402
t403
MDIO
(Input)
t404
MDIO
(Output)
t405
NOTE:
Advanced timing extracted from statistical data. It may or may not reflect the true timing of the device.
Table 47: MDC/MDIO Timing (Slave Mode)
Description
Parameter
Minimum
Typical
Maximum
Unit
MDC cycle time
t401
80
–
–
ns
MDC high/low
–
30
–
–
ns
MDC rise/fall time
t402
–
–
10
ns
MDIO input setup time to MDC rising
t403
7.5
–
–
ns
MDIO input hold time from MDC rising
t404
7.5
–
–
ns
MDIO output delay from MDC rising
t405
0
–
45
ns
Figure 66: MDC/MDIO Timing (Master Mode)
t401
t402
MDC
t402
MDIO
(Input to BCM53134)
t403
t404
MDIO
(Output from BCM53134)
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t405m
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BCM53134M Data Sheet
Multiport Ultra Low-Power Gigabit Ethernet Switch
Table 48: MDC/MDIO Timing (Master Mode)
Description
Parameter
Minimum
Typical
Maximum
Unit
MDC cycle time
t401
400
–
–
ns
MDC high/low
–
160
–
240
ns
MDC rise/fall time
t402
–
–
10
ns
MDIO input setup time to MDC rising
t403
20
–
–
ns
MDIO input hold time from MDC rising
t404
0
–
–
ns
MDIO output delay from MDC falling
t405m
–5
–
20
ns
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8.4 Serial LED Interface Timing
The following specifies timing information regarding the LED interface pins.
Figure 67: Serial LED Interface Timing
t301
t302
t304
t303
LEDCLK
LEDDATA
S0
S1
SN
S2
S0
t305
NOTE:
Advanced timing extracted from statistical data. It may or may not reflect the true timing of the device.
Table 49: Serial LED Interface Timing
Description
Parameter
Minimum
Typical
Maximum
Unit
LED update cycle period
t301
–
42
–
ms
LEDCLK period
t302
–
320
–
ns
LEDCLK high-pulse width
t303
150
–
170
ns
LEDCLK low-pulse width
t304
150
–
170
ns
LEDCLK to LEDDATA output time
t305
140
–
180
ns
8.5 SPI Timings
Figure 68: SPI Timings, SS Asserted During SCK High
t601
t603
t602
t604
SCK
t607= 10 ns
t608 = 20 ns
SS
MOSI
t605
t606
MISO
NOTE:
SS should be asserted only while SCK is high.
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BCM53134M Data Sheet
NOTE:
Multiport Ultra Low-Power Gigabit Ethernet Switch
Advanced timing extracted from statistical data. It may or may not reflect the true timing of the device.
Table 50: SPI Timings
Description
Parameter
Minimum
Typical
Maximum
SCK clock period
t601
40 ns
500 ns
–
SCK high/low time
t602
20 ns
250 ns
–
MOSI to SCK setup time
t603
5 ns
–
–
MOSI to SCK hold time
t604
5 ns
–
–
SCK to MISO valid
t605
–
–
10 ns
SCK to MISO valid
t605
–
–
10 ns
Time interval from assert of SS to start of SCK
t607
10 ns
–
–
Time interval from end of SCK to deassert of SS
t608
20 ns
–
–
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8.6 JTAG Interface
JTAG timing is synchronous to the JTAG_TCK clock.
Figure 69: JTAG Interface
TCYCLE
50% VDD
JTAG_CLK
TSU
TH
VALID
JTAG_TDI
TOD
VALID
JTAG_TDO
Table 51: JTAG Interface
Parameter
Description
Min.
Typ.
Max.
Unit
TCYCLE
JTAG Cycle Time
50
–
–
ns
TSU
Input Setup Time
12.5
–
–
ns
TH
Input Hold Time
12.5
–
–
ns
TOD
Output Delay Time Measured from Falling Edge of JTAG_TCK
–
–
22
ns
8.7 EEPROM Timing
Figure 70: EEPROM Timing
t701
t703
t702
t704
SCK
CS
DI
t705
t706
DO
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NOTE:
Multiport Ultra Low-Power Gigabit Ethernet Switch
Advanced timing extracted from statistical data. It may or may not reflect the true timing of the device.
Table 52: EEPROM Timing
Description
Parameter
Minimum
Typical
Maximum
SCK clock frequency
t701
–
100 kHz
–
SCK high/low time
t702
–
5 μs
–
SCK low to CS, DI valid
t703
–
–
500 ns
SCK low to CS, DI invalid
t704
500 ns
–
–
DO to SCK falling setup time
t705
200 ns
–
–
DO to SCK falling hold time
t706
200 ns
–
–
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BCM53134M Data Sheet
Multiport Ultra Low-Power Gigabit Ethernet Switch
Chapter 9: Thermal Characteristics
NOTE:
The maximum allowed junction temperature is 110°C.
9.1 Package Only
Table 53: Package Only, 2s2p PCB, TA = 70°C, P = 1.723W
Device power dissipation, P (W)
1.72
Ambient air temperature TA (°C)
70
θJA in still air (°C/W)
38.17
θJB (°C/W)
17.32
θJC (°C/W)
23.74
2s2p board, pkg only
Package Thermal Performance Curve
Air Velocity
m/s
ft/min
TJ
TT
θJA
ΨJT
ΨJB
(°C)
(°C)
(°C/W)
(°C/W)
(°C/W)
0
0
135.8
133.5
38.17
1.30
25.74
0.508
100
132.4
130.1
36.19
1.32
25.77
1.016
200
130.7
128.3
35.21
1.38
25.74
2.032
400
128.8
126.1
34.11
1.55
25.62
3.048
600
127.6
124.6
33.43
1.71
25.50
9.2 Package Only with Heat Sink (50 x 50 x 35 mm3)
Table 54: Package with External Heat Sink 50 x 50 x 35 mm3, 2s2p PCB, TA = 70°C, P = 1.723W
Device power dissipation, P (W)
1.72
Ambient air temperature TA (°C)
70
θJA in still air (°C/W)
23.75
θJB (°C/W)
17.32
θJC (°C/W)
23.74
3
2s2p board, 50 x 50 x 35 mm estHS
Package Thermal Performance Curve
Air Velocity
TJ
TT
θJA
ΨJT
ΨJB
m/s
ft/min
(°C)
(°C)
(°C/W)
(°C/W)
(°C/W)
0
0
110.9
82.0
23.75
16.78
17.47
0.508
100
105.9
76.4
20.82
17.10
17.19
1.016
200
104.8
75.3
20.20
17.15
17.15
2.032
400
104.2
74.7
19.87
17.15
17.14
3.048
600
104.2
74.5
19.73
17.14
17.14
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9.3 Package Only
Table 55: Package Only, 2s2p PCB, TA = 55°C, P = 1.723W
Device power dissipation, P (W)
1.72
Ambient air temperature TA (°C)
55
θJA in still air (°C/W)
38.65
θJB (°C/W)
17.32
θJC (°C/W)
23.74
2s2p board, pkg only
Package Thermal Performance Curve
Air Velocity
TJ
TT
θJA
ΨJT
ΨJB
m/s
ft/min
(°C)
(°C)
(°C/W)
(°C/W)
(°C/W)
0
0
121.6
119.4
38.65
1.29
25.74
0.508
100
117.8
115.5
36.43
1.31
25.77
1.016
200
116.0
113.6
35.38
1.36
25.75
2.032
400
114.0
111.3
34.23
1.54
25.63
3.048
600
112.8
109.8
33.52
1.70
25.51
9.4 Package Only with Heat Sink (19 x 19 x 5 mm3)
Table 56: Package with External Heat Sink 19.x 19 x 5 mm3, 2s2p PCB, TA = 55°C, P = 1.723W
Device power dissipation, P (W)
1.72
Ambient air temperature TA (°C)
55
θJA in still air (°C/W)
31.70
θJB (°C/W)
17.32
θJC (°C/W)
23.74
2s2p board, pkg only
Package Thermal Performance Curve
Air Velocity
TJ
TT
θJA
ΨJT
ΨJB
m/s
ft/min
(°C)
(°C)
(°C/W)
(°C/W)
(°C/W)
0
0
109.6
84.5
31.70
14.58
19.66
0.508
100
105.3
79.8
29.20
14.82
19.46
1.016
200
102.1
76.0
27.31
15.13
19.17
2.032
400
98.7
72.0
25.34
15.49
18.80
3.048
600
96.9
69.9
24.33
15.68
18.59
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BCM53134M Data Sheet
Multiport Ultra Low-Power Gigabit Ethernet Switch
Chapter 10: Mechanical Information
Figure 71: BCM53134M Mechanical Information
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BCM53134M Data Sheet
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Chapter 11: Ordering Information
Table 57: Ordering Information
Part Number
Package
Ambient Temperature
BCM53134MKFBG
212-pin FBGA package
0°C to 70°C
BCM53134MIFBG
212-pin FBGA package
–45°C to 85°C
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BCM53134M Data Sheet
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Revision History
53134M-DS105; November 15, 2018
Updated:
RGMII Interface
Table 35, Signal Descriptions
Table 40, Electrical Characteristics
Table 43, RGMII Output Timing (Normal Mode)
Table 44, RGMII Output Timing (Delayed Mode)
53134M-DS104; July 23, 2018
Updated:
Table 35, Signal Descriptions
Table 37, Pin List by Pin Number 53134S/53134M
Table 39, Pin List by Pin Name 53134S/53134M
53134M-DS103; March 15, 2018
Updated:
Table 42, Electrical Characteristics
53134M-DS102; August 24, 2016
Updated:
Figure 70: “MDC/MDIO Timing (Master Mode),” on page 188
Table 52: “MDC/MDIO Timing (Master Mode),” on page 188
Section 9: “Thermal Characteristics,” on page 195
Added:
“Egress VID Modification” on page 40
53134M-DS101; May 11, 2016
Updated:
Figure 2: “Functional Block Diagram,” on page 3
“Multimode TX Digital-to-Analog Converter” on page 89
Table 34: “Signal Descriptions,” on page 142
Table 36: “Pin List by Pin Number 53134S/53134M,” on page 155
Table 38: “Pin List by Pin Name 53134S/53134M,” on page 169
Table 60: “Package only, 2s2p PCB, TA = 70° C, P = 1.723W,” on page 194
Table 61: “Package with External Heat Sink 50 x 50 x 35 mm, 2s2p PCB, TA = 70° C, P = 1.723W,” on page 194
Table 62: “Package only, 2s2p PCB, TA = 55 °C, P = 1.723W,” on page 195
Table 63: “Package with External Heat Sink 19.x 19 x 5 mm, 2s2p PCB, TA = 55° C, P = 1.723W,” on page 195
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BCM53134M Data Sheet
Multiport Ultra Low-Power Gigabit Ethernet Switch
Added:
“JTAG Interface” on page 190
53134M-DS100-DS100; December 18, 2015
Initial release.
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Technologies, Avago, and the A logo are among the trademarks of Broadcom and/or its affiliates in the United States, certain
other countries, and/or the EU.
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The term “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. For more information, please visit www.broadcom.com.
Broadcom reserves the right to make changes without further notice to any products or data herein to improve reliability,
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