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BCM8155FAIFBG

BCM8155FAIFBG

  • 厂商:

    AVAGO(博通)

  • 封装:

  • 描述:

    MULTIRATE (8G?11.352G) 10 GBPS R

  • 数据手册
  • 价格&库存
BCM8155FAIFBG 数据手册
BCM8155 ® Multirate Low-Power 10G RZ/NRZ/Duo-binary Transceiver with 10G Clock FEATURES • Fully integrated multirate CDR, DEMUX, MUX, CMU • 300-pin Multisource Agreement (MSA) compatible • Compliant with ITU GR-253, XFP, and SFP+ specifications • 16-bit LVDS interface compliant with Optical Internetworking Forum (OIF) SFI-4 • Programmable RZ/NRZ/Duo-binary modes • Adjustable duty cycle in RZ mode • RX equalization for ISI compensation • Limiting amplifier • RX phase adjustment • Adaptable RX decision threshold adjustment • 10G serial transmit clock output with adjustable phase • 10G serial TX preemphasis • PRBS generator/checker for built-in self-test (BIST) • Line and system loopback modes SUMMARY OF BENEFITS • Enhanced capability for long haul transmission with the ability to enable RZ modulation on the transmitter • Compliant with OIF, Telcordia®, ITU-T, XFI specification, and IEEE 802.3ae standards • Input sensitivity 10 mV peak-to-peak • Rates supported from 8.5 Gbps to 11.352 Gbps • Fault isolation with loopbacks, pattern generator, and checker • Reduces design cycle and time-to-market • High-level of integration allows for higher port density solutions. • Lowest power SFI-4 to 10G serial transceiver • Standard CMOS 65 nm fabrication process APPLICATIONS • Receiver and transmitter serial data polarity inversion • LVDS polarity inversion and bit order reversal • OC-192/STM-64/10-GbE/FEC transmission equipment • Analog loss-of-signal output (ALOSB) and loss-of-signal input (LOSIB) • SONET/SDH/10-GbE/10FC/FEC for RZ, NRZ or duo- • CMU and CDR lock detect • FIFO overflow alarm binary optical modules • ADD/DROP multiplexers • Reference clock: 1/16 or 1/64 of the line data rate • Digital cross-connects • Selectable RX clock and RX data squelch • ATM switch backbone • Selectable timing modes/cleanup are field-configurable • SONET/SDH/10-GbE/10FC/FEC for NRZ, RZ, or duo- • Internal phase detector and charge pump for cleanup phaselocked loop (PLL) (external VCXO required) • Broadcom Serial Control (BSC) interface compatible with Philips® I2C standard • Optional SPI interface • Core voltage, 1V • Low power: 600 mW binary test equipment • Terabit and edge routers OVERVIEW System Interface Line Interface +1.0V Differential Externally AC-Coupled Internally Biased Reference Clock Inputs TXREFCLKP/N RXREFCLKP/N VCXOP/N Reference Clock Outputs TXPCLKP/N TXMCLKP/N RXMCLKP/N Transmitter Parallel Inputs TXPICLKP/N TXDIN[15:0]P/N Receiver Parallel Outputs RXPOCLKP/N RXDOUT[15:0]P/N Filter and Bias Inputs TXVCP/N RXVCP/N RDINCM OFFSETP/N Clean-up PLL Charge Pump Output PHDOUT Resistor Calibration Reference RB_CAL RB_CAL_VSS Status Outputs TXFIFOERRB TXLOCKERRB PHDLOCKERRB ALOSB RXFIFOERRB RXLOCKERRB +3.3V CMOS Control Inputs RESETB LOSIB TXREFSEL SPI_SEL +3.3V CMOS BSC SDA SCL ADR[2:0] +1.0V LVDS +1.8V/2.3V LVDS +1.0V Differential CML Externally AC-Coupled TSDP/N TSCLKP/N Transmit Serial Outputs +1.0V Differential CML Externally AC-Coupled Internally Biased RDINP/N Receive Serial Input +1.0V Differential CML Externally AC-Coupled Internally Biased AUXP/N Auxillary Input Bypass +1.0V LVDS +1.0V Analog +3.3V Analog Connect 4.75-k resistor between these two pins Open Drain CMOS +1.0V +1.8V +3.3V VSS BCM8155 Interface Block Diagram The BCM8155 is a fully integrated MSA-compatible multirate SONET/ SDH/10-GbE/Fibre-Channel/FEC transceiver operating at 8.5 Gbps, 9.1 Gbps, 9.953 Gbps, 10.3125 Gbps, 10.519 Gbps, 10.664 Gbps, 10.709 Gbps, 11.095 Gbps, 11.318 Gbps, or 11.352 Gbps. It supports RZ, NRZ, and duo-binary modulation formats. On-chip clock synthesis is performed by a high-frequency, low-jitter PLL, allowing the use of a low-frequency reference clock selectable to the line rate divided by 16 or 64. The 10G TX clock phase adjusts for clocked driver applications. An on-chip phase detector and charge pump, plus external VCXO, implements a cleanup PLL. This can attenuate jitter on the CDRrecovered clock for loop timing applications, or provide a low-jitter reference from a noisy system clock. SONET timing modes can employ the new BCM8155 architecture, making timing mode and cleanup functions user-selectable in the field rather than during manufacturing. This simplifies engineering and manufacturing requirements. The low-jitter LVDS interface guarantees compliance with the bit error rate requirements of the Telcordia (formerly Bellcore), ANSI, and ITUT standards. New features added to the BCM8155 include: • Selectable RZ, NRZ and DB modulation • Rates from 8.5 Gbps to 11.352 Gbps • PRBS generator/checker for BIST • Adaptive decision threshold adjustment • Adjustable 10G TX clock phase • 10G RX equalization for ISI compensation • 10G TX preemphasis • Differential duo-binary precoder • BSC interface (compatible with Philips I2C standard) or optional SPI interface The BCM8155 is offered in two different packages: 1. 12 mm x 12 mm, 196-pin BGA (0.8 mm ball pitch) 2. 15 mm x 15 mm, 196-pin BGA (1 mm ball pitch) Broadcom®, the pulse logo, Connecting everything®, and the Connecting everything logo are among the trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/or the EU. Any other trademarks or trade names mentioned are the property of their respective owners. ® BROADCOM CORPORATION 5300 California Avenue, Irvine, California 92617 © 2008 by BROADCOM CORPORATION. All rights reserved. 8155-PB00-R 11/21/08 Phone: 949-926-5000 Fax: 949-926-5203 E-mail: info@broadcom.com Web: www.broadcom.com
BCM8155FAIFBG 价格&库存

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