BCM8157AIFBG

BCM8157 ® MULTIRATE LOW-POWER 10G XFI TO SFI-4.1 TRANSCEIVER (8.5 GBPS–11.35 GBPS) FEATURES • Fully integrated multirate CDR, DEMUX, MUX, CMU • SONET-compliant serial interface • 300-pin Multisource Agreement (MSA)-compatible • Compliant to ITU GR-253, XFP, and SFP+ specifications • 16-bit LVDS interface compliant to Optical Internetworking Forum (OIF) SFI-4 • RX equalization for ISI compensation SUMMARY OF BENEFITS • Compliant to OIF, Telcordia®, ITU-T, XFI specification, and IEEE 802.3ae standards • Fault isolation with loopbacks, pattern generator, and checker • Reduces design cycle and time-to-market • High-level of integration allows for higher port density solutions. • Limiting amplifier • Lowest power SFI-4 to 10G serial transceiver • RX phase adjustment • Support for SFP+ and XFP modules • 10G serial TX preemphasis • Standard CMOS 65-nm fabrication process • PRBS generator/checker for built-in self-test (BIST) • Data rates from 8.5 Gbps to 11.352 Gbps • Pin compatible to the BCM8154 and BCM8156 • Support for 8.5G Fibre Channel • Line and system loopback modes APPLICATIONS • Receiver and transmitter serial data polarity inversion • LVDS polarity inversion and bit order reversal • OC-192/STM-64/10-GbE/FEC transmission equipment • Analog loss-of-signal output (ALOSB) and loss-of-signal input (LOSIB) • ADD/DROP multiplexers • CMU and CDR lock detect • Digital cross-connects • FIFO overflow alarm • ATM switch backbone • Reference clock: 1/16 or 1/64 of the line data rate • Terabit and edge routers • Selectable RX clock and RX data squelch • Multi-port XFP-based designs • Selectable timing modes/cleanup are field configurable • Internal phase detector and charge pump for cleanup phaselocked loop (PLL) (external VCXO required) • Broadcom Serial Control (BSC) interface compatible with Philips® I2C standard • Optional SPI interface • Core voltage, 1V • Low-power: 580 mW OVERVIEW System Interface Reference Clock Inputs TXREFCLKP/N RXREFCLKP/N VCXOP/N Reference Clock Outputs TXPCLKP/N TXMCLKP/N RXMCLKP/N Transmitter Parallel Inputs TXPICLKP/N TXDIN[15:0]P/N Receiver Parallel Outputs RXPOCLKP/N RXDOUT[15:0]P/N Filter and Bias Inputs TXVCP/N RXVCP/N RDINCM Clean-up PLL Charge Pump Output PHDOUT Line Interface +1.0V Differential Externally AC-Coupled Internally Biased +1.0V LVDS +1.8V/2.3V LVDS +1.0V Differential CML Externally AC-Coupled TSDP/N Transmit Serial Outputs +1.0V Differential CML Externally AC-Coupled Internally Biased RDINP/N Receive Serial Input +1.0V Differential CML Externally AC-Coupled Internally Biased AUXP/N Auxillary Input Bypass +1.0V LVDS +1.0V Analog +3.3V Analog Connect 4.75-k resistor between these two pins Resistor Calibration Reference RB_CAL RB_CAL_VSS Status Outputs TXFIFOERRB TXLOCKERRB PHDLOCKERRB ALOSB RXFIFOERRB RXLOCKERRB +3.3V CMOS Control Inputs RESETB LOSIB TXREFSEL SPI_SEL +3.3V CMOS BSC SDA SCL ADR[2:0] Open Drain CMOS +1.0V +1.8V +3.3V VSS BCM8157 Interface Block Diagram The BCM8157 is a fully integrated MSA-compatible multirate SONET/ SDH/10-GbE/Fibre-Channel/FEC transceiver operating at 8.5 Gbps, 9.15 Gbps, 9.953 Gbps, 10.3125 Gbps, 10.519 Gbps, 10.664 Gbps, 10.709 Gbps, 11.095 Gbps, 11.318 Gbps, or 11.352 Gbps. On-chip clock synthesis is performed by the high-frequency, low-jitter PLL, allowing the use of a low-frequency reference clock selectable to the line rate divided by either 16 or 64. The 10G TX clock phase is adjustable for clocked driver applications. An on-chip phase detector and charge pump plus external VCXO implement a cleanup PLL. The cleanup PLL can be used to attenuate jitter on the CDR recovered clock for loop timing applications or to provide a low-jitter reference clock from a noisy system clock. Any SONET timing mode may be configured with the new BCM8157 timing architecture, making the timing mode and cleanup functions user- selectable in the field rather than during manufacturing, therefore, simplifying engineering and manufacturing requirements. New features added to the BCM8157 include: • Support for 8.5G FC • PRBS generator/checker for BIST • 10G RX equalization for ISI compensation • 10G TX preemphasis • BSC interface (compatible with Philips I2C standard) or optional SPI interface The low-jitter LVDS interface guarantees compliance with the bit error rate requirements of the Telcordia, ANSI, and ITU-T standards. The BCM8157 is offered in three different packages: 1. 15 mm x 15 mm, 196-pin BGA (1-mm ball pitch) 2. 12 mm x 12 mm, 196-pin BGA (0.8-mm ball pitch) Broadcom®, the pulse logo, Connecting everything®, and the Connecting everything logo are among the trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/or the EU. Any other trademarks or trade names mentioned are the property of their respective owners. ® BROADCOM CORPORATION 5300 California Avenue, Irvine, California 92617 © 2008 by BROADCOM CORPORATION. All rights reserved. 8157-PB01-R 09/11/08 Phone: 949-926-5000 Fax: 949-926-5203 E-mail: info@broadcom.com Web: www.broadcom.com