BCM8724BIFBG

BCM8724 ® DUAL 10-GIGABIT ETHERNET XFI TO XAUI™ TRANSCEIVER FEATURES SUMMARY OF BENEFITS • Dual XFI to XAUI™ 10-GbE transceiver • Meets or exceeds IEEE 802.3ae • Fully integrated CMU, CDR, SerDes, limiting amplifier, and • Supports XFP/XFI and SFP+ interfaces EyeOpener™ • Dual 10-GbE PMD interfaces with phase adjust • PMD interface: serial 10.3125-Gbps CML • Dual four-lane XAUI interfaces (3.125 Gbps) • XAUI link synchronization/deskew • XAUI transmit pre-emphasis for transmission over backplanes • PCS 64B/66B scrambler/descrambler • Simplifies designing and routing high-density linecard applications with multiple 10-GbE optical interfaces with either XFP or SFP+ • Reduces space and power in multiport 10-GbE linecard applications • Based on a proven design that is compliant with 10-GbE interface standards • XGXS 8B/10B error detection ENDEC • Adjustable receive equalization on 10-GbE serial interfaces (EyeOpener™) • Loopback modes supporting IEEE standard modes • 802.3 Clause 45 management interface with extended indirect APPLICATIONS address register access • Built-In Self-Test (BIST) on the 10-GbE serial and XAUI interfaces • High-density 10-GbE linecards using either SFP+ or XFP optical modules • Power dissipation: 1.8W • LAN/MAN switch/routers • Core Supply : 1.2V, I/O – 3.3V • Hubs and repeaters • Packaged in a 19 mm x 19 mm Plastic BGA • Network interface cards (NICs) OVERVIEW XFP/SFP+ MAC/SWITCH BCM8724 PCS/PMA XGXS RS XAUI Interface 1 XGXS XFI 1 10.3125 Gbps XFP/SFP+ XAUI Interface 2 XFI 2 10.3125 Gbps MDC MDIO Management Interface BCM8724 Block Diagram The BCM8724 Ethernet LAN-PHY is a fully integrated dualserialization/deserialization (10.3125 Gbps) interface device performing the extension functions for a 10-gigabit serial Ethernet reconciliation sublayer (RS) interface. The XGXS, PCS, and PMA functions include 8B/10B coding, 64B/66B coding, SerDes, clock multiplication unit (CMU), and clock and data recovery (CDR). On-chip clock synthesis is performed by the high-frequency low-jitter phase-locked loops for the PMD and XAUI output retimers. Individual PMD and XAUI clock recovery is performed on the device by synchronizing directly to their respective incoming data streams. Elastic buffers are provided to allow the XAUI and PMD interfaces to operate in asynchronous configuration. Only an external 156.25-MHz oscillator is required for the reference clock input. The serial 10-GbE receiver includes an adjustable equalizer/EyeOpener that allows for compensation for long trace lengths in multichannel linecard applications. The BCM8724 is available in a 19 mm x 19 mm, 324-pin FBGA with a 1.0-mm ball pitch RoHS compliant package. Broadcom®, the pulse logo, Connecting everything®, and the Connecting everything logo are among the trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/or the EU. Any other trademarks or trade names mentioned are the property of their respective owners. ® BROADCOM CORPORATION 16215 Alton Parkway, P.O. Box 57013 Irvine, California 92619-7013 © 2007 by BROADCOM CORPORATION. All rights reserved. 8724-PB01-R 03/13/07 Phone: 949-450-8700 Fax: 949-450-8710 E-mail: info@broadcom.com Web: www.broadcom.com