BCM8725AIFBG

BCM8725 ® DUAL-CHANNEL SERIAL 10-GIGABIT ETHERNET/FIBRE CHANNEL TRANSCEIVER WITH WIS LAYER AND XAUI™ INTERFACE FEATURES SUMMARY OF BENEFITS • Two fully independent channels • Meets or exceeds IEEE 802.3ae • Pin compatible with the BCM8724 • Supports XFP/XFI and SFP+ interfaces • Integrated IEEE 802.3ae Clause 50 compliant WIS layer for • Simplifies designing and routing high-density line-card EOS/WAN applications • Support for XENPAK/X2 3.0 and XPAK MSA Optical Module standards • Support for 10-Gigabit Fibre Channel Draft, Rev 3.0 • Support for XFP/XFI/SFP+ (SFF-8431 revision 1.1) interfaces • Reference clock output for XFP module reference clock applications with multiple 10-GbE optical interfaces with either XFP or SFP+ • Reduces space and power in multiport 10-GbE line-card applications • Based on a proven design that is compliant with 10-GbE interface standards • Dual-channel LAN/WAN PHY • Fully integrated CMU, CDR, SerDes, Limiting Amplifier, EyeOpener®, and 4-lane XAUI™ interface • 10-GbE PMD interface phase adjust • XAUI link synchronization/deskew APPLICATIONS • XAUI transmit pre-emphasis for transmission over backplanes • PMD Transmit pre-emphasis for flexible placement of PHY • High-density 10-GbE line-cards using either SFP+ or XFP optical modules • Receive equalization on XAUI and 10-GbE serial interfaces • LAN/MAN/WAN switch/routers • Loss-of-signal detection • Hubs and repeaters • Loopback modes supporting IEEE standard modes • Network interface cards (NICs) • IEEE 802.3™ Clause 45 management interface with extended indirect address register access • Built-in self-test (BIST) and pseudo-random bit sequence (PRBS) generator/checker • Power dissipation: 2W • Core Supply - 1.2V, I/O - 3.3V OVERVIEW XFP/SFP+ MAC/SWITCH BCM8725 PCS/PMA XGXS RS XAUI Interface 1 XGXS XFI 1 9.953 Gbps/ 10.3125 Gbps/10.518 Gbps XFP/SFP+ XAUI Interface 2 XFI 2 9.953 Gbps/ 10.3125 Gbps/10.518 Gbps MDC MDIO Management Interface BCM8725 Block Diagram The BCM8725 Ethernet/Fibre Channel/SONET LAN/WAN PHY i s a fully integrated dual-channel serialization/deserialization (9.953 Gbps/ 10.3125 Gbps/10.5188 Gbps) interface device performing the extension functions for a 10 Gb serial Ethernet Reconciliation Sublayer (RS) interface. and XAUI clock recovery is performed on the device by synchronizing directly to their respective incoming data streams. Elastic buffers are provided to allow the PMD and XAUI interfaces to operate in asynchronous configuration. Only an external 155.52 MHz/156.25 MHz/159.38 MHz oscillator is required for the reference clock input. For WAN applications a WIS compliant framer with flexible clocking modes allows transmission of Ethernet traffic over a WAN network. Onchip clock synthesis is performed by the high-frequency low-jitter phaselocked loops for the PMD and XAUI output retimers. Individual PMD The BCM8725 is available in a 19 mm x 19 mm, 324-pin FBGA with 1mm ball-pitch RoHS-compliant package. Broadcom®, the pulse logo, Connecting everything®, the Connecting everything logo, and EyeOpener® are among the trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/or the EU. Any other trademarks or trade names mentioned are the property of their respective owners. ® BROADCOM CORPORATION 5300 California Avenue, Irvine, California 92617 © 2008 by BROADCOM CORPORATION. All rights reserved. 8725-PB00-R 04/15/08 Phone: 949-926-5000 Fax: 949-926-5203 E-mail: info@broadcom.com Web: www.broadcom.com